Overall: 4752/13205 fields covered

ADC

0x400c0000: Analog-to-Digital Converter

107/266 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MR
0x8 SEQR1
0xc SEQR2
0x10 CHER
0x14 CHDR
0x18 CHSR
0x20 LCDR
0x24 IER
0x28 IDR
0x2c IMR
0x30 ISR
0x3c OVER
0x40 EMR
0x44 CWR
0x48 CGR
0x4c COR
0x50 CDR[[0]]
0x54 CDR[[1]]
0x58 CDR[[2]]
0x5c CDR[[3]]
0x60 CDR[[4]]
0x64 CDR[[5]]
0x68 CDR[[6]]
0x6c CDR[[7]]
0x70 CDR[[8]]
0x74 CDR[[9]]
0x78 CDR[[10]]
0x7c CDR[[11]]
0x80 CDR[[12]]
0x84 CDR[[13]]
0x88 CDR[[14]]
0x8c CDR[[15]]
0x94 ACR
0xe4 WPMR
0xe8 WPSR
0x100 RPR
0x104 RCR
0x110 RNPR
0x114 RNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START
w 		SWRST
w
Toggle Fields

SWRST

Bit 0: Software Reset.

START

Bit 1: Start Conversion.

MR

Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

9/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USEQ
rw 		TRANSFER
rw 		TRACKTIM
rw 		ANACH
rw 		SETTLING
rw 		STARTUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCAL
rw 		FREERUN
rw 		FWUP
rw 		SLEEP
rw 		TRGSEL
rw 		TRGEN
rw
Toggle Fields

TRGEN

Bit 0: Trigger Enable.

Allowed values:
0: DIS: Hardware triggers are disabled. Starting a conversion is only possible by software.
1: EN: Hardware trigger selected by TRGSEL field is enabled.

TRGSEL

Bits 1-3: Trigger Selection.

Allowed values:
0x0: ADC_TRIG0: External : ADCTRG
0x1: ADC_TRIG1: TIOA Output of the Timer Counter Channel 0
0x2: ADC_TRIG2: TIOA Output of the Timer Counter Channel 1
0x3: ADC_TRIG3: TIOA Output of the Timer Counter Channel 2
0x4: ADC_TRIG4: PWM Event Line 0
0x5: ADC_TRIG5: PWM Event Line 0

SLEEP

Bit 5: Sleep Mode.

Allowed values:
0: NORMAL: Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
1: SLEEP: Sleep Mode: The wake-up time can be modified by programming FWUP bit

FWUP

Bit 6: Fast Wake Up.

Allowed values:
0: OFF: If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions
1: ON: If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF

FREERUN

Bit 7: Free Run Mode.

Allowed values:
0: OFF: Normal Mode
1: ON: Free Run Mode: Never wait for any trigger.

PRESCAL

Bits 8-15: Prescaler Rate Selection.

STARTUP

Bits 16-19: Start Up Time.

Allowed values:
0x0: SUT0: 0 periods of ADCClock
0x1: SUT8: 8 periods of ADCClock
0x2: SUT16: 16 periods of ADCClock
0x3: SUT24: 24 periods of ADCClock
0x4: SUT64: 64 periods of ADCClock
0x5: SUT80: 80 periods of ADCClock
0x6: SUT96: 96 periods of ADCClock
0x7: SUT112: 112 periods of ADCClock
0x8: SUT512: 512 periods of ADCClock
0x9: SUT576: 576 periods of ADCClock
0xA: SUT640: 640 periods of ADCClock
0xB: SUT704: 704 periods of ADCClock
0xC: SUT768: 768 periods of ADCClock
0xD: SUT832: 832 periods of ADCClock
0xE: SUT896: 896 periods of ADCClock
0xF: SUT960: 960 periods of ADCClock

SETTLING

Bits 20-21: Analog Settling Time.

Allowed values:
0x0: AST3: 3 periods of ADCClock
0x1: AST5: 5 periods of ADCClock
0x2: AST9: 9 periods of ADCClock
0x3: AST17: 17 periods of ADCClock

ANACH

Bit 23: Analog Change.

Allowed values:
0: NONE: No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels
1: ALLOWED: Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers

TRACKTIM

Bits 24-27: Tracking Time.

TRANSFER

Bits 28-29: Transfer Period.

USEQ

Bit 31: Use Sequence Enable.

Allowed values:
0: NUM_ORDER: Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.
1: REG_ORDER: User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel.

SEQR1

Channel Sequence Register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USCH8
rw 		USCH7
rw 		USCH6
rw 		USCH5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USCH4
rw 		USCH3
rw 		USCH2
rw 		USCH1
rw
Toggle Fields

USCH1

Bits 0-3: User Sequence Number 1.

USCH2

Bits 4-7: User Sequence Number 2.

USCH3

Bits 8-11: User Sequence Number 3.

USCH4

Bits 12-15: User Sequence Number 4.

USCH5

Bits 16-19: User Sequence Number 5.

USCH6

Bits 20-23: User Sequence Number 6.

USCH7

Bits 24-27: User Sequence Number 7.

USCH8

Bits 28-31: User Sequence Number 8.

SEQR2

Channel Sequence Register 2

Offset: 0xc, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USCH15
rw 		USCH14
rw 		USCH13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USCH12
rw 		USCH11
rw 		USCH10
rw 		USCH9
rw
Toggle Fields

USCH9

Bits 0-3: User Sequence Number 9.

USCH10

Bits 4-7: User Sequence Number 10.

USCH11

Bits 8-11: User Sequence Number 11.

USCH12

Bits 12-15: User Sequence Number 12.

USCH13

Bits 16-19: User Sequence Number 13.

USCH14

Bits 20-23: User Sequence Number 14.

USCH15

Bits 24-27: User Sequence Number 15.

CHER

Channel Enable Register

Offset: 0x10, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15
w 		CH14
w 		CH13
w 		CH12
w 		CH11
w 		CH10
w 		CH9
w 		CH8
w 		CH7
w 		CH6
w 		CH5
w 		CH4
w 		CH3
w 		CH2
w 		CH1
w 		CH0
w
Toggle Fields

CH0

Bit 0: Channel 0 Enable.

CH1

Bit 1: Channel 1 Enable.

CH2

Bit 2: Channel 2 Enable.

CH3

Bit 3: Channel 3 Enable.

CH4

Bit 4: Channel 4 Enable.

CH5

Bit 5: Channel 5 Enable.

CH6

Bit 6: Channel 6 Enable.

CH7

Bit 7: Channel 7 Enable.

CH8

Bit 8: Channel 8 Enable.

CH9

Bit 9: Channel 9 Enable.

CH10

Bit 10: Channel 10 Enable.

CH11

Bit 11: Channel 11 Enable.

CH12

Bit 12: Channel 12 Enable.

CH13

Bit 13: Channel 13 Enable.

CH14

Bit 14: Channel 14 Enable.

CH15

Bit 15: Channel 15 Enable.

CHDR

Channel Disable Register

Offset: 0x14, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15
w 		CH14
w 		CH13
w 		CH12
w 		CH11
w 		CH10
w 		CH9
w 		CH8
w 		CH7
w 		CH6
w 		CH5
w 		CH4
w 		CH3
w 		CH2
w 		CH1
w 		CH0
w
Toggle Fields

CH0

Bit 0: Channel 0 Disable.

CH1

Bit 1: Channel 1 Disable.

CH2

Bit 2: Channel 2 Disable.

CH3

Bit 3: Channel 3 Disable.

CH4

Bit 4: Channel 4 Disable.

CH5

Bit 5: Channel 5 Disable.

CH6

Bit 6: Channel 6 Disable.

CH7

Bit 7: Channel 7 Disable.

CH8

Bit 8: Channel 8 Disable.

CH9

Bit 9: Channel 9 Disable.

CH10

Bit 10: Channel 10 Disable.

CH11

Bit 11: Channel 11 Disable.

CH12

Bit 12: Channel 12 Disable.

CH13

Bit 13: Channel 13 Disable.

CH14

Bit 14: Channel 14 Disable.

CH15

Bit 15: Channel 15 Disable.

CHSR

Channel Status Register

Offset: 0x18, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15
r 		CH14
r 		CH13
r 		CH12
r 		CH11
r 		CH10
r 		CH9
r 		CH8
r 		CH7
r 		CH6
r 		CH5
r 		CH4
r 		CH3
r 		CH2
r 		CH1
r 		CH0
r
Toggle Fields

CH0

Bit 0: Channel 0 Status.

CH1

Bit 1: Channel 1 Status.

CH2

Bit 2: Channel 2 Status.

CH3

Bit 3: Channel 3 Status.

CH4

Bit 4: Channel 4 Status.

CH5

Bit 5: Channel 5 Status.

CH6

Bit 6: Channel 6 Status.

CH7

Bit 7: Channel 7 Status.

CH8

Bit 8: Channel 8 Status.

CH9

Bit 9: Channel 9 Status.

CH10

Bit 10: Channel 10 Status.

CH11

Bit 11: Channel 11 Status.

CH12

Bit 12: Channel 12 Status.

CH13

Bit 13: Channel 13 Status.

CH14

Bit 14: Channel 14 Status.

CH15

Bit 15: Channel 15 Status.

LCDR

Last Converted Data Register

Offset: 0x20, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNB
r 		LDATA
r
Toggle Fields

LDATA

Bits 0-11: Last Data Converted.

CHNB

Bits 12-15: Channel Number.

IER

Interrupt Enable Register

Offset: 0x24, reset: None, access: write-only

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXBUFF
w 		ENDRX
w 		COMPE
w 		GOVRE
w 		DRDY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOC15
w 		EOC14
w 		EOC13
w 		EOC12
w 		EOC11
w 		EOC10
w 		EOC9
w 		EOC8
w 		EOC7
w 		EOC6
w 		EOC5
w 		EOC4
w 		EOC3
w 		EOC2
w 		EOC1
w 		EOC0
w
Toggle Fields

EOC0

Bit 0: End of Conversion Interrupt Enable 0.

EOC1

Bit 1: End of Conversion Interrupt Enable 1.

EOC2

Bit 2: End of Conversion Interrupt Enable 2.

EOC3

Bit 3: End of Conversion Interrupt Enable 3.

EOC4

Bit 4: End of Conversion Interrupt Enable 4.

EOC5

Bit 5: End of Conversion Interrupt Enable 5.

EOC6

Bit 6: End of Conversion Interrupt Enable 6.

EOC7

Bit 7: End of Conversion Interrupt Enable 7.

EOC8

Bit 8: End of Conversion Interrupt Enable 8.

EOC9

Bit 9: End of Conversion Interrupt Enable 9.

EOC10

Bit 10: End of Conversion Interrupt Enable 10.

EOC11

Bit 11: End of Conversion Interrupt Enable 11.

EOC12

Bit 12: End of Conversion Interrupt Enable 12.

EOC13

Bit 13: End of Conversion Interrupt Enable 13.

EOC14

Bit 14: End of Conversion Interrupt Enable 14.

EOC15

Bit 15: End of Conversion Interrupt Enable 15.

DRDY

Bit 24: Data Ready Interrupt Enable.

GOVRE

Bit 25: General Overrun Error Interrupt Enable.

COMPE

Bit 26: Comparison Event Interrupt Enable.

ENDRX

Bit 27: End of Receive Buffer Interrupt Enable.

RXBUFF

Bit 28: Receive Buffer Full Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x28, reset: None, access: write-only

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXBUFF
w 		ENDRX
w 		COMPE
w 		GOVRE
w 		DRDY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOC15
w 		EOC14
w 		EOC13
w 		EOC12
w 		EOC11
w 		EOC10
w 		EOC9
w 		EOC8
w 		EOC7
w 		EOC6
w 		EOC5
w 		EOC4
w 		EOC3
w 		EOC2
w 		EOC1
w 		EOC0
w
Toggle Fields

EOC0

Bit 0: End of Conversion Interrupt Disable 0.

EOC1

Bit 1: End of Conversion Interrupt Disable 1.

EOC2

Bit 2: End of Conversion Interrupt Disable 2.

EOC3

Bit 3: End of Conversion Interrupt Disable 3.

EOC4

Bit 4: End of Conversion Interrupt Disable 4.

EOC5

Bit 5: End of Conversion Interrupt Disable 5.

EOC6

Bit 6: End of Conversion Interrupt Disable 6.

EOC7

Bit 7: End of Conversion Interrupt Disable 7.

EOC8

Bit 8: End of Conversion Interrupt Disable 8.

EOC9

Bit 9: End of Conversion Interrupt Disable 9.

EOC10

Bit 10: End of Conversion Interrupt Disable 10.

EOC11

Bit 11: End of Conversion Interrupt Disable 11.

EOC12

Bit 12: End of Conversion Interrupt Disable 12.

EOC13

Bit 13: End of Conversion Interrupt Disable 13.

EOC14

Bit 14: End of Conversion Interrupt Disable 14.

EOC15

Bit 15: End of Conversion Interrupt Disable 15.

DRDY

Bit 24: Data Ready Interrupt Disable.

GOVRE

Bit 25: General Overrun Error Interrupt Disable.

COMPE

Bit 26: Comparison Event Interrupt Disable.

ENDRX

Bit 27: End of Receive Buffer Interrupt Disable.

RXBUFF

Bit 28: Receive Buffer Full Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x2c, reset: 0x00000000, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXBUFF
r 		ENDRX
r 		COMPE
r 		GOVRE
r 		DRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOC15
r 		EOC14
r 		EOC13
r 		EOC12
r 		EOC11
r 		EOC10
r 		EOC9
r 		EOC8
r 		EOC7
r 		EOC6
r 		EOC5
r 		EOC4
r 		EOC3
r 		EOC2
r 		EOC1
r 		EOC0
r
Toggle Fields

EOC0

Bit 0: End of Conversion Interrupt Mask 0.

EOC1

Bit 1: End of Conversion Interrupt Mask 1.

EOC2

Bit 2: End of Conversion Interrupt Mask 2.

EOC3

Bit 3: End of Conversion Interrupt Mask 3.

EOC4

Bit 4: End of Conversion Interrupt Mask 4.

EOC5

Bit 5: End of Conversion Interrupt Mask 5.

EOC6

Bit 6: End of Conversion Interrupt Mask 6.

EOC7

Bit 7: End of Conversion Interrupt Mask 7.

EOC8

Bit 8: End of Conversion Interrupt Mask 8.

EOC9

Bit 9: End of Conversion Interrupt Mask 9.

EOC10

Bit 10: End of Conversion Interrupt Mask 10.

EOC11

Bit 11: End of Conversion Interrupt Mask 11.

EOC12

Bit 12: End of Conversion Interrupt Mask 12.

EOC13

Bit 13: End of Conversion Interrupt Mask 13.

EOC14

Bit 14: End of Conversion Interrupt Mask 14.

EOC15

Bit 15: End of Conversion Interrupt Mask 15.

DRDY

Bit 24: Data Ready Interrupt Mask.

GOVRE

Bit 25: General Overrun Error Interrupt Mask.

COMPE

Bit 26: Comparison Event Interrupt Mask.

ENDRX

Bit 27: End of Receive Buffer Interrupt Mask.

RXBUFF

Bit 28: Receive Buffer Full Interrupt Mask.

ISR

Interrupt Status Register

Offset: 0x30, reset: 0x00000000, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXBUFF
r 		ENDRX
r 		COMPE
r 		GOVRE
r 		DRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOC15
r 		EOC14
r 		EOC13
r 		EOC12
r 		EOC11
r 		EOC10
r 		EOC9
r 		EOC8
r 		EOC7
r 		EOC6
r 		EOC5
r 		EOC4
r 		EOC3
r 		EOC2
r 		EOC1
r 		EOC0
r
Toggle Fields

EOC0

Bit 0: End of Conversion 0.

EOC1

Bit 1: End of Conversion 1.

EOC2

Bit 2: End of Conversion 2.

EOC3

Bit 3: End of Conversion 3.

EOC4

Bit 4: End of Conversion 4.

EOC5

Bit 5: End of Conversion 5.

EOC6

Bit 6: End of Conversion 6.

EOC7

Bit 7: End of Conversion 7.

EOC8

Bit 8: End of Conversion 8.

EOC9

Bit 9: End of Conversion 9.

EOC10

Bit 10: End of Conversion 10.

EOC11

Bit 11: End of Conversion 11.

EOC12

Bit 12: End of Conversion 12.

EOC13

Bit 13: End of Conversion 13.

EOC14

Bit 14: End of Conversion 14.

EOC15

Bit 15: End of Conversion 15.

DRDY

Bit 24: Data Ready.

GOVRE

Bit 25: General Overrun Error.

COMPE

Bit 26: Comparison Error.

ENDRX

Bit 27: End of RX Buffer.

RXBUFF

Bit 28: RX Buffer Full.

OVER

Overrun Status Register

Offset: 0x3c, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVRE15
r 		OVRE14
r 		OVRE13
r 		OVRE12
r 		OVRE11
r 		OVRE10
r 		OVRE9
r 		OVRE8
r 		OVRE7
r 		OVRE6
r 		OVRE5
r 		OVRE4
r 		OVRE3
r 		OVRE2
r 		OVRE1
r 		OVRE0
r
Toggle Fields

OVRE0

Bit 0: Overrun Error 0.

OVRE1

Bit 1: Overrun Error 1.

OVRE2

Bit 2: Overrun Error 2.

OVRE3

Bit 3: Overrun Error 3.

OVRE4

Bit 4: Overrun Error 4.

OVRE5

Bit 5: Overrun Error 5.

OVRE6

Bit 6: Overrun Error 6.

OVRE7

Bit 7: Overrun Error 7.

OVRE8

Bit 8: Overrun Error 8.

OVRE9

Bit 9: Overrun Error 9.

OVRE10

Bit 10: Overrun Error 10.

OVRE11

Bit 11: Overrun Error 11.

OVRE12

Bit 12: Overrun Error 12.

OVRE13

Bit 13: Overrun Error 13.

OVRE14

Bit 14: Overrun Error 14.

OVRE15

Bit 15: Overrun Error 15.

EMR

Extended Mode Register

Offset: 0x40, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPFILTER
rw 		CMPALL
rw 		CMPSEL
rw 		CMPMODE
rw
Toggle Fields

CMPMODE

Bits 0-1: Comparison Mode.

Allowed values:
0x0: LOW: Generates an event when the converted data is lower than the low threshold of the window.
0x1: HIGH: Generates an event when the converted data is higher than the high threshold of the window.
0x2: IN: Generates an event when the converted data is in the comparison window.
0x3: OUT: Generates an event when the converted data is out of the comparison window.

CMPSEL

Bits 4-7: Comparison Selected Channel.

CMPALL

Bit 9: Compare All Channels.

CMPFILTER

Bits 12-13: Compare Event Filtering.

TAG

Bit 24: TAG of the ADC_LDCR register.

CWR

Compare Window Register

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HIGHTHRES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOWTHRES
rw
Toggle Fields

LOWTHRES

Bits 0-11: Low Threshold.

HIGHTHRES

Bits 16-27: High Threshold.

CGR

Channel Gain Register

Offset: 0x48, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GAIN15
rw 		GAIN14
rw 		GAIN13
rw 		GAIN12
rw 		GAIN11
rw 		GAIN10
rw 		GAIN9
rw 		GAIN8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GAIN7
rw 		GAIN6
rw 		GAIN5
rw 		GAIN4
rw 		GAIN3
rw 		GAIN2
rw 		GAIN1
rw 		GAIN0
rw
Toggle Fields

GAIN0

Bits 0-1: Gain for Channel 0.

GAIN1

Bits 2-3: Gain for Channel 1.

GAIN2

Bits 4-5: Gain for Channel 2.

GAIN3

Bits 6-7: Gain for Channel 3.

GAIN4

Bits 8-9: Gain for Channel 4.

GAIN5

Bits 10-11: Gain for Channel 5.

GAIN6

Bits 12-13: Gain for Channel 6.

GAIN7

Bits 14-15: Gain for Channel 7.

GAIN8

Bits 16-17: Gain for Channel 8.

GAIN9

Bits 18-19: Gain for Channel 9.

GAIN10

Bits 20-21: Gain for Channel 10.

GAIN11

Bits 22-23: Gain for Channel 11.

GAIN12

Bits 24-25: Gain for Channel 12.

GAIN13

Bits 26-27: Gain for Channel 13.

GAIN14

Bits 28-29: Gain for Channel 14.

GAIN15

Bits 30-31: Gain for Channel 15.

COR

Channel Offset Register

Offset: 0x4c, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFF15
rw 		DIFF14
rw 		DIFF13
rw 		DIFF12
rw 		DIFF11
rw 		DIFF10
rw 		DIFF9
rw 		DIFF8
rw 		DIFF7
rw 		DIFF6
rw 		DIFF5
rw 		DIFF4
rw 		DIFF3
rw 		DIFF2
rw 		DIFF1
rw 		DIFF0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFF15
rw 		OFF14
rw 		OFF13
rw 		OFF12
rw 		OFF11
rw 		OFF10
rw 		OFF9
rw 		OFF8
rw 		OFF7
rw 		OFF6
rw 		OFF5
rw 		OFF4
rw 		OFF3
rw 		OFF2
rw 		OFF1
rw 		OFF0
rw
Toggle Fields

OFF0

Bit 0: Offset for channel 0.

OFF1

Bit 1: Offset for channel 1.

OFF2

Bit 2: Offset for channel 2.

OFF3

Bit 3: Offset for channel 3.

OFF4

Bit 4: Offset for channel 4.

OFF5

Bit 5: Offset for channel 5.

OFF6

Bit 6: Offset for channel 6.

OFF7

Bit 7: Offset for channel 7.

OFF8

Bit 8: Offset for channel 8.

OFF9

Bit 9: Offset for channel 9.

OFF10

Bit 10: Offset for channel 10.

OFF11

Bit 11: Offset for channel 11.

OFF12

Bit 12: Offset for channel 12.

OFF13

Bit 13: Offset for channel 13.

OFF14

Bit 14: Offset for channel 14.

OFF15

Bit 15: Offset for channel 15.

DIFF0

Bit 16: Differential inputs for channel 0.

DIFF1

Bit 17: Differential inputs for channel 1.

DIFF2

Bit 18: Differential inputs for channel 2.

DIFF3

Bit 19: Differential inputs for channel 3.

DIFF4

Bit 20: Differential inputs for channel 4.

DIFF5

Bit 21: Differential inputs for channel 5.

DIFF6

Bit 22: Differential inputs for channel 6.

DIFF7

Bit 23: Differential inputs for channel 7.

DIFF8

Bit 24: Differential inputs for channel 8.

DIFF9

Bit 25: Differential inputs for channel 9.

DIFF10

Bit 26: Differential inputs for channel 10.

DIFF11

Bit 27: Differential inputs for channel 11.

DIFF12

Bit 28: Differential inputs for channel 12.

DIFF13

Bit 29: Differential inputs for channel 13.

DIFF14

Bit 30: Differential inputs for channel 14.

DIFF15

Bit 31: Differential inputs for channel 15.

CDR[[0]]

Channel Data Register

Offset: 0x50, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[1]]

Channel Data Register

Offset: 0x54, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[2]]

Channel Data Register

Offset: 0x58, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[3]]

Channel Data Register

Offset: 0x5c, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[4]]

Channel Data Register

Offset: 0x60, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[5]]

Channel Data Register

Offset: 0x64, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[6]]

Channel Data Register

Offset: 0x68, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[7]]

Channel Data Register

Offset: 0x6c, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[8]]

Channel Data Register

Offset: 0x70, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[9]]

Channel Data Register

Offset: 0x74, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[10]]

Channel Data Register

Offset: 0x78, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[11]]

Channel Data Register

Offset: 0x7c, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[12]]

Channel Data Register

Offset: 0x80, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[13]]

Channel Data Register

Offset: 0x84, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[14]]

Channel Data Register

Offset: 0x88, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

CDR[[15]]

Channel Data Register

Offset: 0x8c, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-11: Converted Data.

ACR

Analog Control Register

Offset: 0x94, reset: 0x00000100, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IBCTL
rw 		TSON
rw
Toggle Fields

TSON

Bit 4: Temperature Sensor On.

IBCTL

Bits 8-9: ADC Bias Current Control.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x414443: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

CAN0

0x400b4000: Controller Area Network 0

117/303 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MR
0x4 IER
0x8 IDR
0xc IMR
0x10 SR
0x14 BR
0x18 TIM
0x1c TIMESTP
0x20 ECR
0x24 TCR
0x28 ACR
0xe4 WPMR
0xe8 WPSR
0x200 MMR0
0x204 MAM0
0x208 MID0
0x20c MFID0
0x210 MSR0
0x214 MDL0
0x218 MDH0
0x21c MCR0
0x220 MMR1
0x224 MAM1
0x228 MID1
0x22c MFID1
0x230 MSR1
0x234 MDL1
0x238 MDH1
0x23c MCR1
0x240 MMR2
0x244 MAM2
0x248 MID2
0x24c MFID2
0x250 MSR2
0x254 MDL2
0x258 MDH2
0x25c MCR2
0x260 MMR3
0x264 MAM3
0x268 MID3
0x26c MFID3
0x270 MSR3
0x274 MDL3
0x278 MDH3
0x27c MCR3
0x280 MMR4
0x284 MAM4
0x288 MID4
0x28c MFID4
0x290 MSR4
0x294 MDL4
0x298 MDH4
0x29c MCR4
0x2a0 MMR5
0x2a4 MAM5
0x2a8 MID5
0x2ac MFID5
0x2b0 MSR5
0x2b4 MDL5
0x2b8 MDH5
0x2bc MCR5
0x2c0 MMR6
0x2c4 MAM6
0x2c8 MID6
0x2cc MFID6
0x2d0 MSR6
0x2d4 MDL6
0x2d8 MDH6
0x2dc MCR6
0x2e0 MMR7
0x2e4 MAM7
0x2e8 MID7
0x2ec MFID7
0x2f0 MSR7
0x2f4 MDL7
0x2f8 MDH7
0x2fc MCR7

MR

Mode Register

Offset: 0x0, reset: 0x00000000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSYNC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRPT
rw 		TIMFRZ
rw 		TTM
rw 		TEOF
rw 		OVL
rw 		ABM
rw 		LPM
rw 		CANEN
rw
Toggle Fields

CANEN

Bit 0: CAN Controller Enable.

LPM

Bit 1: Disable/Enable Low Power Mode.

ABM

Bit 2: Disable/Enable Autobaud/Listen mode.

OVL

Bit 3: Disable/Enable Overload Frame.

TEOF

Bit 4: Timestamp messages at each end of Frame.

TTM

Bit 5: Disable/Enable Time Triggered Mode.

TIMFRZ

Bit 6: Enable Timer Freeze.

DRPT

Bit 7: Disable Repeat.

RXSYNC

Bits 24-26: Reception Synchronization Stage (not readable).

Allowed values:
0x0: DOUBLE_PP: Rx Signal with Double Synchro Stages (2 Positive Edges)
0x1: DOUBLE_PN: Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge)
0x2: SINGLE_P: Rx Signal with Single Synchro Stage (Positive Edge)
0x3: NONE: Rx Signal with No Synchro Stage

IER

Interrupt Enable Register

Offset: 0x4, reset: None, access: write-only

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BERR
w 		FERR
w 		AERR
w 		SERR
w 		CERR
w 		TSTP
w 		TOVF
w 		WAKEUP
w 		SLEEP
w 		BOFF
w 		ERRP
w 		WARN
w 		ERRA
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Mailbox 0 Interrupt Enable.

MB1

Bit 1: Mailbox 1 Interrupt Enable.

MB2

Bit 2: Mailbox 2 Interrupt Enable.

MB3

Bit 3: Mailbox 3 Interrupt Enable.

MB4

Bit 4: Mailbox 4 Interrupt Enable.

MB5

Bit 5: Mailbox 5 Interrupt Enable.

MB6

Bit 6: Mailbox 6 Interrupt Enable.

MB7

Bit 7: Mailbox 7 Interrupt Enable.

ERRA

Bit 16: Error Active Mode Interrupt Enable.

WARN

Bit 17: Warning Limit Interrupt Enable.

ERRP

Bit 18: Error Passive Mode Interrupt Enable.

BOFF

Bit 19: Bus Off Mode Interrupt Enable.

SLEEP

Bit 20: Sleep Interrupt Enable.

WAKEUP

Bit 21: Wakeup Interrupt Enable.

TOVF

Bit 22: Timer Overflow Interrupt Enable.

TSTP

Bit 23: TimeStamp Interrupt Enable.

CERR

Bit 24: CRC Error Interrupt Enable.

SERR

Bit 25: Stuffing Error Interrupt Enable.

AERR

Bit 26: Acknowledgment Error Interrupt Enable.

FERR

Bit 27: Form Error Interrupt Enable.

BERR

Bit 28: Bit Error Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x8, reset: None, access: write-only

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BERR
w 		FERR
w 		AERR
w 		SERR
w 		CERR
w 		TSTP
w 		TOVF
w 		WAKEUP
w 		SLEEP
w 		BOFF
w 		ERRP
w 		WARN
w 		ERRA
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Mailbox 0 Interrupt Disable.

MB1

Bit 1: Mailbox 1 Interrupt Disable.

MB2

Bit 2: Mailbox 2 Interrupt Disable.

MB3

Bit 3: Mailbox 3 Interrupt Disable.

MB4

Bit 4: Mailbox 4 Interrupt Disable.

MB5

Bit 5: Mailbox 5 Interrupt Disable.

MB6

Bit 6: Mailbox 6 Interrupt Disable.

MB7

Bit 7: Mailbox 7 Interrupt Disable.

ERRA

Bit 16: Error Active Mode Interrupt Disable.

WARN

Bit 17: Warning Limit Interrupt Disable.

ERRP

Bit 18: Error Passive Mode Interrupt Disable.

BOFF

Bit 19: Bus Off Mode Interrupt Disable.

SLEEP

Bit 20: Sleep Interrupt Disable.

WAKEUP

Bit 21: Wakeup Interrupt Disable.

TOVF

Bit 22: Timer Overflow Interrupt.

TSTP

Bit 23: TimeStamp Interrupt Disable.

CERR

Bit 24: CRC Error Interrupt Disable.

SERR

Bit 25: Stuffing Error Interrupt Disable.

AERR

Bit 26: Acknowledgment Error Interrupt Disable.

FERR

Bit 27: Form Error Interrupt Disable.

BERR

Bit 28: Bit Error Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0xc, reset: 0x00000000, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BERR
r 		FERR
r 		AERR
r 		SERR
r 		CERR
r 		TSTP
r 		TOVF
r 		WAKEUP
r 		SLEEP
r 		BOFF
r 		ERRP
r 		WARN
r 		ERRA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
r 		MB6
r 		MB5
r 		MB4
r 		MB3
r 		MB2
r 		MB1
r 		MB0
r
Toggle Fields

MB0

Bit 0: Mailbox 0 Interrupt Mask.

MB1

Bit 1: Mailbox 1 Interrupt Mask.

MB2

Bit 2: Mailbox 2 Interrupt Mask.

MB3

Bit 3: Mailbox 3 Interrupt Mask.

MB4

Bit 4: Mailbox 4 Interrupt Mask.

MB5

Bit 5: Mailbox 5 Interrupt Mask.

MB6

Bit 6: Mailbox 6 Interrupt Mask.

MB7

Bit 7: Mailbox 7 Interrupt Mask.

ERRA

Bit 16: Error Active Mode Interrupt Mask.

WARN

Bit 17: Warning Limit Interrupt Mask.

ERRP

Bit 18: Error Passive Mode Interrupt Mask.

BOFF

Bit 19: Bus Off Mode Interrupt Mask.

SLEEP

Bit 20: Sleep Interrupt Mask.

WAKEUP

Bit 21: Wakeup Interrupt Mask.

TOVF

Bit 22: Timer Overflow Interrupt Mask.

TSTP

Bit 23: Timestamp Interrupt Mask.

CERR

Bit 24: CRC Error Interrupt Mask.

SERR

Bit 25: Stuffing Error Interrupt Mask.

AERR

Bit 26: Acknowledgment Error Interrupt Mask.

FERR

Bit 27: Form Error Interrupt Mask.

BERR

Bit 28: Bit Error Interrupt Mask.

SR

Status Register

Offset: 0x10, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVLSY
r 		TBSY
r 		RBSY
r 		BERR
r 		FERR
r 		AERR
r 		SERR
r 		CERR
r 		TSTP
r 		TOVF
r 		WAKEUP
r 		SLEEP
r 		BOFF
r 		ERRP
r 		WARN
r 		ERRA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
r 		MB6
r 		MB5
r 		MB4
r 		MB3
r 		MB2
r 		MB1
r 		MB0
r
Toggle Fields

MB0

Bit 0: Mailbox 0 Event.

MB1

Bit 1: Mailbox 1 Event.

MB2

Bit 2: Mailbox 2 Event.

MB3

Bit 3: Mailbox 3 Event.

MB4

Bit 4: Mailbox 4 Event.

MB5

Bit 5: Mailbox 5 Event.

MB6

Bit 6: Mailbox 6 Event.

MB7

Bit 7: Mailbox 7 Event.

ERRA

Bit 16: Error Active Mode.

WARN

Bit 17: Warning Limit.

ERRP

Bit 18: Error Passive Mode.

BOFF

Bit 19: Bus Off Mode.

SLEEP

Bit 20: CAN controller in Low power Mode.

WAKEUP

Bit 21: CAN controller is not in Low power Mode.

TOVF

Bit 22: Timer Overflow.

TSTP

Bit 23: None.

CERR

Bit 24: Mailbox CRC Error.

SERR

Bit 25: Mailbox Stuffing Error.

AERR

Bit 26: Acknowledgment Error.

FERR

Bit 27: Form Error.

BERR

Bit 28: Bit Error.

RBSY

Bit 29: Receiver busy.

TBSY

Bit 30: Transmitter busy.

OVLSY

Bit 31: Overload busy.

BR

Baudrate Register

Offset: 0x14, reset: 0x00000000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP
rw 		BRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SJW
rw 		PROPAG
rw 		PHASE1
rw 		PHASE2
rw
Toggle Fields

PHASE2

Bits 0-2: Phase 2 segment.

PHASE1

Bits 4-6: Phase 1 segment.

PROPAG

Bits 8-10: Programming time segment.

SJW

Bits 12-13: Re-synchronization jump width.

BRP

Bits 16-22: Baudrate Prescaler..

SMP

Bit 24: Sampling Mode.

Allowed values:
0: ONCE: The incoming bit stream is sampled once at sample point.
1: THREE: The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.

TIM

Timer Register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER
r
Toggle Fields

TIMER

Bits 0-15: Timer.

TIMESTP

Timestamp Register

Offset: 0x1c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timestamp.

ECR

Error Counter Register

Offset: 0x20, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REC
r
Toggle Fields

REC

Bits 0-7: Receive Error Counter.

TEC

Bits 16-23: Transmit Error Counter.

TCR

Transfer Command Register

Offset: 0x24, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMRST
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Transfer Request for Mailbox 0.

MB1

Bit 1: Transfer Request for Mailbox 1.

MB2

Bit 2: Transfer Request for Mailbox 2.

MB3

Bit 3: Transfer Request for Mailbox 3.

MB4

Bit 4: Transfer Request for Mailbox 4.

MB5

Bit 5: Transfer Request for Mailbox 5.

MB6

Bit 6: Transfer Request for Mailbox 6.

MB7

Bit 7: Transfer Request for Mailbox 7.

TIMRST

Bit 31: Timer Reset.

ACR

Abort Command Register

Offset: 0x28, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Abort Request for Mailbox 0.

MB1

Bit 1: Abort Request for Mailbox 1.

MB2

Bit 2: Abort Request for Mailbox 2.

MB3

Bit 3: Abort Request for Mailbox 3.

MB4

Bit 4: Abort Request for Mailbox 4.

MB5

Bit 5: Abort Request for Mailbox 5.

MB6

Bit 6: Abort Request for Mailbox 6.

MB7

Bit 7: Abort Request for Mailbox 7.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protection Enable.

WPKEY

Bits 8-31: SPI Write Protection Key Password.

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-15: Write Protection Violation Source.

MMR0

Mailbox Mode Register (MB = 0)

Offset: 0x200, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM0

Mailbox Acceptance Mask Register (MB = 0)

Offset: 0x204, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID0

Mailbox ID Register (MB = 0)

Offset: 0x208, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID0

Mailbox Family ID Register (MB = 0)

Offset: 0x20c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR0

Mailbox Status Register (MB = 0)

Offset: 0x210, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL0

Mailbox Data Low Register (MB = 0)

Offset: 0x214, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH0

Mailbox Data High Register (MB = 0)

Offset: 0x218, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR0

Mailbox Control Register (MB = 0)

Offset: 0x21c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR1

Mailbox Mode Register (MB = 1)

Offset: 0x220, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM1

Mailbox Acceptance Mask Register (MB = 1)

Offset: 0x224, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID1

Mailbox ID Register (MB = 1)

Offset: 0x228, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID1

Mailbox Family ID Register (MB = 1)

Offset: 0x22c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR1

Mailbox Status Register (MB = 1)

Offset: 0x230, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL1

Mailbox Data Low Register (MB = 1)

Offset: 0x234, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH1

Mailbox Data High Register (MB = 1)

Offset: 0x238, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR1

Mailbox Control Register (MB = 1)

Offset: 0x23c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR2

Mailbox Mode Register (MB = 2)

Offset: 0x240, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM2

Mailbox Acceptance Mask Register (MB = 2)

Offset: 0x244, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID2

Mailbox ID Register (MB = 2)

Offset: 0x248, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID2

Mailbox Family ID Register (MB = 2)

Offset: 0x24c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR2

Mailbox Status Register (MB = 2)

Offset: 0x250, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL2

Mailbox Data Low Register (MB = 2)

Offset: 0x254, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH2

Mailbox Data High Register (MB = 2)

Offset: 0x258, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR2

Mailbox Control Register (MB = 2)

Offset: 0x25c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR3

Mailbox Mode Register (MB = 3)

Offset: 0x260, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM3

Mailbox Acceptance Mask Register (MB = 3)

Offset: 0x264, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID3

Mailbox ID Register (MB = 3)

Offset: 0x268, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID3

Mailbox Family ID Register (MB = 3)

Offset: 0x26c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR3

Mailbox Status Register (MB = 3)

Offset: 0x270, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL3

Mailbox Data Low Register (MB = 3)

Offset: 0x274, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH3

Mailbox Data High Register (MB = 3)

Offset: 0x278, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR3

Mailbox Control Register (MB = 3)

Offset: 0x27c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR4

Mailbox Mode Register (MB = 4)

Offset: 0x280, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM4

Mailbox Acceptance Mask Register (MB = 4)

Offset: 0x284, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID4

Mailbox ID Register (MB = 4)

Offset: 0x288, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID4

Mailbox Family ID Register (MB = 4)

Offset: 0x28c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR4

Mailbox Status Register (MB = 4)

Offset: 0x290, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL4

Mailbox Data Low Register (MB = 4)

Offset: 0x294, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH4

Mailbox Data High Register (MB = 4)

Offset: 0x298, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR4

Mailbox Control Register (MB = 4)

Offset: 0x29c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR5

Mailbox Mode Register (MB = 5)

Offset: 0x2a0, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM5

Mailbox Acceptance Mask Register (MB = 5)

Offset: 0x2a4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID5

Mailbox ID Register (MB = 5)

Offset: 0x2a8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID5

Mailbox Family ID Register (MB = 5)

Offset: 0x2ac, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR5

Mailbox Status Register (MB = 5)

Offset: 0x2b0, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL5

Mailbox Data Low Register (MB = 5)

Offset: 0x2b4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH5

Mailbox Data High Register (MB = 5)

Offset: 0x2b8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR5

Mailbox Control Register (MB = 5)

Offset: 0x2bc, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR6

Mailbox Mode Register (MB = 6)

Offset: 0x2c0, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM6

Mailbox Acceptance Mask Register (MB = 6)

Offset: 0x2c4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID6

Mailbox ID Register (MB = 6)

Offset: 0x2c8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID6

Mailbox Family ID Register (MB = 6)

Offset: 0x2cc, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR6

Mailbox Status Register (MB = 6)

Offset: 0x2d0, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL6

Mailbox Data Low Register (MB = 6)

Offset: 0x2d4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH6

Mailbox Data High Register (MB = 6)

Offset: 0x2d8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR6

Mailbox Control Register (MB = 6)

Offset: 0x2dc, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR7

Mailbox Mode Register (MB = 7)

Offset: 0x2e0, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM7

Mailbox Acceptance Mask Register (MB = 7)

Offset: 0x2e4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID7

Mailbox ID Register (MB = 7)

Offset: 0x2e8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID7

Mailbox Family ID Register (MB = 7)

Offset: 0x2ec, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR7

Mailbox Status Register (MB = 7)

Offset: 0x2f0, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL7

Mailbox Data Low Register (MB = 7)

Offset: 0x2f4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH7

Mailbox Data High Register (MB = 7)

Offset: 0x2f8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR7

Mailbox Control Register (MB = 7)

Offset: 0x2fc, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

CAN1

0x400b8000: Controller Area Network 1

117/303 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MR
0x4 IER
0x8 IDR
0xc IMR
0x10 SR
0x14 BR
0x18 TIM
0x1c TIMESTP
0x20 ECR
0x24 TCR
0x28 ACR
0xe4 WPMR
0xe8 WPSR
0x200 MMR0
0x204 MAM0
0x208 MID0
0x20c MFID0
0x210 MSR0
0x214 MDL0
0x218 MDH0
0x21c MCR0
0x220 MMR1
0x224 MAM1
0x228 MID1
0x22c MFID1
0x230 MSR1
0x234 MDL1
0x238 MDH1
0x23c MCR1
0x240 MMR2
0x244 MAM2
0x248 MID2
0x24c MFID2
0x250 MSR2
0x254 MDL2
0x258 MDH2
0x25c MCR2
0x260 MMR3
0x264 MAM3
0x268 MID3
0x26c MFID3
0x270 MSR3
0x274 MDL3
0x278 MDH3
0x27c MCR3
0x280 MMR4
0x284 MAM4
0x288 MID4
0x28c MFID4
0x290 MSR4
0x294 MDL4
0x298 MDH4
0x29c MCR4
0x2a0 MMR5
0x2a4 MAM5
0x2a8 MID5
0x2ac MFID5
0x2b0 MSR5
0x2b4 MDL5
0x2b8 MDH5
0x2bc MCR5
0x2c0 MMR6
0x2c4 MAM6
0x2c8 MID6
0x2cc MFID6
0x2d0 MSR6
0x2d4 MDL6
0x2d8 MDH6
0x2dc MCR6
0x2e0 MMR7
0x2e4 MAM7
0x2e8 MID7
0x2ec MFID7
0x2f0 MSR7
0x2f4 MDL7
0x2f8 MDH7
0x2fc MCR7

MR

Mode Register

Offset: 0x0, reset: 0x00000000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSYNC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRPT
rw 		TIMFRZ
rw 		TTM
rw 		TEOF
rw 		OVL
rw 		ABM
rw 		LPM
rw 		CANEN
rw
Toggle Fields

CANEN

Bit 0: CAN Controller Enable.

LPM

Bit 1: Disable/Enable Low Power Mode.

ABM

Bit 2: Disable/Enable Autobaud/Listen mode.

OVL

Bit 3: Disable/Enable Overload Frame.

TEOF

Bit 4: Timestamp messages at each end of Frame.

TTM

Bit 5: Disable/Enable Time Triggered Mode.

TIMFRZ

Bit 6: Enable Timer Freeze.

DRPT

Bit 7: Disable Repeat.

RXSYNC

Bits 24-26: Reception Synchronization Stage (not readable).

Allowed values:
0x0: DOUBLE_PP: Rx Signal with Double Synchro Stages (2 Positive Edges)
0x1: DOUBLE_PN: Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge)
0x2: SINGLE_P: Rx Signal with Single Synchro Stage (Positive Edge)
0x3: NONE: Rx Signal with No Synchro Stage

IER

Interrupt Enable Register

Offset: 0x4, reset: None, access: write-only

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BERR
w 		FERR
w 		AERR
w 		SERR
w 		CERR
w 		TSTP
w 		TOVF
w 		WAKEUP
w 		SLEEP
w 		BOFF
w 		ERRP
w 		WARN
w 		ERRA
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Mailbox 0 Interrupt Enable.

MB1

Bit 1: Mailbox 1 Interrupt Enable.

MB2

Bit 2: Mailbox 2 Interrupt Enable.

MB3

Bit 3: Mailbox 3 Interrupt Enable.

MB4

Bit 4: Mailbox 4 Interrupt Enable.

MB5

Bit 5: Mailbox 5 Interrupt Enable.

MB6

Bit 6: Mailbox 6 Interrupt Enable.

MB7

Bit 7: Mailbox 7 Interrupt Enable.

ERRA

Bit 16: Error Active Mode Interrupt Enable.

WARN

Bit 17: Warning Limit Interrupt Enable.

ERRP

Bit 18: Error Passive Mode Interrupt Enable.

BOFF

Bit 19: Bus Off Mode Interrupt Enable.

SLEEP

Bit 20: Sleep Interrupt Enable.

WAKEUP

Bit 21: Wakeup Interrupt Enable.

TOVF

Bit 22: Timer Overflow Interrupt Enable.

TSTP

Bit 23: TimeStamp Interrupt Enable.

CERR

Bit 24: CRC Error Interrupt Enable.

SERR

Bit 25: Stuffing Error Interrupt Enable.

AERR

Bit 26: Acknowledgment Error Interrupt Enable.

FERR

Bit 27: Form Error Interrupt Enable.

BERR

Bit 28: Bit Error Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x8, reset: None, access: write-only

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BERR
w 		FERR
w 		AERR
w 		SERR
w 		CERR
w 		TSTP
w 		TOVF
w 		WAKEUP
w 		SLEEP
w 		BOFF
w 		ERRP
w 		WARN
w 		ERRA
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Mailbox 0 Interrupt Disable.

MB1

Bit 1: Mailbox 1 Interrupt Disable.

MB2

Bit 2: Mailbox 2 Interrupt Disable.

MB3

Bit 3: Mailbox 3 Interrupt Disable.

MB4

Bit 4: Mailbox 4 Interrupt Disable.

MB5

Bit 5: Mailbox 5 Interrupt Disable.

MB6

Bit 6: Mailbox 6 Interrupt Disable.

MB7

Bit 7: Mailbox 7 Interrupt Disable.

ERRA

Bit 16: Error Active Mode Interrupt Disable.

WARN

Bit 17: Warning Limit Interrupt Disable.

ERRP

Bit 18: Error Passive Mode Interrupt Disable.

BOFF

Bit 19: Bus Off Mode Interrupt Disable.

SLEEP

Bit 20: Sleep Interrupt Disable.

WAKEUP

Bit 21: Wakeup Interrupt Disable.

TOVF

Bit 22: Timer Overflow Interrupt.

TSTP

Bit 23: TimeStamp Interrupt Disable.

CERR

Bit 24: CRC Error Interrupt Disable.

SERR

Bit 25: Stuffing Error Interrupt Disable.

AERR

Bit 26: Acknowledgment Error Interrupt Disable.

FERR

Bit 27: Form Error Interrupt Disable.

BERR

Bit 28: Bit Error Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0xc, reset: 0x00000000, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BERR
r 		FERR
r 		AERR
r 		SERR
r 		CERR
r 		TSTP
r 		TOVF
r 		WAKEUP
r 		SLEEP
r 		BOFF
r 		ERRP
r 		WARN
r 		ERRA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
r 		MB6
r 		MB5
r 		MB4
r 		MB3
r 		MB2
r 		MB1
r 		MB0
r
Toggle Fields

MB0

Bit 0: Mailbox 0 Interrupt Mask.

MB1

Bit 1: Mailbox 1 Interrupt Mask.

MB2

Bit 2: Mailbox 2 Interrupt Mask.

MB3

Bit 3: Mailbox 3 Interrupt Mask.

MB4

Bit 4: Mailbox 4 Interrupt Mask.

MB5

Bit 5: Mailbox 5 Interrupt Mask.

MB6

Bit 6: Mailbox 6 Interrupt Mask.

MB7

Bit 7: Mailbox 7 Interrupt Mask.

ERRA

Bit 16: Error Active Mode Interrupt Mask.

WARN

Bit 17: Warning Limit Interrupt Mask.

ERRP

Bit 18: Error Passive Mode Interrupt Mask.

BOFF

Bit 19: Bus Off Mode Interrupt Mask.

SLEEP

Bit 20: Sleep Interrupt Mask.

WAKEUP

Bit 21: Wakeup Interrupt Mask.

TOVF

Bit 22: Timer Overflow Interrupt Mask.

TSTP

Bit 23: Timestamp Interrupt Mask.

CERR

Bit 24: CRC Error Interrupt Mask.

SERR

Bit 25: Stuffing Error Interrupt Mask.

AERR

Bit 26: Acknowledgment Error Interrupt Mask.

FERR

Bit 27: Form Error Interrupt Mask.

BERR

Bit 28: Bit Error Interrupt Mask.

SR

Status Register

Offset: 0x10, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVLSY
r 		TBSY
r 		RBSY
r 		BERR
r 		FERR
r 		AERR
r 		SERR
r 		CERR
r 		TSTP
r 		TOVF
r 		WAKEUP
r 		SLEEP
r 		BOFF
r 		ERRP
r 		WARN
r 		ERRA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
r 		MB6
r 		MB5
r 		MB4
r 		MB3
r 		MB2
r 		MB1
r 		MB0
r
Toggle Fields

MB0

Bit 0: Mailbox 0 Event.

MB1

Bit 1: Mailbox 1 Event.

MB2

Bit 2: Mailbox 2 Event.

MB3

Bit 3: Mailbox 3 Event.

MB4

Bit 4: Mailbox 4 Event.

MB5

Bit 5: Mailbox 5 Event.

MB6

Bit 6: Mailbox 6 Event.

MB7

Bit 7: Mailbox 7 Event.

ERRA

Bit 16: Error Active Mode.

WARN

Bit 17: Warning Limit.

ERRP

Bit 18: Error Passive Mode.

BOFF

Bit 19: Bus Off Mode.

SLEEP

Bit 20: CAN controller in Low power Mode.

WAKEUP

Bit 21: CAN controller is not in Low power Mode.

TOVF

Bit 22: Timer Overflow.

TSTP

Bit 23: None.

CERR

Bit 24: Mailbox CRC Error.

SERR

Bit 25: Mailbox Stuffing Error.

AERR

Bit 26: Acknowledgment Error.

FERR

Bit 27: Form Error.

BERR

Bit 28: Bit Error.

RBSY

Bit 29: Receiver busy.

TBSY

Bit 30: Transmitter busy.

OVLSY

Bit 31: Overload busy.

BR

Baudrate Register

Offset: 0x14, reset: 0x00000000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP
rw 		BRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SJW
rw 		PROPAG
rw 		PHASE1
rw 		PHASE2
rw
Toggle Fields

PHASE2

Bits 0-2: Phase 2 segment.

PHASE1

Bits 4-6: Phase 1 segment.

PROPAG

Bits 8-10: Programming time segment.

SJW

Bits 12-13: Re-synchronization jump width.

BRP

Bits 16-22: Baudrate Prescaler..

SMP

Bit 24: Sampling Mode.

Allowed values:
0: ONCE: The incoming bit stream is sampled once at sample point.
1: THREE: The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.

TIM

Timer Register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER
r
Toggle Fields

TIMER

Bits 0-15: Timer.

TIMESTP

Timestamp Register

Offset: 0x1c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timestamp.

ECR

Error Counter Register

Offset: 0x20, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REC
r
Toggle Fields

REC

Bits 0-7: Receive Error Counter.

TEC

Bits 16-23: Transmit Error Counter.

TCR

Transfer Command Register

Offset: 0x24, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMRST
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Transfer Request for Mailbox 0.

MB1

Bit 1: Transfer Request for Mailbox 1.

MB2

Bit 2: Transfer Request for Mailbox 2.

MB3

Bit 3: Transfer Request for Mailbox 3.

MB4

Bit 4: Transfer Request for Mailbox 4.

MB5

Bit 5: Transfer Request for Mailbox 5.

MB6

Bit 6: Transfer Request for Mailbox 6.

MB7

Bit 7: Transfer Request for Mailbox 7.

TIMRST

Bit 31: Timer Reset.

ACR

Abort Command Register

Offset: 0x28, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MB7
w 		MB6
w 		MB5
w 		MB4
w 		MB3
w 		MB2
w 		MB1
w 		MB0
w
Toggle Fields

MB0

Bit 0: Abort Request for Mailbox 0.

MB1

Bit 1: Abort Request for Mailbox 1.

MB2

Bit 2: Abort Request for Mailbox 2.

MB3

Bit 3: Abort Request for Mailbox 3.

MB4

Bit 4: Abort Request for Mailbox 4.

MB5

Bit 5: Abort Request for Mailbox 5.

MB6

Bit 6: Abort Request for Mailbox 6.

MB7

Bit 7: Abort Request for Mailbox 7.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protection Enable.

WPKEY

Bits 8-31: SPI Write Protection Key Password.

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-15: Write Protection Violation Source.

MMR0

Mailbox Mode Register (MB = 0)

Offset: 0x200, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM0

Mailbox Acceptance Mask Register (MB = 0)

Offset: 0x204, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID0

Mailbox ID Register (MB = 0)

Offset: 0x208, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID0

Mailbox Family ID Register (MB = 0)

Offset: 0x20c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR0

Mailbox Status Register (MB = 0)

Offset: 0x210, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL0

Mailbox Data Low Register (MB = 0)

Offset: 0x214, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH0

Mailbox Data High Register (MB = 0)

Offset: 0x218, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR0

Mailbox Control Register (MB = 0)

Offset: 0x21c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR1

Mailbox Mode Register (MB = 1)

Offset: 0x220, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM1

Mailbox Acceptance Mask Register (MB = 1)

Offset: 0x224, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID1

Mailbox ID Register (MB = 1)

Offset: 0x228, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID1

Mailbox Family ID Register (MB = 1)

Offset: 0x22c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR1

Mailbox Status Register (MB = 1)

Offset: 0x230, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL1

Mailbox Data Low Register (MB = 1)

Offset: 0x234, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH1

Mailbox Data High Register (MB = 1)

Offset: 0x238, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR1

Mailbox Control Register (MB = 1)

Offset: 0x23c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR2

Mailbox Mode Register (MB = 2)

Offset: 0x240, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM2

Mailbox Acceptance Mask Register (MB = 2)

Offset: 0x244, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID2

Mailbox ID Register (MB = 2)

Offset: 0x248, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID2

Mailbox Family ID Register (MB = 2)

Offset: 0x24c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR2

Mailbox Status Register (MB = 2)

Offset: 0x250, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL2

Mailbox Data Low Register (MB = 2)

Offset: 0x254, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH2

Mailbox Data High Register (MB = 2)

Offset: 0x258, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR2

Mailbox Control Register (MB = 2)

Offset: 0x25c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR3

Mailbox Mode Register (MB = 3)

Offset: 0x260, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM3

Mailbox Acceptance Mask Register (MB = 3)

Offset: 0x264, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID3

Mailbox ID Register (MB = 3)

Offset: 0x268, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID3

Mailbox Family ID Register (MB = 3)

Offset: 0x26c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR3

Mailbox Status Register (MB = 3)

Offset: 0x270, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL3

Mailbox Data Low Register (MB = 3)

Offset: 0x274, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH3

Mailbox Data High Register (MB = 3)

Offset: 0x278, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR3

Mailbox Control Register (MB = 3)

Offset: 0x27c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR4

Mailbox Mode Register (MB = 4)

Offset: 0x280, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM4

Mailbox Acceptance Mask Register (MB = 4)

Offset: 0x284, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID4

Mailbox ID Register (MB = 4)

Offset: 0x288, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID4

Mailbox Family ID Register (MB = 4)

Offset: 0x28c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR4

Mailbox Status Register (MB = 4)

Offset: 0x290, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL4

Mailbox Data Low Register (MB = 4)

Offset: 0x294, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH4

Mailbox Data High Register (MB = 4)

Offset: 0x298, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR4

Mailbox Control Register (MB = 4)

Offset: 0x29c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR5

Mailbox Mode Register (MB = 5)

Offset: 0x2a0, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM5

Mailbox Acceptance Mask Register (MB = 5)

Offset: 0x2a4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID5

Mailbox ID Register (MB = 5)

Offset: 0x2a8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID5

Mailbox Family ID Register (MB = 5)

Offset: 0x2ac, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR5

Mailbox Status Register (MB = 5)

Offset: 0x2b0, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL5

Mailbox Data Low Register (MB = 5)

Offset: 0x2b4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH5

Mailbox Data High Register (MB = 5)

Offset: 0x2b8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR5

Mailbox Control Register (MB = 5)

Offset: 0x2bc, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR6

Mailbox Mode Register (MB = 6)

Offset: 0x2c0, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM6

Mailbox Acceptance Mask Register (MB = 6)

Offset: 0x2c4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID6

Mailbox ID Register (MB = 6)

Offset: 0x2c8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID6

Mailbox Family ID Register (MB = 6)

Offset: 0x2cc, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR6

Mailbox Status Register (MB = 6)

Offset: 0x2d0, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL6

Mailbox Data Low Register (MB = 6)

Offset: 0x2d4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH6

Mailbox Data High Register (MB = 6)

Offset: 0x2d8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR6

Mailbox Control Register (MB = 6)

Offset: 0x2dc, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

MMR7

Mailbox Mode Register (MB = 7)

Offset: 0x2e0, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MOT
rw 		PRIOR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMEMARK
rw
Toggle Fields

MTIMEMARK

Bits 0-15: Mailbox Timemark.

PRIOR

Bits 16-19: Mailbox Priority.

MOT

Bits 24-26: Mailbox Object Type.

Allowed values:
0x0: MB_DISABLED: Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
0x1: MB_RX: Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
0x2: MB_RX_OVERWRITE: Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
0x3: MB_TX: Transmit mailbox. Mailbox is configured for transmission.
0x4: MB_CONSUMER: Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
0x5: MB_PRODUCER: Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

MAM7

Mailbox Acceptance Mask Register (MB = 7)

Offset: 0x2e4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MID7

Mailbox ID Register (MB = 7)

Offset: 0x2e8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIDE
rw 		MIDvA
rw 		MIDvB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIDvB
rw
Toggle Fields

MIDvB

Bits 0-17: Complementary bits for identifier in extended frame mode.

MIDvA

Bits 18-28: Identifier for standard frame mode.

MIDE

Bit 29: Identifier Version.

MFID7

Mailbox Family ID Register (MB = 7)

Offset: 0x2ec, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFID
r
Toggle Fields

MFID

Bits 0-28: Family ID.

MSR7

Mailbox Status Register (MB = 7)

Offset: 0x2f0, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMI
r 		MRDY
r 		MABT
r 		MRTR
r 		MDLC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTIMESTAMP
r
Toggle Fields

MTIMESTAMP

Bits 0-15: Timer value.

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MABT

Bit 22: Mailbox Message Abort.

MRDY

Bit 23: Mailbox Ready.

MMI

Bit 24: Mailbox Message Ignored.

MDL7

Mailbox Data Low Register (MB = 7)

Offset: 0x2f4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDL
rw
Toggle Fields

MDL

Bits 0-31: Message Data Low Value.

MDH7

Mailbox Data High Register (MB = 7)

Offset: 0x2f8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDH
rw
Toggle Fields

MDH

Bits 0-31: Message Data High Value.

MCR7

Mailbox Control Register (MB = 7)

Offset: 0x2fc, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTCR
w 		MACR
w 		MRTR
w 		MDLC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MDLC

Bits 16-19: Mailbox Data Length Code.

MRTR

Bit 20: Mailbox Remote Transmission Request.

MACR

Bit 22: Abort Request for Mailbox x.

MTCR

Bit 23: Mailbox Transfer Command.

CHIPID

0x400e0940: Chip Identifier

9/9 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CIDR
0x4 EXID

CIDR

Chip ID Register

Offset: 0x0, reset: None, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXT
r 		NVPTYP
r 		ARCH
r 		SRAMSIZ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NVPSIZ2
r 		NVPSIZ
r 		EPROC
r 		VERSION
r
Toggle Fields

VERSION

Bits 0-4: Version of the Device.

EPROC

Bits 5-7: Embedded Processor.

Allowed values:
0x1: ARM946ES: ARM946ES
0x2: ARM7TDMI: ARM7TDMI
0x3: CM3: Cortex-M3
0x4: ARM920T: ARM920T
0x5: ARM926EJS: ARM926EJS
0x6: CA5: Cortex-A5
0x7: CM4: Cortex-M4

NVPSIZ

Bits 8-11: Nonvolatile Program Memory Size.

Allowed values:
0x0: NONE: None
0x1: 8K: 8 Kbytes
0x2: 16K: 16 Kbytes
0x3: 32K: 32 Kbytes
0x5: 64K: 64 Kbytes
0x7: 128K: 128 Kbytes
0x9: 256K: 256 Kbytes
0xA: 512K: 512 Kbytes
0xC: 1024K: 1024 Kbytes
0xE: 2048K: 2048 Kbytes

NVPSIZ2

Bits 12-15: Second Nonvolatile Program Memory Size.

Allowed values:
0x0: NONE: None
0x1: 8K: 8 Kbytes
0x2: 16K: 16 Kbytes
0x3: 32K: 32 Kbytes
0x5: 64K: 64 Kbytes
0x7: 128K: 128 Kbytes
0x9: 256K: 256 Kbytes
0xA: 512K: 512 Kbytes
0xC: 1024K: 1024 Kbytes
0xE: 2048K: 2048 Kbytes

SRAMSIZ

Bits 16-19: Internal SRAM Size.

Allowed values:
0x0: 48K: 48 Kbytes
0x1: 192K: 192 Kbytes
0x2: 2K: 2 Kbytes
0x3: 6K: 6 Kbytes
0x4: 24K: 24 Kbytes
0x5: 4K: 4 Kbytes
0x6: 80K: 80 Kbytes
0x7: 160K: 160 Kbytes
0x8: 8K: 8 Kbytes
0x9: 16K: 16 Kbytes
0xA: 32K: 32 Kbytes
0xB: 64K: 64 Kbytes
0xC: 128K: 128 Kbytes
0xD: 256K: 256 Kbytes
0xE: 96K: 96 Kbytes
0xF: 512K: 512 Kbytes

ARCH

Bits 20-27: Architecture Identifier.

Allowed values:
0x83: SAM3AxC: SAM3AxC (100-pin version)
0x84: SAM3XxC: SAM3XxC (100-pin version)
0x85: SAM3XxE: SAM3XxE (144-pin version)
0x86: SAM3XxG: SAM3XxG (208/217-pin version)

NVPTYP

Bits 28-30: Nonvolatile Program Memory Type.

Allowed values:
0x0: ROM: ROM
0x1: ROMLESS: ROMless or on-chip Flash
0x2: FLASH: Embedded Flash Memory
0x3: ROM_FLASH: ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size
0x4: SRAM: SRAM emulating ROM

EXT

Bit 31: Extension Flag.

EXID

Chip ID Extension Register

Offset: 0x4, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r
Toggle Fields

EXID

Bits 0-31: Chip ID Extension.

DACC

0x400c8000: Digital-to-Analog Converter Controller

20/51 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MR
0x10 CHER
0x14 CHDR
0x18 CHSR
0x20 CDR
0x24 IER
0x28 IDR
0x2c IMR
0x30 ISR
0x94 ACR
0xe4 WPMR
0xe8 WPSR
0x108 TPR
0x10c TCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
w
Toggle Fields

SWRST

Bit 0: Software Reset.

MR

Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STARTUP
rw 		MAXS
rw 		TAG
rw 		USER_SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH
rw 		FASTWKUP
rw 		SLEEP
rw 		WORD
rw 		TRGSEL
rw 		TRGEN
rw
Toggle Fields

TRGEN

Bit 0: Trigger Enable.

Allowed values:
0: DIS: External trigger mode disabled. DACC in free running mode.
1: EN: External trigger mode enabled.

TRGSEL

Bits 1-3: Trigger Selection.

WORD

Bit 4: Word Transfer.

Allowed values:
0: HALF: Half-Word transfer
1: WORD: Word Transfer

SLEEP

Bit 5: Sleep Mode.

FASTWKUP

Bit 6: Fast Wake up Mode.

REFRESH

Bits 8-15: Refresh Period.

USER_SEL

Bits 16-17: User Channel Selection.

Allowed values:
0: CHANNEL0: Channel 0
1: CHANNEL1: Channel 1

TAG

Bit 20: Tag Selection Mode.

Allowed values:
0: DIS: Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.
1: EN: Tag selection mode enabled

MAXS

Bit 21: Max Speed Mode.

Allowed values:
0: NORMAL: Normal Mode
1: MAXIMUM: Max Speed Mode enabled

STARTUP

Bits 24-29: Startup Time Selection.

Allowed values:
0x0: 0: 0 periods of DACClock
0x1: 8: 8 periods of DACClock
0x2: 16: 16 periods of DACClock
0x3: 24: 24 periods of DACClock
0x4: 64: 64 periods of DACClock
0x5: 80: 80 periods of DACClock
0x6: 96: 96 periods of DACClock
0x7: 112: 112 periods of DACClock
0x8: 512: 512 periods of DACClock
0x9: 576: 576 periods of DACClock
0xA: 640: 640 periods of DACClock
0xB: 704: 704 periods of DACClock
0xC: 768: 768 periods of DACClock
0xD: 832: 832 periods of DACClock
0xE: 896: 896 periods of DACClock
0xF: 960: 960 periods of DACClock
0x10: 1024: 1024 periods of DACClock
0x11: 1088: 1088 periods of DACClock
0x12: 1152: 1152 periods of DACClock
0x13: 1216: 1216 periods of DACClock
0x14: 1280: 1280 periods of DACClock
0x15: 1344: 1344 periods of DACClock
0x16: 1408: 1408 periods of DACClock
0x17: 1472: 1472 periods of DACClock
0x18: 1536: 1536 periods of DACClock
0x19: 1600: 1600 periods of DACClock
0x1A: 1664: 1664 periods of DACClock
0x1B: 1728: 1728 periods of DACClock
0x1C: 1792: 1792 periods of DACClock
0x1D: 1856: 1856 periods of DACClock
0x1E: 1920: 1920 periods of DACClock
0x1F: 1984: 1984 periods of DACClock

CHER

Channel Enable Register

Offset: 0x10, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1
w 		CH0
w
Toggle Fields

CH0

Bit 0: Channel 0 Enable.

CH1

Bit 1: Channel 1 Enable.

CHDR

Channel Disable Register

Offset: 0x14, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1
w 		CH0
w
Toggle Fields

CH0

Bit 0: Channel 0 Disable.

CH1

Bit 1: Channel 1 Disable.

CHSR

Channel Status Register

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1
r 		CH0
r
Toggle Fields

CH0

Bit 0: Channel 0 Status.

CH1

Bit 1: Channel 1 Status.

CDR

Conversion Data Register

Offset: 0x20, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
w
Toggle Fields

DATA

Bits 0-31: Data to Convert.

IER

Interrupt Enable Register

Offset: 0x24, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
w 		ENDTX
w 		EOC
w 		TXRDY
w
Toggle Fields

TXRDY

Bit 0: Transmit Ready Interrupt Enable.

EOC

Bit 1: End of Conversion Interrupt Enable.

ENDTX

Bit 2: End of Transmit Buffer Interrupt Enable.

TXBUFE

Bit 3: Transmit Buffer Empty Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x28, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
w 		ENDTX
w 		EOC
w 		TXRDY
w
Toggle Fields

TXRDY

Bit 0: Transmit Ready Interrupt Disable..

EOC

Bit 1: End of Conversion Interrupt Disable.

ENDTX

Bit 2: End of Transmit Buffer Interrupt Disable.

TXBUFE

Bit 3: Transmit Buffer Empty Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x2c, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
r 		ENDTX
r 		EOC
r 		TXRDY
r
Toggle Fields

TXRDY

Bit 0: Transmit Ready Interrupt Mask.

EOC

Bit 1: End of Conversion Interrupt Mask.

ENDTX

Bit 2: End of Transmit Buffer Interrupt Mask.

TXBUFE

Bit 3: Transmit Buffer Empty Interrupt Mask.

ISR

Interrupt Status Register

Offset: 0x30, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
r 		ENDTX
r 		EOC
r 		TXRDY
r
Toggle Fields

TXRDY

Bit 0: Transmit Ready Interrupt Flag.

EOC

Bit 1: End of Conversion Interrupt Flag.

ENDTX

Bit 2: End of DMA Interrupt Flag.

TXBUFE

Bit 3: Transmit Buffer Empty.

ACR

Analog Current Register

Offset: 0x94, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IBCTLDACCORE
rw 		IBCTLCH1
rw 		IBCTLCH0
rw
Toggle Fields

IBCTLCH0

Bits 0-1: Analog Output Current Control.

IBCTLCH1

Bits 2-3: Analog Output Current Control.

IBCTLDACCORE

Bits 8-9: Bias Current Control for DAC Core.

WPMR

Write Protect Mode register

Offset: 0xe4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

WPSR

Write Protect Status register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPROTADDR
r 		WPROTERR
r
Toggle Fields

WPROTERR

Bit 0: Write protection error.

WPROTADDR

Bits 8-15: Write protection error address.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

DMAC

0x400c4000: DMA Controller

160/318 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCFG
0x4 EN
0x8 SREQ
0xc CREQ
0x10 LAST
0x18 EBCIER
0x1c EBCIDR
0x20 EBCIMR
0x24 EBCISR
0x28 CHER
0x2c CHDR
0x30 CHSR
0x3c SADDR0
0x40 DADDR0
0x44 DSCR0
0x48 CTRLA0
0x4c CTRLB0
0x50 CFG0
0x64 SADDR1
0x68 DADDR1
0x6c DSCR1
0x70 CTRLA1
0x74 CTRLB1
0x78 CFG1
0x8c SADDR2
0x90 DADDR2
0x94 DSCR2
0x98 CTRLA2
0x9c CTRLB2
0xa0 CFG2
0xb4 SADDR3
0xb8 DADDR3
0xbc DSCR3
0xc0 CTRLA3
0xc4 CTRLB3
0xc8 CFG3
0xdc SADDR4
0xe0 DADDR4
0xe4 DSCR4
0xe8 CTRLA4
0xec CTRLB4
0xf0 CFG4
0x104 SADDR5
0x108 DADDR5
0x10c DSCR5
0x110 CTRLA5
0x114 CTRLB5
0x118 CFG5
0x1e4 WPMR
0x1e8 WPSR

GCFG

DMAC Global Configuration Register

Offset: 0x0, reset: 0x00000010, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARB_CFG
rw
Toggle Fields

ARB_CFG

Bit 4: Arbiter Configuration.

Allowed values:
0: FIXED: Fixed priority arbiter (see "Basic Definitions" )
1: ROUND_ROBIN: Modified round robin arbiter.

EN

DMAC Enable Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
rw
Toggle Fields

ENABLE

Bit 0: General Enable of DMA.

SREQ

DMAC Software Single Request Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSREQ5
rw 		SSREQ5
rw 		DSREQ4
rw 		SSREQ4
rw 		DSREQ3
rw 		SSREQ3
rw 		DSREQ2
rw 		SSREQ2
rw 		DSREQ1
rw 		SSREQ1
rw 		DSREQ0
rw 		SSREQ0
rw
Toggle Fields

SSREQ0

Bit 0: Source Request.

DSREQ0

Bit 1: Destination Request.

SSREQ1

Bit 2: Source Request.

DSREQ1

Bit 3: Destination Request.

SSREQ2

Bit 4: Source Request.

DSREQ2

Bit 5: Destination Request.

SSREQ3

Bit 6: Source Request.

DSREQ3

Bit 7: Destination Request.

SSREQ4

Bit 8: Source Request.

DSREQ4

Bit 9: Destination Request.

SSREQ5

Bit 10: Source Request.

DSREQ5

Bit 11: Destination Request.

CREQ

DMAC Software Chunk Transfer Request Register

Offset: 0xc, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCREQ5
rw 		SCREQ5
rw 		DCREQ4
rw 		SCREQ4
rw 		DCREQ3
rw 		SCREQ3
rw 		DCREQ2
rw 		SCREQ2
rw 		DCREQ1
rw 		SCREQ1
rw 		DCREQ0
rw 		SCREQ0
rw
Toggle Fields

SCREQ0

Bit 0: Source Chunk Request.

DCREQ0

Bit 1: Destination Chunk Request.

SCREQ1

Bit 2: Source Chunk Request.

DCREQ1

Bit 3: Destination Chunk Request.

SCREQ2

Bit 4: Source Chunk Request.

DCREQ2

Bit 5: Destination Chunk Request.

SCREQ3

Bit 6: Source Chunk Request.

DCREQ3

Bit 7: Destination Chunk Request.

SCREQ4

Bit 8: Source Chunk Request.

DCREQ4

Bit 9: Destination Chunk Request.

SCREQ5

Bit 10: Source Chunk Request.

DCREQ5

Bit 11: Destination Chunk Request.

LAST

DMAC Software Last Transfer Flag Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLAST5
rw 		SLAST5
rw 		DLAST4
rw 		SLAST4
rw 		DLAST3
rw 		SLAST3
rw 		DLAST2
rw 		SLAST2
rw 		DLAST1
rw 		SLAST1
rw 		DLAST0
rw 		SLAST0
rw
Toggle Fields

SLAST0

Bit 0: Source Last.

DLAST0

Bit 1: Destination Last.

SLAST1

Bit 2: Source Last.

DLAST1

Bit 3: Destination Last.

SLAST2

Bit 4: Source Last.

DLAST2

Bit 5: Destination Last.

SLAST3

Bit 6: Source Last.

DLAST3

Bit 7: Destination Last.

SLAST4

Bit 8: Source Last.

DLAST4

Bit 9: Destination Last.

SLAST5

Bit 10: Source Last.

DLAST5

Bit 11: Destination Last.

EBCIER

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.

Offset: 0x18, reset: None, access: write-only

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR5
w 		ERR4
w 		ERR3
w 		ERR2
w 		ERR1
w 		ERR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBTC5
w 		CBTC4
w 		CBTC3
w 		CBTC2
w 		CBTC1
w 		CBTC0
w 		BTC5
w 		BTC4
w 		BTC3
w 		BTC2
w 		BTC1
w 		BTC0
w
Toggle Fields

BTC0

Bit 0: Buffer Transfer Completed [5:0].

BTC1

Bit 1: Buffer Transfer Completed [5:0].

BTC2

Bit 2: Buffer Transfer Completed [5:0].

BTC3

Bit 3: Buffer Transfer Completed [5:0].

BTC4

Bit 4: Buffer Transfer Completed [5:0].

BTC5

Bit 5: Buffer Transfer Completed [5:0].

CBTC0

Bit 8: Chained Buffer Transfer Completed [5:0].

CBTC1

Bit 9: Chained Buffer Transfer Completed [5:0].

CBTC2

Bit 10: Chained Buffer Transfer Completed [5:0].

CBTC3

Bit 11: Chained Buffer Transfer Completed [5:0].

CBTC4

Bit 12: Chained Buffer Transfer Completed [5:0].

CBTC5

Bit 13: Chained Buffer Transfer Completed [5:0].

ERR0

Bit 16: Access Error [5:0].

ERR1

Bit 17: Access Error [5:0].

ERR2

Bit 18: Access Error [5:0].

ERR3

Bit 19: Access Error [5:0].

ERR4

Bit 20: Access Error [5:0].

ERR5

Bit 21: Access Error [5:0].

EBCIDR

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.

Offset: 0x1c, reset: None, access: write-only

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR5
w 		ERR4
w 		ERR3
w 		ERR2
w 		ERR1
w 		ERR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBTC5
w 		CBTC4
w 		CBTC3
w 		CBTC2
w 		CBTC1
w 		CBTC0
w 		BTC5
w 		BTC4
w 		BTC3
w 		BTC2
w 		BTC1
w 		BTC0
w
Toggle Fields

BTC0

Bit 0: Buffer Transfer Completed [5:0].

BTC1

Bit 1: Buffer Transfer Completed [5:0].

BTC2

Bit 2: Buffer Transfer Completed [5:0].

BTC3

Bit 3: Buffer Transfer Completed [5:0].

BTC4

Bit 4: Buffer Transfer Completed [5:0].

BTC5

Bit 5: Buffer Transfer Completed [5:0].

CBTC0

Bit 8: Chained Buffer Transfer Completed [5:0].

CBTC1

Bit 9: Chained Buffer Transfer Completed [5:0].

CBTC2

Bit 10: Chained Buffer Transfer Completed [5:0].

CBTC3

Bit 11: Chained Buffer Transfer Completed [5:0].

CBTC4

Bit 12: Chained Buffer Transfer Completed [5:0].

CBTC5

Bit 13: Chained Buffer Transfer Completed [5:0].

ERR0

Bit 16: Access Error [5:0].

ERR1

Bit 17: Access Error [5:0].

ERR2

Bit 18: Access Error [5:0].

ERR3

Bit 19: Access Error [5:0].

ERR4

Bit 20: Access Error [5:0].

ERR5

Bit 21: Access Error [5:0].

EBCIMR

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.

Offset: 0x20, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR5
r 		ERR4
r 		ERR3
r 		ERR2
r 		ERR1
r 		ERR0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBTC5
r 		CBTC4
r 		CBTC3
r 		CBTC2
r 		CBTC1
r 		CBTC0
r 		BTC5
r 		BTC4
r 		BTC3
r 		BTC2
r 		BTC1
r 		BTC0
r
Toggle Fields

BTC0

Bit 0: Buffer Transfer Completed [5:0].

BTC1

Bit 1: Buffer Transfer Completed [5:0].

BTC2

Bit 2: Buffer Transfer Completed [5:0].

BTC3

Bit 3: Buffer Transfer Completed [5:0].

BTC4

Bit 4: Buffer Transfer Completed [5:0].

BTC5

Bit 5: Buffer Transfer Completed [5:0].

CBTC0

Bit 8: Chained Buffer Transfer Completed [5:0].

CBTC1

Bit 9: Chained Buffer Transfer Completed [5:0].

CBTC2

Bit 10: Chained Buffer Transfer Completed [5:0].

CBTC3

Bit 11: Chained Buffer Transfer Completed [5:0].

CBTC4

Bit 12: Chained Buffer Transfer Completed [5:0].

CBTC5

Bit 13: Chained Buffer Transfer Completed [5:0].

ERR0

Bit 16: Access Error [5:0].

ERR1

Bit 17: Access Error [5:0].

ERR2

Bit 18: Access Error [5:0].

ERR3

Bit 19: Access Error [5:0].

ERR4

Bit 20: Access Error [5:0].

ERR5

Bit 21: Access Error [5:0].

EBCISR

DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.

Offset: 0x24, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR5
r 		ERR4
r 		ERR3
r 		ERR2
r 		ERR1
r 		ERR0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBTC5
r 		CBTC4
r 		CBTC3
r 		CBTC2
r 		CBTC1
r 		CBTC0
r 		BTC5
r 		BTC4
r 		BTC3
r 		BTC2
r 		BTC1
r 		BTC0
r
Toggle Fields

BTC0

Bit 0: Buffer Transfer Completed [5:0].

BTC1

Bit 1: Buffer Transfer Completed [5:0].

BTC2

Bit 2: Buffer Transfer Completed [5:0].

BTC3

Bit 3: Buffer Transfer Completed [5:0].

BTC4

Bit 4: Buffer Transfer Completed [5:0].

BTC5

Bit 5: Buffer Transfer Completed [5:0].

CBTC0

Bit 8: Chained Buffer Transfer Completed [5:0].

CBTC1

Bit 9: Chained Buffer Transfer Completed [5:0].

CBTC2

Bit 10: Chained Buffer Transfer Completed [5:0].

CBTC3

Bit 11: Chained Buffer Transfer Completed [5:0].

CBTC4

Bit 12: Chained Buffer Transfer Completed [5:0].

CBTC5

Bit 13: Chained Buffer Transfer Completed [5:0].

ERR0

Bit 16: Access Error [5:0].

ERR1

Bit 17: Access Error [5:0].

ERR2

Bit 18: Access Error [5:0].

ERR3

Bit 19: Access Error [5:0].

ERR4

Bit 20: Access Error [5:0].

ERR5

Bit 21: Access Error [5:0].

CHER

DMAC Channel Handler Enable Register

Offset: 0x28, reset: None, access: write-only

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEEP5
w 		KEEP4
w 		KEEP3
w 		KEEP2
w 		KEEP1
w 		KEEP0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP5
w 		SUSP4
w 		SUSP3
w 		SUSP2
w 		SUSP1
w 		SUSP0
w 		ENA5
w 		ENA4
w 		ENA3
w 		ENA2
w 		ENA1
w 		ENA0
w
Toggle Fields

ENA0

Bit 0: Enable [5:0].

ENA1

Bit 1: Enable [5:0].

ENA2

Bit 2: Enable [5:0].

ENA3

Bit 3: Enable [5:0].

ENA4

Bit 4: Enable [5:0].

ENA5

Bit 5: Enable [5:0].

SUSP0

Bit 8: Suspend [5:0].

SUSP1

Bit 9: Suspend [5:0].

SUSP2

Bit 10: Suspend [5:0].

SUSP3

Bit 11: Suspend [5:0].

SUSP4

Bit 12: Suspend [5:0].

SUSP5

Bit 13: Suspend [5:0].

KEEP0

Bit 24: Keep on [5:0].

KEEP1

Bit 25: Keep on [5:0].

KEEP2

Bit 26: Keep on [5:0].

KEEP3

Bit 27: Keep on [5:0].

KEEP4

Bit 28: Keep on [5:0].

KEEP5

Bit 29: Keep on [5:0].

CHDR

DMAC Channel Handler Disable Register

Offset: 0x2c, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES5
w 		RES4
w 		RES3
w 		RES2
w 		RES1
w 		RES0
w 		DIS5
w 		DIS4
w 		DIS3
w 		DIS2
w 		DIS1
w 		DIS0
w
Toggle Fields

DIS0

Bit 0: Disable [5:0].

DIS1

Bit 1: Disable [5:0].

DIS2

Bit 2: Disable [5:0].

DIS3

Bit 3: Disable [5:0].

DIS4

Bit 4: Disable [5:0].

DIS5

Bit 5: Disable [5:0].

RES0

Bit 8: Resume [5:0].

RES1

Bit 9: Resume [5:0].

RES2

Bit 10: Resume [5:0].

RES3

Bit 11: Resume [5:0].

RES4

Bit 12: Resume [5:0].

RES5

Bit 13: Resume [5:0].

CHSR

DMAC Channel Handler Status Register

Offset: 0x30, reset: 0x00FF0000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STAL5
r 		STAL4
r 		STAL3
r 		STAL2
r 		STAL1
r 		STAL0
r 		EMPT5
r 		EMPT4
r 		EMPT3
r 		EMPT2
r 		EMPT1
r 		EMPT0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP5
r 		SUSP4
r 		SUSP3
r 		SUSP2
r 		SUSP1
r 		SUSP0
r 		ENA5
r 		ENA4
r 		ENA3
r 		ENA2
r 		ENA1
r 		ENA0
r
Toggle Fields

ENA0

Bit 0: Enable [5:0].

ENA1

Bit 1: Enable [5:0].

ENA2

Bit 2: Enable [5:0].

ENA3

Bit 3: Enable [5:0].

ENA4

Bit 4: Enable [5:0].

ENA5

Bit 5: Enable [5:0].

SUSP0

Bit 8: Suspend [5:0].

SUSP1

Bit 9: Suspend [5:0].

SUSP2

Bit 10: Suspend [5:0].

SUSP3

Bit 11: Suspend [5:0].

SUSP4

Bit 12: Suspend [5:0].

SUSP5

Bit 13: Suspend [5:0].

EMPT0

Bit 16: Empty [5:0].

EMPT1

Bit 17: Empty [5:0].

EMPT2

Bit 18: Empty [5:0].

EMPT3

Bit 19: Empty [5:0].

EMPT4

Bit 20: Empty [5:0].

EMPT5

Bit 21: Empty [5:0].

STAL0

Bit 24: Stalled [5:0].

STAL1

Bit 25: Stalled [5:0].

STAL2

Bit 26: Stalled [5:0].

STAL3

Bit 27: Stalled [5:0].

STAL4

Bit 28: Stalled [5:0].

STAL5

Bit 29: Stalled [5:0].

SADDR0

DMAC Channel Source Address Register (ch_num = 0)

Offset: 0x3c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDR
rw
Toggle Fields

SADDR

Bits 0-31: Channel x Source Address.

DADDR0

DMAC Channel Destination Address Register (ch_num = 0)

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DADDR
rw
Toggle Fields

DADDR

Bits 0-31: Channel x Destination Address.

DSCR0

DMAC Channel Descriptor Address Register (ch_num = 0)

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSCR
rw
Toggle Fields

DSCR

Bits 2-31: Buffer Transfer Descriptor Address.

CTRLA0

DMAC Channel Control A Register (ch_num = 0)

Offset: 0x48, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE
rw 		DST_WIDTH
rw 		SRC_WIDTH
rw 		DCSIZE
rw 		SCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTSIZE
rw
Toggle Fields

BTSIZE

Bits 0-15: Buffer Transfer Size.

SCSIZE

Bits 16-18: Source Chunk Transfer Size..

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

DCSIZE

Bits 20-22: Destination Chunk Transfer Size.

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

SRC_WIDTH

Bits 24-25: Transfer Width for the Source.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DST_WIDTH

Bits 28-29: Transfer Width for the Destination.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DONE

Bit 31: Current Descriptor Stop Command and Transfer Completed Memory Indicator.

CTRLB0

DMAC Channel Control B Register (ch_num = 0)

Offset: 0x4c, reset: 0x00000000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN
rw 		DST_INCR
rw 		SRC_INCR
rw 		FC
rw 		DST_DSCR
rw 		SRC_DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SRC_DSCR

Bit 16: Source Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Source address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the source.

DST_DSCR

Bit 20: Destination Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Destination address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the destination.

FC

Bits 21-22: Flow Control.

Allowed values:
0x0: MEM2MEM_DMA_FC: Memory-to-Memory Transfer DMAC is flow controller
0x1: MEM2PER_DMA_FC: Memory-to-Peripheral Transfer DMAC is flow controller
0x2: PER2MEM_DMA_FC: Peripheral-to-Memory Transfer DMAC is flow controller
0x3: PER2PER_DMA_FC: Peripheral-to-Peripheral Transfer DMAC is flow controller

SRC_INCR

Bits 24-25: Incrementing, Decrementing or Fixed Address for the Source.

Allowed values:
0x0: INCREMENTING: The source address is incremented
0x1: DECREMENTING: The source address is decremented
0x2: FIXED: The source address remains unchanged

DST_INCR

Bits 28-29: Incrementing, Decrementing or Fixed Address for the Destination.

Allowed values:
0x0: INCREMENTING: The destination address is incremented
0x1: DECREMENTING: The destination address is decremented
0x2: FIXED: The destination address remains unchanged

IEN

Bit 30: Interrupt Enable Not.

CFG0

DMAC Channel Configuration Register (ch_num = 0)

Offset: 0x50, reset: 0x01000000, access: read-write

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCFG
rw 		AHB_PROT
rw 		LOCK_IF_L
rw 		LOCK_B
rw 		LOCK_IF
rw 		SOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DST_H2SEL
rw 		SRC_H2SEL
rw 		DST_PER
rw 		SRC_PER
rw
Toggle Fields

SRC_PER

Bits 0-3: Source with Peripheral identifier.

DST_PER

Bits 4-7: Destination with Peripheral identifier.

SRC_H2SEL

Bit 9: Software or Hardware Selection for the Source.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

DST_H2SEL

Bit 13: Software or Hardware Selection for the Destination.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

SOD

Bit 16: Stop On Done.

Allowed values:
0: DISABLE: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1: ENABLE: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.

LOCK_IF

Bit 20: Interface Lock.

Allowed values:
0: DISABLE: Interface Lock capability is disabled
1: ENABLE: Interface Lock capability is enabled

LOCK_B

Bit 21: Bus Lock.

Allowed values:
0: DISABLE: AHB Bus Locking capability is disabled.

LOCK_IF_L

Bit 22: Master Interface Arbiter Lock.

Allowed values:
0: CHUNK: The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1: BUFFER: The Master Interface Arbiter is locked by the channel x for a buffer transfer.

AHB_PROT

Bits 24-26: AHB Protection.

FIFOCFG

Bits 28-29: FIFO Configuration.

Allowed values:
0x0: ALAP_CFG: The largest defined length AHB burst is performed on the destination AHB interface.
0x1: HALF_CFG: When half FIFO size is available/filled, a source/destination request is serviced.
0x2: ASAP_CFG: When there is enough space/data available to perform a single AHB access, then the request is serviced.

SADDR1

DMAC Channel Source Address Register (ch_num = 1)

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDR
rw
Toggle Fields

SADDR

Bits 0-31: Channel x Source Address.

DADDR1

DMAC Channel Destination Address Register (ch_num = 1)

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DADDR
rw
Toggle Fields

DADDR

Bits 0-31: Channel x Destination Address.

DSCR1

DMAC Channel Descriptor Address Register (ch_num = 1)

Offset: 0x6c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSCR
rw
Toggle Fields

DSCR

Bits 2-31: Buffer Transfer Descriptor Address.

CTRLA1

DMAC Channel Control A Register (ch_num = 1)

Offset: 0x70, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE
rw 		DST_WIDTH
rw 		SRC_WIDTH
rw 		DCSIZE
rw 		SCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTSIZE
rw
Toggle Fields

BTSIZE

Bits 0-15: Buffer Transfer Size.

SCSIZE

Bits 16-18: Source Chunk Transfer Size..

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

DCSIZE

Bits 20-22: Destination Chunk Transfer Size.

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

SRC_WIDTH

Bits 24-25: Transfer Width for the Source.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DST_WIDTH

Bits 28-29: Transfer Width for the Destination.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DONE

Bit 31: Current Descriptor Stop Command and Transfer Completed Memory Indicator.

CTRLB1

DMAC Channel Control B Register (ch_num = 1)

Offset: 0x74, reset: 0x00000000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN
rw 		DST_INCR
rw 		SRC_INCR
rw 		FC
rw 		DST_DSCR
rw 		SRC_DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SRC_DSCR

Bit 16: Source Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Source address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the source.

DST_DSCR

Bit 20: Destination Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Destination address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the destination.

FC

Bits 21-22: Flow Control.

Allowed values:
0x0: MEM2MEM_DMA_FC: Memory-to-Memory Transfer DMAC is flow controller
0x1: MEM2PER_DMA_FC: Memory-to-Peripheral Transfer DMAC is flow controller
0x2: PER2MEM_DMA_FC: Peripheral-to-Memory Transfer DMAC is flow controller
0x3: PER2PER_DMA_FC: Peripheral-to-Peripheral Transfer DMAC is flow controller

SRC_INCR

Bits 24-25: Incrementing, Decrementing or Fixed Address for the Source.

Allowed values:
0x0: INCREMENTING: The source address is incremented
0x1: DECREMENTING: The source address is decremented
0x2: FIXED: The source address remains unchanged

DST_INCR

Bits 28-29: Incrementing, Decrementing or Fixed Address for the Destination.

Allowed values:
0x0: INCREMENTING: The destination address is incremented
0x1: DECREMENTING: The destination address is decremented
0x2: FIXED: The destination address remains unchanged

IEN

Bit 30: Interrupt Enable Not.

CFG1

DMAC Channel Configuration Register (ch_num = 1)

Offset: 0x78, reset: 0x01000000, access: read-write

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCFG
rw 		AHB_PROT
rw 		LOCK_IF_L
rw 		LOCK_B
rw 		LOCK_IF
rw 		SOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DST_H2SEL
rw 		SRC_H2SEL
rw 		DST_PER
rw 		SRC_PER
rw
Toggle Fields

SRC_PER

Bits 0-3: Source with Peripheral identifier.

DST_PER

Bits 4-7: Destination with Peripheral identifier.

SRC_H2SEL

Bit 9: Software or Hardware Selection for the Source.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

DST_H2SEL

Bit 13: Software or Hardware Selection for the Destination.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

SOD

Bit 16: Stop On Done.

Allowed values:
0: DISABLE: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1: ENABLE: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.

LOCK_IF

Bit 20: Interface Lock.

Allowed values:
0: DISABLE: Interface Lock capability is disabled
1: ENABLE: Interface Lock capability is enabled

LOCK_B

Bit 21: Bus Lock.

Allowed values:
0: DISABLE: AHB Bus Locking capability is disabled.

LOCK_IF_L

Bit 22: Master Interface Arbiter Lock.

Allowed values:
0: CHUNK: The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1: BUFFER: The Master Interface Arbiter is locked by the channel x for a buffer transfer.

AHB_PROT

Bits 24-26: AHB Protection.

FIFOCFG

Bits 28-29: FIFO Configuration.

Allowed values:
0x0: ALAP_CFG: The largest defined length AHB burst is performed on the destination AHB interface.
0x1: HALF_CFG: When half FIFO size is available/filled, a source/destination request is serviced.
0x2: ASAP_CFG: When there is enough space/data available to perform a single AHB access, then the request is serviced.

SADDR2

DMAC Channel Source Address Register (ch_num = 2)

Offset: 0x8c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDR
rw
Toggle Fields

SADDR

Bits 0-31: Channel x Source Address.

DADDR2

DMAC Channel Destination Address Register (ch_num = 2)

Offset: 0x90, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DADDR
rw
Toggle Fields

DADDR

Bits 0-31: Channel x Destination Address.

DSCR2

DMAC Channel Descriptor Address Register (ch_num = 2)

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSCR
rw
Toggle Fields

DSCR

Bits 2-31: Buffer Transfer Descriptor Address.

CTRLA2

DMAC Channel Control A Register (ch_num = 2)

Offset: 0x98, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE
rw 		DST_WIDTH
rw 		SRC_WIDTH
rw 		DCSIZE
rw 		SCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTSIZE
rw
Toggle Fields

BTSIZE

Bits 0-15: Buffer Transfer Size.

SCSIZE

Bits 16-18: Source Chunk Transfer Size..

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

DCSIZE

Bits 20-22: Destination Chunk Transfer Size.

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

SRC_WIDTH

Bits 24-25: Transfer Width for the Source.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DST_WIDTH

Bits 28-29: Transfer Width for the Destination.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DONE

Bit 31: Current Descriptor Stop Command and Transfer Completed Memory Indicator.

CTRLB2

DMAC Channel Control B Register (ch_num = 2)

Offset: 0x9c, reset: 0x00000000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN
rw 		DST_INCR
rw 		SRC_INCR
rw 		FC
rw 		DST_DSCR
rw 		SRC_DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SRC_DSCR

Bit 16: Source Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Source address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the source.

DST_DSCR

Bit 20: Destination Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Destination address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the destination.

FC

Bits 21-22: Flow Control.

Allowed values:
0x0: MEM2MEM_DMA_FC: Memory-to-Memory Transfer DMAC is flow controller
0x1: MEM2PER_DMA_FC: Memory-to-Peripheral Transfer DMAC is flow controller
0x2: PER2MEM_DMA_FC: Peripheral-to-Memory Transfer DMAC is flow controller
0x3: PER2PER_DMA_FC: Peripheral-to-Peripheral Transfer DMAC is flow controller

SRC_INCR

Bits 24-25: Incrementing, Decrementing or Fixed Address for the Source.

Allowed values:
0x0: INCREMENTING: The source address is incremented
0x1: DECREMENTING: The source address is decremented
0x2: FIXED: The source address remains unchanged

DST_INCR

Bits 28-29: Incrementing, Decrementing or Fixed Address for the Destination.

Allowed values:
0x0: INCREMENTING: The destination address is incremented
0x1: DECREMENTING: The destination address is decremented
0x2: FIXED: The destination address remains unchanged

IEN

Bit 30: Interrupt Enable Not.

CFG2

DMAC Channel Configuration Register (ch_num = 2)

Offset: 0xa0, reset: 0x01000000, access: read-write

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCFG
rw 		AHB_PROT
rw 		LOCK_IF_L
rw 		LOCK_B
rw 		LOCK_IF
rw 		SOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DST_H2SEL
rw 		SRC_H2SEL
rw 		DST_PER
rw 		SRC_PER
rw
Toggle Fields

SRC_PER

Bits 0-3: Source with Peripheral identifier.

DST_PER

Bits 4-7: Destination with Peripheral identifier.

SRC_H2SEL

Bit 9: Software or Hardware Selection for the Source.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

DST_H2SEL

Bit 13: Software or Hardware Selection for the Destination.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

SOD

Bit 16: Stop On Done.

Allowed values:
0: DISABLE: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1: ENABLE: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.

LOCK_IF

Bit 20: Interface Lock.

Allowed values:
0: DISABLE: Interface Lock capability is disabled
1: ENABLE: Interface Lock capability is enabled

LOCK_B

Bit 21: Bus Lock.

Allowed values:
0: DISABLE: AHB Bus Locking capability is disabled.

LOCK_IF_L

Bit 22: Master Interface Arbiter Lock.

Allowed values:
0: CHUNK: The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1: BUFFER: The Master Interface Arbiter is locked by the channel x for a buffer transfer.

AHB_PROT

Bits 24-26: AHB Protection.

FIFOCFG

Bits 28-29: FIFO Configuration.

Allowed values:
0x0: ALAP_CFG: The largest defined length AHB burst is performed on the destination AHB interface.
0x1: HALF_CFG: When half FIFO size is available/filled, a source/destination request is serviced.
0x2: ASAP_CFG: When there is enough space/data available to perform a single AHB access, then the request is serviced.

SADDR3

DMAC Channel Source Address Register (ch_num = 3)

Offset: 0xb4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDR
rw
Toggle Fields

SADDR

Bits 0-31: Channel x Source Address.

DADDR3

DMAC Channel Destination Address Register (ch_num = 3)

Offset: 0xb8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DADDR
rw
Toggle Fields

DADDR

Bits 0-31: Channel x Destination Address.

DSCR3

DMAC Channel Descriptor Address Register (ch_num = 3)

Offset: 0xbc, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSCR
rw
Toggle Fields

DSCR

Bits 2-31: Buffer Transfer Descriptor Address.

CTRLA3

DMAC Channel Control A Register (ch_num = 3)

Offset: 0xc0, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE
rw 		DST_WIDTH
rw 		SRC_WIDTH
rw 		DCSIZE
rw 		SCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTSIZE
rw
Toggle Fields

BTSIZE

Bits 0-15: Buffer Transfer Size.

SCSIZE

Bits 16-18: Source Chunk Transfer Size..

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

DCSIZE

Bits 20-22: Destination Chunk Transfer Size.

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

SRC_WIDTH

Bits 24-25: Transfer Width for the Source.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DST_WIDTH

Bits 28-29: Transfer Width for the Destination.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DONE

Bit 31: Current Descriptor Stop Command and Transfer Completed Memory Indicator.

CTRLB3

DMAC Channel Control B Register (ch_num = 3)

Offset: 0xc4, reset: 0x00000000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN
rw 		DST_INCR
rw 		SRC_INCR
rw 		FC
rw 		DST_DSCR
rw 		SRC_DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SRC_DSCR

Bit 16: Source Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Source address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the source.

DST_DSCR

Bit 20: Destination Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Destination address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the destination.

FC

Bits 21-22: Flow Control.

Allowed values:
0x0: MEM2MEM_DMA_FC: Memory-to-Memory Transfer DMAC is flow controller
0x1: MEM2PER_DMA_FC: Memory-to-Peripheral Transfer DMAC is flow controller
0x2: PER2MEM_DMA_FC: Peripheral-to-Memory Transfer DMAC is flow controller
0x3: PER2PER_DMA_FC: Peripheral-to-Peripheral Transfer DMAC is flow controller

SRC_INCR

Bits 24-25: Incrementing, Decrementing or Fixed Address for the Source.

Allowed values:
0x0: INCREMENTING: The source address is incremented
0x1: DECREMENTING: The source address is decremented
0x2: FIXED: The source address remains unchanged

DST_INCR

Bits 28-29: Incrementing, Decrementing or Fixed Address for the Destination.

Allowed values:
0x0: INCREMENTING: The destination address is incremented
0x1: DECREMENTING: The destination address is decremented
0x2: FIXED: The destination address remains unchanged

IEN

Bit 30: Interrupt Enable Not.

CFG3

DMAC Channel Configuration Register (ch_num = 3)

Offset: 0xc8, reset: 0x01000000, access: read-write

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCFG
rw 		AHB_PROT
rw 		LOCK_IF_L
rw 		LOCK_B
rw 		LOCK_IF
rw 		SOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DST_H2SEL
rw 		SRC_H2SEL
rw 		DST_PER
rw 		SRC_PER
rw
Toggle Fields

SRC_PER

Bits 0-3: Source with Peripheral identifier.

DST_PER

Bits 4-7: Destination with Peripheral identifier.

SRC_H2SEL

Bit 9: Software or Hardware Selection for the Source.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

DST_H2SEL

Bit 13: Software or Hardware Selection for the Destination.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

SOD

Bit 16: Stop On Done.

Allowed values:
0: DISABLE: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1: ENABLE: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.

LOCK_IF

Bit 20: Interface Lock.

Allowed values:
0: DISABLE: Interface Lock capability is disabled
1: ENABLE: Interface Lock capability is enabled

LOCK_B

Bit 21: Bus Lock.

Allowed values:
0: DISABLE: AHB Bus Locking capability is disabled.

LOCK_IF_L

Bit 22: Master Interface Arbiter Lock.

Allowed values:
0: CHUNK: The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1: BUFFER: The Master Interface Arbiter is locked by the channel x for a buffer transfer.

AHB_PROT

Bits 24-26: AHB Protection.

FIFOCFG

Bits 28-29: FIFO Configuration.

Allowed values:
0x0: ALAP_CFG: The largest defined length AHB burst is performed on the destination AHB interface.
0x1: HALF_CFG: When half FIFO size is available/filled, a source/destination request is serviced.
0x2: ASAP_CFG: When there is enough space/data available to perform a single AHB access, then the request is serviced.

SADDR4

DMAC Channel Source Address Register (ch_num = 4)

Offset: 0xdc, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDR
rw
Toggle Fields

SADDR

Bits 0-31: Channel x Source Address.

DADDR4

DMAC Channel Destination Address Register (ch_num = 4)

Offset: 0xe0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DADDR
rw
Toggle Fields

DADDR

Bits 0-31: Channel x Destination Address.

DSCR4

DMAC Channel Descriptor Address Register (ch_num = 4)

Offset: 0xe4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSCR
rw
Toggle Fields

DSCR

Bits 2-31: Buffer Transfer Descriptor Address.

CTRLA4

DMAC Channel Control A Register (ch_num = 4)

Offset: 0xe8, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE
rw 		DST_WIDTH
rw 		SRC_WIDTH
rw 		DCSIZE
rw 		SCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTSIZE
rw
Toggle Fields

BTSIZE

Bits 0-15: Buffer Transfer Size.

SCSIZE

Bits 16-18: Source Chunk Transfer Size..

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

DCSIZE

Bits 20-22: Destination Chunk Transfer Size.

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

SRC_WIDTH

Bits 24-25: Transfer Width for the Source.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DST_WIDTH

Bits 28-29: Transfer Width for the Destination.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DONE

Bit 31: Current Descriptor Stop Command and Transfer Completed Memory Indicator.

CTRLB4

DMAC Channel Control B Register (ch_num = 4)

Offset: 0xec, reset: 0x00000000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN
rw 		DST_INCR
rw 		SRC_INCR
rw 		FC
rw 		DST_DSCR
rw 		SRC_DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SRC_DSCR

Bit 16: Source Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Source address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the source.

DST_DSCR

Bit 20: Destination Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Destination address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the destination.

FC

Bits 21-22: Flow Control.

Allowed values:
0x0: MEM2MEM_DMA_FC: Memory-to-Memory Transfer DMAC is flow controller
0x1: MEM2PER_DMA_FC: Memory-to-Peripheral Transfer DMAC is flow controller
0x2: PER2MEM_DMA_FC: Peripheral-to-Memory Transfer DMAC is flow controller
0x3: PER2PER_DMA_FC: Peripheral-to-Peripheral Transfer DMAC is flow controller

SRC_INCR

Bits 24-25: Incrementing, Decrementing or Fixed Address for the Source.

Allowed values:
0x0: INCREMENTING: The source address is incremented
0x1: DECREMENTING: The source address is decremented
0x2: FIXED: The source address remains unchanged

DST_INCR

Bits 28-29: Incrementing, Decrementing or Fixed Address for the Destination.

Allowed values:
0x0: INCREMENTING: The destination address is incremented
0x1: DECREMENTING: The destination address is decremented
0x2: FIXED: The destination address remains unchanged

IEN

Bit 30: Interrupt Enable Not.

CFG4

DMAC Channel Configuration Register (ch_num = 4)

Offset: 0xf0, reset: 0x01000000, access: read-write

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCFG
rw 		AHB_PROT
rw 		LOCK_IF_L
rw 		LOCK_B
rw 		LOCK_IF
rw 		SOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DST_H2SEL
rw 		SRC_H2SEL
rw 		DST_PER
rw 		SRC_PER
rw
Toggle Fields

SRC_PER

Bits 0-3: Source with Peripheral identifier.

DST_PER

Bits 4-7: Destination with Peripheral identifier.

SRC_H2SEL

Bit 9: Software or Hardware Selection for the Source.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

DST_H2SEL

Bit 13: Software or Hardware Selection for the Destination.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

SOD

Bit 16: Stop On Done.

Allowed values:
0: DISABLE: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1: ENABLE: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.

LOCK_IF

Bit 20: Interface Lock.

Allowed values:
0: DISABLE: Interface Lock capability is disabled
1: ENABLE: Interface Lock capability is enabled

LOCK_B

Bit 21: Bus Lock.

Allowed values:
0: DISABLE: AHB Bus Locking capability is disabled.

LOCK_IF_L

Bit 22: Master Interface Arbiter Lock.

Allowed values:
0: CHUNK: The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1: BUFFER: The Master Interface Arbiter is locked by the channel x for a buffer transfer.

AHB_PROT

Bits 24-26: AHB Protection.

FIFOCFG

Bits 28-29: FIFO Configuration.

Allowed values:
0x0: ALAP_CFG: The largest defined length AHB burst is performed on the destination AHB interface.
0x1: HALF_CFG: When half FIFO size is available/filled, a source/destination request is serviced.
0x2: ASAP_CFG: When there is enough space/data available to perform a single AHB access, then the request is serviced.

SADDR5

DMAC Channel Source Address Register (ch_num = 5)

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDR
rw
Toggle Fields

SADDR

Bits 0-31: Channel x Source Address.

DADDR5

DMAC Channel Destination Address Register (ch_num = 5)

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DADDR
rw
Toggle Fields

DADDR

Bits 0-31: Channel x Destination Address.

DSCR5

DMAC Channel Descriptor Address Register (ch_num = 5)

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSCR
rw
Toggle Fields

DSCR

Bits 2-31: Buffer Transfer Descriptor Address.

CTRLA5

DMAC Channel Control A Register (ch_num = 5)

Offset: 0x110, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DONE
rw 		DST_WIDTH
rw 		SRC_WIDTH
rw 		DCSIZE
rw 		SCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTSIZE
rw
Toggle Fields

BTSIZE

Bits 0-15: Buffer Transfer Size.

SCSIZE

Bits 16-18: Source Chunk Transfer Size..

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

DCSIZE

Bits 20-22: Destination Chunk Transfer Size.

Allowed values:
0x0: CHK_1: 1 data transferred
0x1: CHK_4: 4 data transferred
0x2: CHK_8: 8 data transferred
0x3: CHK_16: 16 data transferred

SRC_WIDTH

Bits 24-25: Transfer Width for the Source.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DST_WIDTH

Bits 28-29: Transfer Width for the Destination.

Allowed values:
0x0: BYTE: the transfer size is set to 8-bit width
0x1: HALF_WORD: the transfer size is set to 16-bit width
0x2: WORD: the transfer size is set to 32-bit width

DONE

Bit 31: Current Descriptor Stop Command and Transfer Completed Memory Indicator.

CTRLB5

DMAC Channel Control B Register (ch_num = 5)

Offset: 0x114, reset: 0x00000000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN
rw 		DST_INCR
rw 		SRC_INCR
rw 		FC
rw 		DST_DSCR
rw 		SRC_DSCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SRC_DSCR

Bit 16: Source Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Source address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the source.

DST_DSCR

Bit 20: Destination Address Descriptor.

Allowed values:
0: FETCH_FROM_MEM: Destination address is updated when the descriptor is fetched from the memory.
1: FETCH_DISABLE: Buffer Descriptor Fetch operation is disabled for the destination.

FC

Bits 21-22: Flow Control.

Allowed values:
0x0: MEM2MEM_DMA_FC: Memory-to-Memory Transfer DMAC is flow controller
0x1: MEM2PER_DMA_FC: Memory-to-Peripheral Transfer DMAC is flow controller
0x2: PER2MEM_DMA_FC: Peripheral-to-Memory Transfer DMAC is flow controller
0x3: PER2PER_DMA_FC: Peripheral-to-Peripheral Transfer DMAC is flow controller

SRC_INCR

Bits 24-25: Incrementing, Decrementing or Fixed Address for the Source.

Allowed values:
0x0: INCREMENTING: The source address is incremented
0x1: DECREMENTING: The source address is decremented
0x2: FIXED: The source address remains unchanged

DST_INCR

Bits 28-29: Incrementing, Decrementing or Fixed Address for the Destination.

Allowed values:
0x0: INCREMENTING: The destination address is incremented
0x1: DECREMENTING: The destination address is decremented
0x2: FIXED: The destination address remains unchanged

IEN

Bit 30: Interrupt Enable Not.

CFG5

DMAC Channel Configuration Register (ch_num = 5)

Offset: 0x118, reset: 0x01000000, access: read-write

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCFG
rw 		AHB_PROT
rw 		LOCK_IF_L
rw 		LOCK_B
rw 		LOCK_IF
rw 		SOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DST_H2SEL
rw 		SRC_H2SEL
rw 		DST_PER
rw 		SRC_PER
rw
Toggle Fields

SRC_PER

Bits 0-3: Source with Peripheral identifier.

DST_PER

Bits 4-7: Destination with Peripheral identifier.

SRC_H2SEL

Bit 9: Software or Hardware Selection for the Source.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

DST_H2SEL

Bit 13: Software or Hardware Selection for the Destination.

Allowed values:
0: SW: Software handshaking interface is used to trigger a transfer request.
1: HW: Hardware handshaking interface is used to trigger a transfer request.

SOD

Bit 16: Stop On Done.

Allowed values:
0: DISABLE: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1: ENABLE: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.

LOCK_IF

Bit 20: Interface Lock.

Allowed values:
0: DISABLE: Interface Lock capability is disabled
1: ENABLE: Interface Lock capability is enabled

LOCK_B

Bit 21: Bus Lock.

Allowed values:
0: DISABLE: AHB Bus Locking capability is disabled.

LOCK_IF_L

Bit 22: Master Interface Arbiter Lock.

Allowed values:
0: CHUNK: The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1: BUFFER: The Master Interface Arbiter is locked by the channel x for a buffer transfer.

AHB_PROT

Bits 24-26: AHB Protection.

FIFOCFG

Bits 28-29: FIFO Configuration.

Allowed values:
0x0: ALAP_CFG: The largest defined length AHB burst is performed on the destination AHB interface.
0x1: HALF_CFG: When half FIFO size is available/filled, a source/destination request is serviced.
0x2: ASAP_CFG: When there is enough space/data available to perform a single AHB access, then the request is serviced.

WPMR

DMAC Write Protect Mode Register

Offset: 0x1e4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x444D41: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

WPSR

DMAC Write Protect Status Register

Offset: 0x1e8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

EFC0

0x400e0a00: Embedded Flash Controller 0

6/11 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FMR
0x4 FCR
0x8 FSR
0xc FRR

FMR

EEFC Flash Mode Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAM
rw 		SCOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FWS
rw 		FRDY
rw
Toggle Fields

FRDY

Bit 0: Ready Interrupt Enable.

FWS

Bits 8-11: Flash Wait State.

SCOD

Bit 16: Sequential Code Optimization Disable.

FAM

Bit 24: Flash Access Mode.

FCR

EEFC Flash Command Register

Offset: 0x4, reset: None, access: write-only

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FKEY
w 		FARG
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FARG
w 		FCMD
w
Toggle Fields

FCMD

Bits 0-7: Flash Command.

Allowed values:
0x00: GETD: Get Flash Descriptor
0x01: WP: Write page
0x02: WPL: Write page and lock
0x03: EWP: Erase page and write page
0x04: EWPL: Erase page and write page then lock
0x05: EA: Erase all
0x08: SLB: Set Lock Bit
0x09: CLB: Clear Lock Bit
0x0A: GLB: Get Lock Bit
0x0B: SGPB: Set GPNVM Bit
0x0C: CGPB: Clear GPNVM Bit
0x0D: GGPB: Get GPNVM Bit
0x0E: STUI: Start Read Unique Identifier
0x0F: SPUI: Stop Read Unique Identifier
0x10: GCALB: Get CALIB Bit

FARG

Bits 8-23: Flash Command Argument.

FKEY

Bits 24-31: Flash Writing Protection Key.

Allowed values:
0x5A: PASSWD: The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.

FSR

EEFC Flash Status Register

Offset: 0x8, reset: 0x00000001, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLOCKE
r 		FCMDE
r 		FRDY
r
Toggle Fields

FRDY

Bit 0: Flash Ready Status.

FCMDE

Bit 1: Flash Command Error Status.

FLOCKE

Bit 2: Flash Lock Error Status.

FRR

EEFC Flash Result Register

Offset: 0xc, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FVALUE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVALUE
r
Toggle Fields

FVALUE

Bits 0-31: Flash Result Value.

EFC1

0x400e0c00: Embedded Flash Controller 1

6/11 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FMR
0x4 FCR
0x8 FSR
0xc FRR

FMR

EEFC Flash Mode Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAM
rw 		SCOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FWS
rw 		FRDY
rw
Toggle Fields

FRDY

Bit 0: Ready Interrupt Enable.

FWS

Bits 8-11: Flash Wait State.

SCOD

Bit 16: Sequential Code Optimization Disable.

FAM

Bit 24: Flash Access Mode.

FCR

EEFC Flash Command Register

Offset: 0x4, reset: None, access: write-only

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FKEY
w 		FARG
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FARG
w 		FCMD
w
Toggle Fields

FCMD

Bits 0-7: Flash Command.

Allowed values:
0x00: GETD: Get Flash Descriptor
0x01: WP: Write page
0x02: WPL: Write page and lock
0x03: EWP: Erase page and write page
0x04: EWPL: Erase page and write page then lock
0x05: EA: Erase all
0x08: SLB: Set Lock Bit
0x09: CLB: Clear Lock Bit
0x0A: GLB: Get Lock Bit
0x0B: SGPB: Set GPNVM Bit
0x0C: CGPB: Clear GPNVM Bit
0x0D: GGPB: Get GPNVM Bit
0x0E: STUI: Start Read Unique Identifier
0x0F: SPUI: Stop Read Unique Identifier
0x10: GCALB: Get CALIB Bit

FARG

Bits 8-23: Flash Command Argument.

FKEY

Bits 24-31: Flash Writing Protection Key.

Allowed values:
0x5A: PASSWD: The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.

FSR

EEFC Flash Status Register

Offset: 0x8, reset: 0x00000001, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLOCKE
r 		FCMDE
r 		FRDY
r
Toggle Fields

FRDY

Bit 0: Flash Ready Status.

FCMDE

Bit 1: Flash Command Error Status.

FLOCKE

Bit 2: Flash Lock Error Status.

FRR

EEFC Flash Result Register

Offset: 0xc, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FVALUE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVALUE
r
Toggle Fields

FVALUE

Bits 0-31: Flash Result Value.

EMAC

0x400b0000: Ethernet MAC 10/100

16/129 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 NCR
0x4 NCFGR
0x8 NSR
0x14 TSR
0x18 RBQP
0x1c TBQP
0x20 RSR
0x24 ISR
0x28 IER
0x2c IDR
0x30 IMR
0x34 MAN
0x38 PTR
0x3c PFR
0x40 FTO
0x44 SCF
0x48 MCF
0x4c FRO
0x50 FCSE
0x54 ALE
0x58 DTF
0x5c LCOL
0x60 ECOL
0x64 TUND
0x68 CSE
0x6c RRE
0x70 ROV
0x74 RSE
0x78 ELE
0x7c RJA
0x80 USF
0x84 STE
0x88 RLE
0x90 HRB
0x94 HRT
0x98 SA1B
0x9c SA1T
0xa0 SA2B
0xa4 SA2T
0xa8 SA3B
0xac SA3T
0xb0 SA4B
0xb4 SA4T
0xb8 TID
0xc0 USRIO

NCR

Network Control Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THALT
rw 		TSTART
rw 		BP
rw 		WESTAT
rw 		INCSTAT
rw 		CLRSTAT
rw 		MPE
rw 		TE
rw 		RE
rw 		LLB
rw 		LB
rw
Toggle Fields

LB

Bit 0: LoopBack.

LLB

Bit 1: Loopback local.

RE

Bit 2: Receive enable.

TE

Bit 3: Transmit enable.

MPE

Bit 4: Management port enable.

CLRSTAT

Bit 5: Clear statistics registers.

INCSTAT

Bit 6: Increment statistics registers.

WESTAT

Bit 7: Write enable for statistics registers.

BP

Bit 8: Back pressure.

TSTART

Bit 9: Start transmission.

THALT

Bit 10: Transmit halt.

NCFGR

Network Configuration Register

Offset: 0x4, reset: 0x00000800, access: read-write

2/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRXFCS
rw 		EFRHD
rw 		DRFCS
rw 		RLCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBOF
rw 		PAE
rw 		RTY
rw 		CLK
rw 		BIG
rw 		UNI
rw 		MTI
rw 		NBC
rw 		CAF
rw 		JFRAME
rw 		FD
rw 		SPD
rw
Toggle Fields

SPD

Bit 0: Speed.

FD

Bit 1: Full Duplex.

JFRAME

Bit 3: Jumbo Frames.

CAF

Bit 4: Copy All Frames.

NBC

Bit 5: No Broadcast.

MTI

Bit 6: Multicast Hash Enable.

UNI

Bit 7: Unicast Hash Enable.

BIG

Bit 8: Receive 1536 bytes frames.

CLK

Bits 10-11: MDC clock divider.

Allowed values:
0x0: MCK_8: MCK divided by 8 (MCK up to 20 MHz).
0x1: MCK_16: MCK divided by 16 (MCK up to 40 MHz).
0x2: MCK_32: MCK divided by 32 (MCK up to 80 MHz).
0x3: MCK_64: MCK divided by 64 (MCK up to 160 MHz).

RTY

Bit 12: Retry test.

PAE

Bit 13: Pause Enable.

RBOF

Bits 14-15: Receive Buffer Offset.

Allowed values:
0x0: OFFSET_0: No offset from start of receive buffer.
0x1: OFFSET_1: One-byte offset from start of receive buffer.
0x2: OFFSET_2: Two-byte offset from start of receive buffer.
0x3: OFFSET_3: Three-byte offset from start of receive buffer.

RLCE

Bit 16: Receive Length field Checking Enable.

DRFCS

Bit 17: Discard Receive FCS.

EFRHD

Bit 18: None.

IRXFCS

Bit 19: Ignore RX FCS.

NSR

Network Status Register

Offset: 0x8, reset: None, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDLE
r 		MDIO
r
Toggle Fields

MDIO

Bit 1: None.

IDLE

Bit 2: None.

TSR

Transmit Status Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UND
rw 		COMP
rw 		BEX
rw 		TGO
rw 		RLES
rw 		COL
rw 		UBR
rw
Toggle Fields

UBR

Bit 0: Used Bit Read.

COL

Bit 1: Collision Occurred.

RLES

Bit 2: Retry Limit exceeded.

TGO

Bit 3: Transmit Go.

BEX

Bit 4: Buffers exhausted mid frame.

COMP

Bit 5: Transmit Complete.

UND

Bit 6: Transmit Underrun.

RBQP

Receive Buffer Queue Pointer Register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 2-31: Receive buffer queue pointer address.

TBQP

Transmit Buffer Queue Pointer Register

Offset: 0x1c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 2-31: Transmit buffer queue pointer address.

RSR

Receive Status Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR
rw 		REC
rw 		BNA
rw
Toggle Fields

BNA

Bit 0: Buffer Not Available.

REC

Bit 1: Frame Received.

OVR

Bit 2: Receive Overrun.

ISR

Interrupt Status Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTZ
rw 		PFRE
rw 		HRESP
rw 		ROVR
rw 		TCOMP
rw 		TXERR
rw 		RLEX
rw 		TUND
rw 		TXUBR
rw 		RXUBR
rw 		RCOMP
rw 		MFD
rw
Toggle Fields

MFD

Bit 0: Management Frame Done.

RCOMP

Bit 1: Receive Complete.

RXUBR

Bit 2: Receive Used Bit Read.

TXUBR

Bit 3: Transmit Used Bit Read.

TUND

Bit 4: Ethernet Transmit Buffer Underrun.

RLEX

Bit 5: Retry Limit Exceeded.

TXERR

Bit 6: Transmit Error.

TCOMP

Bit 7: Transmit Complete.

ROVR

Bit 10: Receive Overrun.

HRESP

Bit 11: Hresp not OK.

PFRE

Bit 12: Pause Frame Received.

PTZ

Bit 13: Pause Time Zero.

IER

Interrupt Enable Register

Offset: 0x28, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTZ
w 		PFR
w 		HRESP
w 		ROVR
w 		TCOMP
w 		TXERR
w 		RLE
w 		TUND
w 		TXUBR
w 		RXUBR
w 		RCOMP
w 		MFD
w
Toggle Fields

MFD

Bit 0: Management Frame sent.

RCOMP

Bit 1: Receive Complete.

RXUBR

Bit 2: Receive Used Bit Read.

TXUBR

Bit 3: Transmit Used Bit Read.

TUND

Bit 4: Ethernet Transmit Buffer Underrun.

RLE

Bit 5: Retry Limit Exceeded.

TXERR

Bit 6: None.

TCOMP

Bit 7: Transmit Complete.

ROVR

Bit 10: Receive Overrun.

HRESP

Bit 11: Hresp not OK.

PFR

Bit 12: Pause Frame Received.

PTZ

Bit 13: Pause Time Zero.

IDR

Interrupt Disable Register

Offset: 0x2c, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTZ
w 		PFR
w 		HRESP
w 		ROVR
w 		TCOMP
w 		TXERR
w 		RLE
w 		TUND
w 		TXUBR
w 		RXUBR
w 		RCOMP
w 		MFD
w
Toggle Fields

MFD

Bit 0: Management Frame sent.

RCOMP

Bit 1: Receive Complete.

RXUBR

Bit 2: Receive Used Bit Read.

TXUBR

Bit 3: Transmit Used Bit Read.

TUND

Bit 4: Ethernet Transmit Buffer Underrun.

RLE

Bit 5: Retry Limit Exceeded.

TXERR

Bit 6: None.

TCOMP

Bit 7: Transmit Complete.

ROVR

Bit 10: Receive Overrun.

HRESP

Bit 11: Hresp not OK.

PFR

Bit 12: Pause Frame Received.

PTZ

Bit 13: Pause Time Zero.

IMR

Interrupt Mask Register

Offset: 0x30, reset: 0x00003FFF, access: read-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTZ
r 		PFR
r 		HRESP
r 		ROVR
r 		TCOMP
r 		TXERR
r 		RLE
r 		TUND
r 		TXUBR
r 		RXUBR
r 		RCOMP
r 		MFD
r
Toggle Fields

MFD

Bit 0: Management Frame sent.

RCOMP

Bit 1: Receive Complete.

RXUBR

Bit 2: Receive Used Bit Read.

TXUBR

Bit 3: Transmit Used Bit Read.

TUND

Bit 4: Ethernet Transmit Buffer Underrun.

RLE

Bit 5: Retry Limit Exceeded.

TXERR

Bit 6: None.

TCOMP

Bit 7: Transmit Complete.

ROVR

Bit 10: Receive Overrun.

HRESP

Bit 11: Hresp not OK.

PFR

Bit 12: Pause Frame Received.

PTZ

Bit 13: Pause Time Zero.

MAN

Phy Maintenance Register

Offset: 0x34, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOF
rw 		RW
rw 		PHYA
rw 		REGA
rw 		CODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-15: None.

CODE

Bits 16-17: None.

REGA

Bits 18-22: Register Address.

PHYA

Bits 23-27: PHY Address.

RW

Bits 28-29: Read-write.

SOF

Bits 30-31: Start of frame.

PTR

Pause Time Register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTIME
rw
Toggle Fields

PTIME

Bits 0-15: Pause Time.

PFR

Pause Frames Received Register

Offset: 0x3c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FROK
rw
Toggle Fields

FROK

Bits 0-15: Pause Frames received OK.

FTO

Frames Transmitted Ok Register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTOK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTOK
rw
Toggle Fields

FTOK

Bits 0-23: Frames Transmitted OK.

SCF

Single Collision Frames Register

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCF
rw
Toggle Fields

SCF

Bits 0-15: Single Collision Frames.

MCF

Multiple Collision Frames Register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCF
rw
Toggle Fields

MCF

Bits 0-15: Multicollision Frames.

FRO

Frames Received Ok Register

Offset: 0x4c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FROK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FROK
rw
Toggle Fields

FROK

Bits 0-23: Frames Received OK.

FCSE

Frame Check Sequence Errors Register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCSE
rw
Toggle Fields

FCSE

Bits 0-7: Frame Check Sequence Errors.

ALE

Alignment Errors Register

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALE
rw
Toggle Fields

ALE

Bits 0-7: Alignment Errors.

DTF

Deferred Transmission Frames Register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTF
rw
Toggle Fields

DTF

Bits 0-15: Deferred Transmission Frames.

LCOL

Late Collisions Register

Offset: 0x5c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCOL
rw
Toggle Fields

LCOL

Bits 0-7: Late Collisions.

ECOL

Excessive Collisions Register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCOL
rw
Toggle Fields

EXCOL

Bits 0-7: Excessive Collisions.

TUND

Transmit Underrun Errors Register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TUND
rw
Toggle Fields

TUND

Bits 0-7: Transmit Underruns.

CSE

Carrier Sense Errors Register

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSE
rw
Toggle Fields

CSE

Bits 0-7: Carrier Sense Errors.

RRE

Receive Resource Errors Register

Offset: 0x6c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRE
rw
Toggle Fields

RRE

Bits 0-15: Receive Resource Errors.

ROV

Receive Overrun Errors Register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVR
rw
Toggle Fields

ROVR

Bits 0-7: Receive Overrun.

RSE

Receive Symbol Errors Register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSE
rw
Toggle Fields

RSE

Bits 0-7: Receive Symbol Errors.

ELE

Excessive Length Errors Register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXL
rw
Toggle Fields

EXL

Bits 0-7: Excessive Length Errors.

RJA

Receive Jabbers Register

Offset: 0x7c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RJB
rw
Toggle Fields

RJB

Bits 0-7: Receive Jabbers.

USF

Undersize Frames Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USF
rw
Toggle Fields

USF

Bits 0-7: Undersize frames.

STE

SQE Test Errors Register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQER
rw
Toggle Fields

SQER

Bits 0-7: SQE test errors.

RLE

Received Length Field Mismatch Register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLFM
rw
Toggle Fields

RLFM

Bits 0-7: Receive Length Field Mismatch.

HRB

Hash Register Bottom [31:0] Register

Offset: 0x90, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-31: None.

HRT

Hash Register Top [63:32] Register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-31: None.

SA1B

Specific Address 1 Bottom Register

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-31: None.

SA1T

Specific Address 1 Top Register

Offset: 0x9c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-15: None.

SA2B

Specific Address 2 Bottom Register

Offset: 0xa0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-31: None.

SA2T

Specific Address 2 Top Register

Offset: 0xa4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-15: None.

SA3B

Specific Address 3 Bottom Register

Offset: 0xa8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-31: None.

SA3T

Specific Address 3 Top Register

Offset: 0xac, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-15: None.

SA4B

Specific Address 4 Bottom Register

Offset: 0xb0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-31: None.

SA4T

Specific Address 4 Top Register

Offset: 0xb4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields

ADDR

Bits 0-15: None.

TID

Type ID Checking Register

Offset: 0xb8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TID
rw
Toggle Fields

TID

Bits 0-15: Type ID checking.

USRIO

User Input/Output Register

Offset: 0xc0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKEN
rw 		RMII
rw
Toggle Fields

RMII

Bit 0: Reduce MII.

CLKEN

Bit 1: Clock Enable.

GPBR

0x400e1a90: General Purpose Backup Registers

0/8 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GPBR[[0]]
0x4 GPBR[[1]]
0x8 GPBR[[2]]
0xc GPBR[[3]]
0x10 GPBR[[4]]
0x14 GPBR[[5]]
0x18 GPBR[[6]]
0x1c GPBR[[7]]

GPBR[[0]]

General Purpose Backup Register

Offset: 0x0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

GPBR[[1]]

General Purpose Backup Register

Offset: 0x4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

GPBR[[2]]

General Purpose Backup Register

Offset: 0x8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

GPBR[[3]]

General Purpose Backup Register

Offset: 0xc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

GPBR[[4]]

General Purpose Backup Register

Offset: 0x10, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

GPBR[[5]]

General Purpose Backup Register

Offset: 0x14, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

GPBR[[6]]

General Purpose Backup Register

Offset: 0x18, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

GPBR[[7]]

General Purpose Backup Register

Offset: 0x1c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPBR_VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPBR_VALUE
rw
Toggle Fields

GPBR_VALUE

Bits 0-31: Value of GPBR x.

HSMCI

0x40000000: High Speed MultiMedia Card Interface

74/409 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MR
0x8 DTOR
0xc SDCR
0x10 ARGR
0x14 CMDR
0x18 BLKR
0x1c CSTOR
0x20 RSPR[[0]]
0x24 RSPR[[1]]
0x28 RSPR[[2]]
0x2c RSPR[[3]]
0x30 RDR
0x34 TDR
0x40 SR
0x44 IER
0x48 IDR
0x4c IMR
0x50 DMA
0x54 CFG
0xe4 WPMR
0xe8 WPSR
0x200 FIFO[[0]]
0x204 FIFO[[1]]
0x208 FIFO[[2]]
0x20c FIFO[[3]]
0x210 FIFO[[4]]
0x214 FIFO[[5]]
0x218 FIFO[[6]]
0x21c FIFO[[7]]
0x220 FIFO[[8]]
0x224 FIFO[[9]]
0x228 FIFO[[10]]
0x22c FIFO[[11]]
0x230 FIFO[[12]]
0x234 FIFO[[13]]
0x238 FIFO[[14]]
0x23c FIFO[[15]]
0x240 FIFO[[16]]
0x244 FIFO[[17]]
0x248 FIFO[[18]]
0x24c FIFO[[19]]
0x250 FIFO[[20]]
0x254 FIFO[[21]]
0x258 FIFO[[22]]
0x25c FIFO[[23]]
0x260 FIFO[[24]]
0x264 FIFO[[25]]
0x268 FIFO[[26]]
0x26c FIFO[[27]]
0x270 FIFO[[28]]
0x274 FIFO[[29]]
0x278 FIFO[[30]]
0x27c FIFO[[31]]
0x280 FIFO[[32]]
0x284 FIFO[[33]]
0x288 FIFO[[34]]
0x28c FIFO[[35]]
0x290 FIFO[[36]]
0x294 FIFO[[37]]
0x298 FIFO[[38]]
0x29c FIFO[[39]]
0x2a0 FIFO[[40]]
0x2a4 FIFO[[41]]
0x2a8 FIFO[[42]]
0x2ac FIFO[[43]]
0x2b0 FIFO[[44]]
0x2b4 FIFO[[45]]
0x2b8 FIFO[[46]]
0x2bc FIFO[[47]]
0x2c0 FIFO[[48]]
0x2c4 FIFO[[49]]
0x2c8 FIFO[[50]]
0x2cc FIFO[[51]]
0x2d0 FIFO[[52]]
0x2d4 FIFO[[53]]
0x2d8 FIFO[[54]]
0x2dc FIFO[[55]]
0x2e0 FIFO[[56]]
0x2e4 FIFO[[57]]
0x2e8 FIFO[[58]]
0x2ec FIFO[[59]]
0x2f0 FIFO[[60]]
0x2f4 FIFO[[61]]
0x2f8 FIFO[[62]]
0x2fc FIFO[[63]]
0x300 FIFO[[64]]
0x304 FIFO[[65]]
0x308 FIFO[[66]]
0x30c FIFO[[67]]
0x310 FIFO[[68]]
0x314 FIFO[[69]]
0x318 FIFO[[70]]
0x31c FIFO[[71]]
0x320 FIFO[[72]]
0x324 FIFO[[73]]
0x328 FIFO[[74]]
0x32c FIFO[[75]]
0x330 FIFO[[76]]
0x334 FIFO[[77]]
0x338 FIFO[[78]]
0x33c FIFO[[79]]
0x340 FIFO[[80]]
0x344 FIFO[[81]]
0x348 FIFO[[82]]
0x34c FIFO[[83]]
0x350 FIFO[[84]]
0x354 FIFO[[85]]
0x358 FIFO[[86]]
0x35c FIFO[[87]]
0x360 FIFO[[88]]
0x364 FIFO[[89]]
0x368 FIFO[[90]]
0x36c FIFO[[91]]
0x370 FIFO[[92]]
0x374 FIFO[[93]]
0x378 FIFO[[94]]
0x37c FIFO[[95]]
0x380 FIFO[[96]]
0x384 FIFO[[97]]
0x388 FIFO[[98]]
0x38c FIFO[[99]]
0x390 FIFO[[100]]
0x394 FIFO[[101]]
0x398 FIFO[[102]]
0x39c FIFO[[103]]
0x3a0 FIFO[[104]]
0x3a4 FIFO[[105]]
0x3a8 FIFO[[106]]
0x3ac FIFO[[107]]
0x3b0 FIFO[[108]]
0x3b4 FIFO[[109]]
0x3b8 FIFO[[110]]
0x3bc FIFO[[111]]
0x3c0 FIFO[[112]]
0x3c4 FIFO[[113]]
0x3c8 FIFO[[114]]
0x3cc FIFO[[115]]
0x3d0 FIFO[[116]]
0x3d4 FIFO[[117]]
0x3d8 FIFO[[118]]
0x3dc FIFO[[119]]
0x3e0 FIFO[[120]]
0x3e4 FIFO[[121]]
0x3e8 FIFO[[122]]
0x3ec FIFO[[123]]
0x3f0 FIFO[[124]]
0x3f4 FIFO[[125]]
0x3f8 FIFO[[126]]
0x3fc FIFO[[127]]
0x400 FIFO[[128]]
0x404 FIFO[[129]]
0x408 FIFO[[130]]
0x40c FIFO[[131]]
0x410 FIFO[[132]]
0x414 FIFO[[133]]
0x418 FIFO[[134]]
0x41c FIFO[[135]]
0x420 FIFO[[136]]
0x424 FIFO[[137]]
0x428 FIFO[[138]]
0x42c FIFO[[139]]
0x430 FIFO[[140]]
0x434 FIFO[[141]]
0x438 FIFO[[142]]
0x43c FIFO[[143]]
0x440 FIFO[[144]]
0x444 FIFO[[145]]
0x448 FIFO[[146]]
0x44c FIFO[[147]]
0x450 FIFO[[148]]
0x454 FIFO[[149]]
0x458 FIFO[[150]]
0x45c FIFO[[151]]
0x460 FIFO[[152]]
0x464 FIFO[[153]]
0x468 FIFO[[154]]
0x46c FIFO[[155]]
0x470 FIFO[[156]]
0x474 FIFO[[157]]
0x478 FIFO[[158]]
0x47c FIFO[[159]]
0x480 FIFO[[160]]
0x484 FIFO[[161]]
0x488 FIFO[[162]]
0x48c FIFO[[163]]
0x490 FIFO[[164]]
0x494 FIFO[[165]]
0x498 FIFO[[166]]
0x49c FIFO[[167]]
0x4a0 FIFO[[168]]
0x4a4 FIFO[[169]]
0x4a8 FIFO[[170]]
0x4ac FIFO[[171]]
0x4b0 FIFO[[172]]
0x4b4 FIFO[[173]]
0x4b8 FIFO[[174]]
0x4bc FIFO[[175]]
0x4c0 FIFO[[176]]
0x4c4 FIFO[[177]]
0x4c8 FIFO[[178]]
0x4cc FIFO[[179]]
0x4d0 FIFO[[180]]
0x4d4 FIFO[[181]]
0x4d8 FIFO[[182]]
0x4dc FIFO[[183]]
0x4e0 FIFO[[184]]
0x4e4 FIFO[[185]]
0x4e8 FIFO[[186]]
0x4ec FIFO[[187]]
0x4f0 FIFO[[188]]
0x4f4 FIFO[[189]]
0x4f8 FIFO[[190]]
0x4fc FIFO[[191]]
0x500 FIFO[[192]]
0x504 FIFO[[193]]
0x508 FIFO[[194]]
0x50c FIFO[[195]]
0x510 FIFO[[196]]
0x514 FIFO[[197]]
0x518 FIFO[[198]]
0x51c FIFO[[199]]
0x520 FIFO[[200]]
0x524 FIFO[[201]]
0x528 FIFO[[202]]
0x52c FIFO[[203]]
0x530 FIFO[[204]]
0x534 FIFO[[205]]
0x538 FIFO[[206]]
0x53c FIFO[[207]]
0x540 FIFO[[208]]
0x544 FIFO[[209]]
0x548 FIFO[[210]]
0x54c FIFO[[211]]
0x550 FIFO[[212]]
0x554 FIFO[[213]]
0x558 FIFO[[214]]
0x55c FIFO[[215]]
0x560 FIFO[[216]]
0x564 FIFO[[217]]
0x568 FIFO[[218]]
0x56c FIFO[[219]]
0x570 FIFO[[220]]
0x574 FIFO[[221]]
0x578 FIFO[[222]]
0x57c FIFO[[223]]
0x580 FIFO[[224]]
0x584 FIFO[[225]]
0x588 FIFO[[226]]
0x58c FIFO[[227]]
0x590 FIFO[[228]]
0x594 FIFO[[229]]
0x598 FIFO[[230]]
0x59c FIFO[[231]]
0x5a0 FIFO[[232]]
0x5a4 FIFO[[233]]
0x5a8 FIFO[[234]]
0x5ac FIFO[[235]]
0x5b0 FIFO[[236]]
0x5b4 FIFO[[237]]
0x5b8 FIFO[[238]]
0x5bc FIFO[[239]]
0x5c0 FIFO[[240]]
0x5c4 FIFO[[241]]
0x5c8 FIFO[[242]]
0x5cc FIFO[[243]]
0x5d0 FIFO[[244]]
0x5d4 FIFO[[245]]
0x5d8 FIFO[[246]]
0x5dc FIFO[[247]]
0x5e0 FIFO[[248]]
0x5e4 FIFO[[249]]
0x5e8 FIFO[[250]]
0x5ec FIFO[[251]]
0x5f0 FIFO[[252]]
0x5f4 FIFO[[253]]
0x5f8 FIFO[[254]]
0x5fc FIFO[[255]]

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
w 		PWSDIS
w 		PWSEN
w 		MCIDIS
w 		MCIEN
w
Toggle Fields

MCIEN

Bit 0: Multi-Media Interface Enable.

MCIDIS

Bit 1: Multi-Media Interface Disable.

PWSEN

Bit 2: Power Save Mode Enable.

PWSDIS

Bit 3: Power Save Mode Disable.

SWRST

Bit 7: Software Reset.

MR

Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADV
rw 		FBYTE
rw 		WRPROOF
rw 		RDPROOF
rw 		PWSDIV
rw 		CLKDIV
rw
Toggle Fields

CLKDIV

Bits 0-7: Clock Divider.

PWSDIV

Bits 8-10: Power Saving Divider.

RDPROOF

Bit 11: Read Proof Enable.

WRPROOF

Bit 12: Write Proof Enable.

FBYTE

Bit 13: Force Byte Transfer.

PADV

Bit 14: Padding Value.

DTOR

Data Timeout Register

Offset: 0x8, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTOMUL
rw 		DTOCYC
rw
Toggle Fields

DTOCYC

Bits 0-3: Data Timeout Cycle Number.

DTOMUL

Bits 4-6: Data Timeout Multiplier.

Allowed values:
0x0: 1: DTOCYC
0x1: 16: DTOCYC x 16
0x2: 128: DTOCYC x 128
0x3: 256: DTOCYC x 256
0x4: 1024: DTOCYC x 1024
0x5: 4096: DTOCYC x 4096
0x6: 65536: DTOCYC x 65536
0x7: 1048576: DTOCYC x 1048576

SDCR

SD/SDIO Card Register

Offset: 0xc, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDCBUS
rw 		SDCSEL
rw
Toggle Fields

SDCSEL

Bits 0-1: SDCard/SDIO Slot.

Allowed values:
0x0: SLOTA: Slot A is selected.
0x1: SLOTB: SDCARD/SDIO Slot B selected
0x2: SLOTC: -
0x3: SLOTD: -

SDCBUS

Bits 6-7: SDCard/SDIO Bus Width.

Allowed values:
0x0: 1: 1 bit
0x2: 4: 4 bits
0x3: 8: 8 bits

ARGR

Argument Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARG
rw
Toggle Fields

ARG

Bits 0-31: Command Argument.

CMDR

Command Register

Offset: 0x14, reset: None, access: write-only

9/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOOT_ACK
w 		ATACS
w 		IOSPCMD
w 		TRTYP
w 		TRDIR
w 		TRCMD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXLAT
w 		OPDCMD
w 		SPCMD
w 		RSPTYP
w 		CMDNB
w
Toggle Fields

CMDNB

Bits 0-5: Command Number.

RSPTYP

Bits 6-7: Response Type.

Allowed values:
0x0: NORESP: No response
0x1: 48_BIT: 48-bit response
0x2: 136_BIT: 136-bit response
0x3: R1B: R1b response type

SPCMD

Bits 8-10: Special Command.

Allowed values:
0x0: STD: Not a special CMD.
0x1: INIT: Initialization CMD: 74 clock cycles for initialization sequence.
0x2: SYNC: Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.
0x3: CE_ATA: CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.
0x4: IT_CMD: Interrupt command: Corresponds to the Interrupt Mode (CMD40).
0x5: IT_RESP: Interrupt response: Corresponds to the Interrupt Mode (CMD40).
0x6: BOR: Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.
0x7: EBO: End Boot Operation. This command allows the host processor to terminate the boot operation mode.

OPDCMD

Bit 11: Open Drain Command.

Allowed values:
0: PUSHPULL: Push pull command.
1: OPENDRAIN: Open drain command.

MAXLAT

Bit 12: Max Latency for Command to Response.

Allowed values:
0: 5: 5-cycle max latency.
1: 64: 64-cycle max latency.

TRCMD

Bits 16-17: Transfer Command.

Allowed values:
0x0: NO_DATA: No data transfer
0x1: START_DATA: Start data transfer
0x2: STOP_DATA: Stop data transfer

TRDIR

Bit 18: Transfer Direction.

Allowed values:
0: WRITE: Write.
1: READ: Read.

TRTYP

Bits 19-21: Transfer Type.

Allowed values:
0x0: SINGLE: MMC/SD Card Single Block
0x1: MULTIPLE: MMC/SD Card Multiple Block
0x2: STREAM: MMC Stream
0x4: BYTE: SDIO Byte
0x5: BLOCK: SDIO Block

IOSPCMD

Bits 24-25: SDIO Special Command.

Allowed values:
0x0: STD: Not an SDIO Special Command
0x1: SUSPEND: SDIO Suspend Command
0x2: RESUME: SDIO Resume Command

ATACS

Bit 26: ATA with Command Completion Signal.

Allowed values:
0: NORMAL: Normal operation mode.
1: COMPLETION: This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).

BOOT_ACK

Bit 27: Boot Operation Acknowledge.

BLKR

Block Register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLKLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCNT
rw
Toggle Fields

BCNT

Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count.

BLKLEN

Bits 16-31: Data Block Length.

CSTOR

Completion Signal Timeout Register

Offset: 0x1c, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSTOMUL
rw 		CSTOCYC
rw
Toggle Fields

CSTOCYC

Bits 0-3: Completion Signal Timeout Cycle Number.

CSTOMUL

Bits 4-6: Completion Signal Timeout Multiplier.

Allowed values:
0x0: 1: CSTOCYC x 1
0x1: 16: CSTOCYC x 16
0x2: 128: CSTOCYC x 128
0x3: 256: CSTOCYC x 256
0x4: 1024: CSTOCYC x 1024
0x5: 4096: CSTOCYC x 4096
0x6: 65536: CSTOCYC x 65536
0x7: 1048576: CSTOCYC x 1048576

RSPR[[0]]

Response Register

Offset: 0x20, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSP
r
Toggle Fields

RSP

Bits 0-31: Response.

RSPR[[1]]

Response Register

Offset: 0x24, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSP
r
Toggle Fields

RSP

Bits 0-31: Response.

RSPR[[2]]

Response Register

Offset: 0x28, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSP
r
Toggle Fields

RSP

Bits 0-31: Response.

RSPR[[3]]

Response Register

Offset: 0x2c, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSP
r
Toggle Fields

RSP

Bits 0-31: Response.

RDR

Receive Data Register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-31: Data to Read.

TDR

Transmit Data Register

Offset: 0x34, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
w
Toggle Fields

DATA

Bits 0-31: Data to Write.

SR

Status Register

Offset: 0x40, reset: 0x0000C0E5, access: read-only

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNRE
r 		OVRE
r 		ACKRCVE
r 		ACKRCV
r 		XFRDONE
r 		FIFOEMPTY
r 		DMADONE
r 		BLKOVRE
r 		CSTOE
r 		DTOE
r 		DCRCE
r 		RTOE
r 		RENDE
r 		RCRCE
r 		RDIRE
r 		RINDE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSRCV
r 		SDIOWAIT
r 		SDIOIRQforSlotB
r 		SDIOIRQforSlotA
r 		NOTBUSY
r 		DTIP
r 		BLKE
r 		TXRDY
r 		RXRDY
r 		CMDRDY
r
Toggle Fields

CMDRDY

Bit 0: Command Ready.

RXRDY

Bit 1: Receiver Ready.

TXRDY

Bit 2: Transmit Ready.

BLKE

Bit 3: Data Block Ended.

DTIP

Bit 4: Data Transfer in Progress.

NOTBUSY

Bit 5: HSMCI Not Busy.

SDIOIRQforSlotA

Bit 8: None.

SDIOIRQforSlotB

Bit 9: None.

SDIOWAIT

Bit 12: SDIO Read Wait Operation Status.

CSRCV

Bit 13: CE-ATA Completion Signal Received.

RINDE

Bit 16: Response Index Error.

RDIRE

Bit 17: Response Direction Error.

RCRCE

Bit 18: Response CRC Error.

RENDE

Bit 19: Response End Bit Error.

RTOE

Bit 20: Response Time-out Error.

DCRCE

Bit 21: Data CRC Error.

DTOE

Bit 22: Data Time-out Error.

CSTOE

Bit 23: Completion Signal Time-out Error.

BLKOVRE

Bit 24: DMA Block Overrun Error.

DMADONE

Bit 25: DMA Transfer done.

FIFOEMPTY

Bit 26: FIFO empty flag.

XFRDONE

Bit 27: Transfer Done flag.

ACKRCV

Bit 28: Boot Operation Acknowledge Received.

ACKRCVE

Bit 29: Boot Operation Acknowledge Error.

OVRE

Bit 30: Overrun.

UNRE

Bit 31: Underrun.

IER

Interrupt Enable Register

Offset: 0x44, reset: None, access: write-only

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNRE
w 		OVRE
w 		ACKRCVE
w 		ACKRCV
w 		XFRDONE
w 		FIFOEMPTY
w 		DMADONE
w 		BLKOVRE
w 		CSTOE
w 		DTOE
w 		DCRCE
w 		RTOE
w 		RENDE
w 		RCRCE
w 		RDIRE
w 		RINDE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSRCV
w 		SDIOWAIT
w 		SDIOIRQforSlotB
w 		SDIOIRQforSlotA
w 		NOTBUSY
w 		DTIP
w 		BLKE
w 		TXRDY
w 		RXRDY
w 		CMDRDY
w
Toggle Fields

CMDRDY

Bit 0: Command Ready Interrupt Enable.

RXRDY

Bit 1: Receiver Ready Interrupt Enable.

TXRDY

Bit 2: Transmit Ready Interrupt Enable.

BLKE

Bit 3: Data Block Ended Interrupt Enable.

DTIP

Bit 4: Data Transfer in Progress Interrupt Enable.

NOTBUSY

Bit 5: Data Not Busy Interrupt Enable.

SDIOIRQforSlotA

Bit 8: None.

SDIOIRQforSlotB

Bit 9: None.

SDIOWAIT

Bit 12: SDIO Read Wait Operation Status Interrupt Enable.

CSRCV

Bit 13: Completion Signal Received Interrupt Enable.

RINDE

Bit 16: Response Index Error Interrupt Enable.

RDIRE

Bit 17: Response Direction Error Interrupt Enable.

RCRCE

Bit 18: Response CRC Error Interrupt Enable.

RENDE

Bit 19: Response End Bit Error Interrupt Enable.

RTOE

Bit 20: Response Time-out Error Interrupt Enable.

DCRCE

Bit 21: Data CRC Error Interrupt Enable.

DTOE

Bit 22: Data Time-out Error Interrupt Enable.

CSTOE

Bit 23: Completion Signal Timeout Error Interrupt Enable.

BLKOVRE

Bit 24: DMA Block Overrun Error Interrupt Enable.

DMADONE

Bit 25: DMA Transfer completed Interrupt Enable.

FIFOEMPTY

Bit 26: FIFO empty Interrupt enable.

XFRDONE

Bit 27: Transfer Done Interrupt enable.

ACKRCV

Bit 28: Boot Acknowledge Interrupt Enable.

ACKRCVE

Bit 29: Boot Acknowledge Error Interrupt Enable.

OVRE

Bit 30: Overrun Interrupt Enable.

UNRE

Bit 31: Underrun Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x48, reset: None, access: write-only

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNRE
w 		OVRE
w 		ACKRCVE
w 		ACKRCV
w 		XFRDONE
w 		FIFOEMPTY
w 		DMADONE
w 		BLKOVRE
w 		CSTOE
w 		DTOE
w 		DCRCE
w 		RTOE
w 		RENDE
w 		RCRCE
w 		RDIRE
w 		RINDE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSRCV
w 		SDIOWAIT
w 		SDIOIRQforSlotB
w 		SDIOIRQforSlotA
w 		NOTBUSY
w 		DTIP
w 		BLKE
w 		TXRDY
w 		RXRDY
w 		CMDRDY
w
Toggle Fields

CMDRDY

Bit 0: Command Ready Interrupt Disable.

RXRDY

Bit 1: Receiver Ready Interrupt Disable.

TXRDY

Bit 2: Transmit Ready Interrupt Disable.

BLKE

Bit 3: Data Block Ended Interrupt Disable.

DTIP

Bit 4: Data Transfer in Progress Interrupt Disable.

NOTBUSY

Bit 5: Data Not Busy Interrupt Disable.

SDIOIRQforSlotA

Bit 8: None.

SDIOIRQforSlotB

Bit 9: None.

SDIOWAIT

Bit 12: SDIO Read Wait Operation Status Interrupt Disable.

CSRCV

Bit 13: Completion Signal received interrupt Disable.

RINDE

Bit 16: Response Index Error Interrupt Disable.

RDIRE

Bit 17: Response Direction Error Interrupt Disable.

RCRCE

Bit 18: Response CRC Error Interrupt Disable.

RENDE

Bit 19: Response End Bit Error Interrupt Disable.

RTOE

Bit 20: Response Time-out Error Interrupt Disable.

DCRCE

Bit 21: Data CRC Error Interrupt Disable.

DTOE

Bit 22: Data Time-out Error Interrupt Disable.

CSTOE

Bit 23: Completion Signal Time out Error Interrupt Disable.

BLKOVRE

Bit 24: DMA Block Overrun Error Interrupt Disable.

DMADONE

Bit 25: DMA Transfer completed Interrupt Disable.

FIFOEMPTY

Bit 26: FIFO empty Interrupt Disable.

XFRDONE

Bit 27: Transfer Done Interrupt Disable.

ACKRCV

Bit 28: Boot Acknowledge Interrupt Disable.

ACKRCVE

Bit 29: Boot Acknowledge Error Interrupt Disable.

OVRE

Bit 30: Overrun Interrupt Disable.

UNRE

Bit 31: Underrun Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x4c, reset: 0x00000000, access: read-only

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNRE
r 		OVRE
r 		ACKRCVE
r 		ACKRCV
r 		XFRDONE
r 		FIFOEMPTY
r 		DMADONE
r 		BLKOVRE
r 		CSTOE
r 		DTOE
r 		DCRCE
r 		RTOE
r 		RENDE
r 		RCRCE
r 		RDIRE
r 		RINDE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSRCV
r 		SDIOWAIT
r 		SDIOIRQforSlotB
r 		SDIOIRQforSlotA
r 		NOTBUSY
r 		DTIP
r 		BLKE
r 		TXRDY
r 		RXRDY
r 		CMDRDY
r
Toggle Fields

CMDRDY

Bit 0: Command Ready Interrupt Mask.

RXRDY

Bit 1: Receiver Ready Interrupt Mask.

TXRDY

Bit 2: Transmit Ready Interrupt Mask.

BLKE

Bit 3: Data Block Ended Interrupt Mask.

DTIP

Bit 4: Data Transfer in Progress Interrupt Mask.

NOTBUSY

Bit 5: Data Not Busy Interrupt Mask.

SDIOIRQforSlotA

Bit 8: None.

SDIOIRQforSlotB

Bit 9: None.

SDIOWAIT

Bit 12: SDIO Read Wait Operation Status Interrupt Mask.

CSRCV

Bit 13: Completion Signal Received Interrupt Mask.

RINDE

Bit 16: Response Index Error Interrupt Mask.

RDIRE

Bit 17: Response Direction Error Interrupt Mask.

RCRCE

Bit 18: Response CRC Error Interrupt Mask.

RENDE

Bit 19: Response End Bit Error Interrupt Mask.

RTOE

Bit 20: Response Time-out Error Interrupt Mask.

DCRCE

Bit 21: Data CRC Error Interrupt Mask.

DTOE

Bit 22: Data Time-out Error Interrupt Mask.

CSTOE

Bit 23: Completion Signal Time-out Error Interrupt Mask.

BLKOVRE

Bit 24: DMA Block Overrun Error Interrupt Mask.

DMADONE

Bit 25: DMA Transfer Completed Interrupt Mask.

FIFOEMPTY

Bit 26: FIFO Empty Interrupt Mask.

XFRDONE

Bit 27: Transfer Done Interrupt Mask.

ACKRCV

Bit 28: Boot Operation Acknowledge Received Interrupt Mask.

ACKRCVE

Bit 29: Boot Operation Acknowledge Error Interrupt Mask.

OVRE

Bit 30: Overrun Interrupt Mask.

UNRE

Bit 31: Underrun Interrupt Mask.

DMA

DMA Configuration Register

Offset: 0x50, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROPT
rw 		DMAEN
rw 		CHKSIZE
rw 		OFFSET
rw
Toggle Fields

OFFSET

Bits 0-1: DMA Write Buffer Offset.

CHKSIZE

Bit 4: DMA Channel Read and Write Chunk Size.

Allowed values:
0: 1: 1 data available
1: 4: 4 data available

DMAEN

Bit 8: DMA Hardware Handshaking Enable.

ROPT

Bit 12: Read Optimization with padding.

CFG

Configuration Register

Offset: 0x54, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSYNC
rw 		HSMODE
rw 		FERRCTRL
rw 		FIFOMODE
rw
Toggle Fields

FIFOMODE

Bit 0: HSMCI Internal FIFO control mode.

FERRCTRL

Bit 4: Flow Error flag reset control mode.

HSMODE

Bit 8: High Speed Mode.

LSYNC

Bit 12: Synchronize on the last block.

WPMR

Write Protection Mode Register

Offset: 0xe4, reset: None, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect Key.

Allowed values:
0x4D4349: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

WPSR

Write Protection Status Register

Offset: 0xe8, reset: None, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-23: Write Protection Violation Source.

FIFO[[0]]

FIFO Memory Aperture0

Offset: 0x200, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[1]]

FIFO Memory Aperture0

Offset: 0x204, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[2]]

FIFO Memory Aperture0

Offset: 0x208, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[3]]

FIFO Memory Aperture0

Offset: 0x20c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[4]]

FIFO Memory Aperture0

Offset: 0x210, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[5]]

FIFO Memory Aperture0

Offset: 0x214, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[6]]

FIFO Memory Aperture0

Offset: 0x218, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[7]]

FIFO Memory Aperture0

Offset: 0x21c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[8]]

FIFO Memory Aperture0

Offset: 0x220, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[9]]

FIFO Memory Aperture0

Offset: 0x224, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[10]]

FIFO Memory Aperture0

Offset: 0x228, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[11]]

FIFO Memory Aperture0

Offset: 0x22c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[12]]

FIFO Memory Aperture0

Offset: 0x230, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[13]]

FIFO Memory Aperture0

Offset: 0x234, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[14]]

FIFO Memory Aperture0

Offset: 0x238, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[15]]

FIFO Memory Aperture0

Offset: 0x23c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[16]]

FIFO Memory Aperture0

Offset: 0x240, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[17]]

FIFO Memory Aperture0

Offset: 0x244, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[18]]

FIFO Memory Aperture0

Offset: 0x248, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[19]]

FIFO Memory Aperture0

Offset: 0x24c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[20]]

FIFO Memory Aperture0

Offset: 0x250, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[21]]

FIFO Memory Aperture0

Offset: 0x254, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[22]]

FIFO Memory Aperture0

Offset: 0x258, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[23]]

FIFO Memory Aperture0

Offset: 0x25c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[24]]

FIFO Memory Aperture0

Offset: 0x260, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[25]]

FIFO Memory Aperture0

Offset: 0x264, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[26]]

FIFO Memory Aperture0

Offset: 0x268, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[27]]

FIFO Memory Aperture0

Offset: 0x26c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[28]]

FIFO Memory Aperture0

Offset: 0x270, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[29]]

FIFO Memory Aperture0

Offset: 0x274, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[30]]

FIFO Memory Aperture0

Offset: 0x278, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[31]]

FIFO Memory Aperture0

Offset: 0x27c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[32]]

FIFO Memory Aperture0

Offset: 0x280, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[33]]

FIFO Memory Aperture0

Offset: 0x284, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[34]]

FIFO Memory Aperture0

Offset: 0x288, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[35]]

FIFO Memory Aperture0

Offset: 0x28c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[36]]

FIFO Memory Aperture0

Offset: 0x290, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[37]]

FIFO Memory Aperture0

Offset: 0x294, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[38]]

FIFO Memory Aperture0

Offset: 0x298, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[39]]

FIFO Memory Aperture0

Offset: 0x29c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[40]]

FIFO Memory Aperture0

Offset: 0x2a0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[41]]

FIFO Memory Aperture0

Offset: 0x2a4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[42]]

FIFO Memory Aperture0

Offset: 0x2a8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[43]]

FIFO Memory Aperture0

Offset: 0x2ac, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[44]]

FIFO Memory Aperture0

Offset: 0x2b0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[45]]

FIFO Memory Aperture0

Offset: 0x2b4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[46]]

FIFO Memory Aperture0

Offset: 0x2b8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[47]]

FIFO Memory Aperture0

Offset: 0x2bc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[48]]

FIFO Memory Aperture0

Offset: 0x2c0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[49]]

FIFO Memory Aperture0

Offset: 0x2c4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[50]]

FIFO Memory Aperture0

Offset: 0x2c8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[51]]

FIFO Memory Aperture0

Offset: 0x2cc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[52]]

FIFO Memory Aperture0

Offset: 0x2d0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[53]]

FIFO Memory Aperture0

Offset: 0x2d4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[54]]

FIFO Memory Aperture0

Offset: 0x2d8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[55]]

FIFO Memory Aperture0

Offset: 0x2dc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[56]]

FIFO Memory Aperture0

Offset: 0x2e0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[57]]

FIFO Memory Aperture0

Offset: 0x2e4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[58]]

FIFO Memory Aperture0

Offset: 0x2e8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[59]]

FIFO Memory Aperture0

Offset: 0x2ec, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[60]]

FIFO Memory Aperture0

Offset: 0x2f0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[61]]

FIFO Memory Aperture0

Offset: 0x2f4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[62]]

FIFO Memory Aperture0

Offset: 0x2f8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[63]]

FIFO Memory Aperture0

Offset: 0x2fc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[64]]

FIFO Memory Aperture0

Offset: 0x300, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[65]]

FIFO Memory Aperture0

Offset: 0x304, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[66]]

FIFO Memory Aperture0

Offset: 0x308, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[67]]

FIFO Memory Aperture0

Offset: 0x30c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[68]]

FIFO Memory Aperture0

Offset: 0x310, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[69]]

FIFO Memory Aperture0

Offset: 0x314, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[70]]

FIFO Memory Aperture0

Offset: 0x318, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[71]]

FIFO Memory Aperture0

Offset: 0x31c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[72]]

FIFO Memory Aperture0

Offset: 0x320, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[73]]

FIFO Memory Aperture0

Offset: 0x324, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[74]]

FIFO Memory Aperture0

Offset: 0x328, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[75]]

FIFO Memory Aperture0

Offset: 0x32c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[76]]

FIFO Memory Aperture0

Offset: 0x330, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[77]]

FIFO Memory Aperture0

Offset: 0x334, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[78]]

FIFO Memory Aperture0

Offset: 0x338, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[79]]

FIFO Memory Aperture0

Offset: 0x33c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[80]]

FIFO Memory Aperture0

Offset: 0x340, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[81]]

FIFO Memory Aperture0

Offset: 0x344, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[82]]

FIFO Memory Aperture0

Offset: 0x348, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[83]]

FIFO Memory Aperture0

Offset: 0x34c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[84]]

FIFO Memory Aperture0

Offset: 0x350, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[85]]

FIFO Memory Aperture0

Offset: 0x354, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[86]]

FIFO Memory Aperture0

Offset: 0x358, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[87]]

FIFO Memory Aperture0

Offset: 0x35c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[88]]

FIFO Memory Aperture0

Offset: 0x360, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[89]]

FIFO Memory Aperture0

Offset: 0x364, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[90]]

FIFO Memory Aperture0

Offset: 0x368, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[91]]

FIFO Memory Aperture0

Offset: 0x36c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[92]]

FIFO Memory Aperture0

Offset: 0x370, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[93]]

FIFO Memory Aperture0

Offset: 0x374, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[94]]

FIFO Memory Aperture0

Offset: 0x378, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[95]]

FIFO Memory Aperture0

Offset: 0x37c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[96]]

FIFO Memory Aperture0

Offset: 0x380, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[97]]

FIFO Memory Aperture0

Offset: 0x384, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[98]]

FIFO Memory Aperture0

Offset: 0x388, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[99]]

FIFO Memory Aperture0

Offset: 0x38c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[100]]

FIFO Memory Aperture0

Offset: 0x390, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[101]]

FIFO Memory Aperture0

Offset: 0x394, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[102]]

FIFO Memory Aperture0

Offset: 0x398, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[103]]

FIFO Memory Aperture0

Offset: 0x39c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[104]]

FIFO Memory Aperture0

Offset: 0x3a0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[105]]

FIFO Memory Aperture0

Offset: 0x3a4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[106]]

FIFO Memory Aperture0

Offset: 0x3a8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[107]]

FIFO Memory Aperture0

Offset: 0x3ac, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[108]]

FIFO Memory Aperture0

Offset: 0x3b0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[109]]

FIFO Memory Aperture0

Offset: 0x3b4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[110]]

FIFO Memory Aperture0

Offset: 0x3b8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[111]]

FIFO Memory Aperture0

Offset: 0x3bc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[112]]

FIFO Memory Aperture0

Offset: 0x3c0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[113]]

FIFO Memory Aperture0

Offset: 0x3c4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[114]]

FIFO Memory Aperture0

Offset: 0x3c8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[115]]

FIFO Memory Aperture0

Offset: 0x3cc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[116]]

FIFO Memory Aperture0

Offset: 0x3d0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[117]]

FIFO Memory Aperture0

Offset: 0x3d4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[118]]

FIFO Memory Aperture0

Offset: 0x3d8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[119]]

FIFO Memory Aperture0

Offset: 0x3dc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[120]]

FIFO Memory Aperture0

Offset: 0x3e0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[121]]

FIFO Memory Aperture0

Offset: 0x3e4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[122]]

FIFO Memory Aperture0

Offset: 0x3e8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[123]]

FIFO Memory Aperture0

Offset: 0x3ec, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[124]]

FIFO Memory Aperture0

Offset: 0x3f0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[125]]

FIFO Memory Aperture0

Offset: 0x3f4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[126]]

FIFO Memory Aperture0

Offset: 0x3f8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[127]]

FIFO Memory Aperture0

Offset: 0x3fc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[128]]

FIFO Memory Aperture0

Offset: 0x400, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[129]]

FIFO Memory Aperture0

Offset: 0x404, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[130]]

FIFO Memory Aperture0

Offset: 0x408, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[131]]

FIFO Memory Aperture0

Offset: 0x40c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[132]]

FIFO Memory Aperture0

Offset: 0x410, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[133]]

FIFO Memory Aperture0

Offset: 0x414, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[134]]

FIFO Memory Aperture0

Offset: 0x418, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[135]]

FIFO Memory Aperture0

Offset: 0x41c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[136]]

FIFO Memory Aperture0

Offset: 0x420, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[137]]

FIFO Memory Aperture0

Offset: 0x424, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[138]]

FIFO Memory Aperture0

Offset: 0x428, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[139]]

FIFO Memory Aperture0

Offset: 0x42c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[140]]

FIFO Memory Aperture0

Offset: 0x430, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[141]]

FIFO Memory Aperture0

Offset: 0x434, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[142]]

FIFO Memory Aperture0

Offset: 0x438, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[143]]

FIFO Memory Aperture0

Offset: 0x43c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[144]]

FIFO Memory Aperture0

Offset: 0x440, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[145]]

FIFO Memory Aperture0

Offset: 0x444, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[146]]

FIFO Memory Aperture0

Offset: 0x448, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[147]]

FIFO Memory Aperture0

Offset: 0x44c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[148]]

FIFO Memory Aperture0

Offset: 0x450, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[149]]

FIFO Memory Aperture0

Offset: 0x454, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[150]]

FIFO Memory Aperture0

Offset: 0x458, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[151]]

FIFO Memory Aperture0

Offset: 0x45c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[152]]

FIFO Memory Aperture0

Offset: 0x460, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[153]]

FIFO Memory Aperture0

Offset: 0x464, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[154]]

FIFO Memory Aperture0

Offset: 0x468, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[155]]

FIFO Memory Aperture0

Offset: 0x46c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[156]]

FIFO Memory Aperture0

Offset: 0x470, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[157]]

FIFO Memory Aperture0

Offset: 0x474, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[158]]

FIFO Memory Aperture0

Offset: 0x478, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[159]]

FIFO Memory Aperture0

Offset: 0x47c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[160]]

FIFO Memory Aperture0

Offset: 0x480, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[161]]

FIFO Memory Aperture0

Offset: 0x484, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[162]]

FIFO Memory Aperture0

Offset: 0x488, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[163]]

FIFO Memory Aperture0

Offset: 0x48c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[164]]

FIFO Memory Aperture0

Offset: 0x490, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[165]]

FIFO Memory Aperture0

Offset: 0x494, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[166]]

FIFO Memory Aperture0

Offset: 0x498, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[167]]

FIFO Memory Aperture0

Offset: 0x49c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[168]]

FIFO Memory Aperture0

Offset: 0x4a0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[169]]

FIFO Memory Aperture0

Offset: 0x4a4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[170]]

FIFO Memory Aperture0

Offset: 0x4a8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[171]]

FIFO Memory Aperture0

Offset: 0x4ac, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[172]]

FIFO Memory Aperture0

Offset: 0x4b0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[173]]

FIFO Memory Aperture0

Offset: 0x4b4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[174]]

FIFO Memory Aperture0

Offset: 0x4b8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[175]]

FIFO Memory Aperture0

Offset: 0x4bc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[176]]

FIFO Memory Aperture0

Offset: 0x4c0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[177]]

FIFO Memory Aperture0

Offset: 0x4c4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[178]]

FIFO Memory Aperture0

Offset: 0x4c8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[179]]

FIFO Memory Aperture0

Offset: 0x4cc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[180]]

FIFO Memory Aperture0

Offset: 0x4d0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[181]]

FIFO Memory Aperture0

Offset: 0x4d4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[182]]

FIFO Memory Aperture0

Offset: 0x4d8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[183]]

FIFO Memory Aperture0

Offset: 0x4dc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[184]]

FIFO Memory Aperture0

Offset: 0x4e0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[185]]

FIFO Memory Aperture0

Offset: 0x4e4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[186]]

FIFO Memory Aperture0

Offset: 0x4e8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[187]]

FIFO Memory Aperture0

Offset: 0x4ec, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[188]]

FIFO Memory Aperture0

Offset: 0x4f0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[189]]

FIFO Memory Aperture0

Offset: 0x4f4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[190]]

FIFO Memory Aperture0

Offset: 0x4f8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[191]]

FIFO Memory Aperture0

Offset: 0x4fc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[192]]

FIFO Memory Aperture0

Offset: 0x500, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[193]]

FIFO Memory Aperture0

Offset: 0x504, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[194]]

FIFO Memory Aperture0

Offset: 0x508, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[195]]

FIFO Memory Aperture0

Offset: 0x50c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[196]]

FIFO Memory Aperture0

Offset: 0x510, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[197]]

FIFO Memory Aperture0

Offset: 0x514, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[198]]

FIFO Memory Aperture0

Offset: 0x518, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[199]]

FIFO Memory Aperture0

Offset: 0x51c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[200]]

FIFO Memory Aperture0

Offset: 0x520, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[201]]

FIFO Memory Aperture0

Offset: 0x524, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[202]]

FIFO Memory Aperture0

Offset: 0x528, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[203]]

FIFO Memory Aperture0

Offset: 0x52c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[204]]

FIFO Memory Aperture0

Offset: 0x530, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[205]]

FIFO Memory Aperture0

Offset: 0x534, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[206]]

FIFO Memory Aperture0

Offset: 0x538, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[207]]

FIFO Memory Aperture0

Offset: 0x53c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[208]]

FIFO Memory Aperture0

Offset: 0x540, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[209]]

FIFO Memory Aperture0

Offset: 0x544, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[210]]

FIFO Memory Aperture0

Offset: 0x548, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[211]]

FIFO Memory Aperture0

Offset: 0x54c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[212]]

FIFO Memory Aperture0

Offset: 0x550, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[213]]

FIFO Memory Aperture0

Offset: 0x554, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[214]]

FIFO Memory Aperture0

Offset: 0x558, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[215]]

FIFO Memory Aperture0

Offset: 0x55c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[216]]

FIFO Memory Aperture0

Offset: 0x560, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[217]]

FIFO Memory Aperture0

Offset: 0x564, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[218]]

FIFO Memory Aperture0

Offset: 0x568, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[219]]

FIFO Memory Aperture0

Offset: 0x56c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[220]]

FIFO Memory Aperture0

Offset: 0x570, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[221]]

FIFO Memory Aperture0

Offset: 0x574, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[222]]

FIFO Memory Aperture0

Offset: 0x578, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[223]]

FIFO Memory Aperture0

Offset: 0x57c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[224]]

FIFO Memory Aperture0

Offset: 0x580, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[225]]

FIFO Memory Aperture0

Offset: 0x584, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[226]]

FIFO Memory Aperture0

Offset: 0x588, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[227]]

FIFO Memory Aperture0

Offset: 0x58c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[228]]

FIFO Memory Aperture0

Offset: 0x590, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[229]]

FIFO Memory Aperture0

Offset: 0x594, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[230]]

FIFO Memory Aperture0

Offset: 0x598, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[231]]

FIFO Memory Aperture0

Offset: 0x59c, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[232]]

FIFO Memory Aperture0

Offset: 0x5a0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[233]]

FIFO Memory Aperture0

Offset: 0x5a4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[234]]

FIFO Memory Aperture0

Offset: 0x5a8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[235]]

FIFO Memory Aperture0

Offset: 0x5ac, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[236]]

FIFO Memory Aperture0

Offset: 0x5b0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[237]]

FIFO Memory Aperture0

Offset: 0x5b4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[238]]

FIFO Memory Aperture0

Offset: 0x5b8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[239]]

FIFO Memory Aperture0

Offset: 0x5bc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[240]]

FIFO Memory Aperture0

Offset: 0x5c0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[241]]

FIFO Memory Aperture0

Offset: 0x5c4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[242]]

FIFO Memory Aperture0

Offset: 0x5c8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[243]]

FIFO Memory Aperture0

Offset: 0x5cc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[244]]

FIFO Memory Aperture0

Offset: 0x5d0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[245]]

FIFO Memory Aperture0

Offset: 0x5d4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[246]]

FIFO Memory Aperture0

Offset: 0x5d8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[247]]

FIFO Memory Aperture0

Offset: 0x5dc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[248]]

FIFO Memory Aperture0

Offset: 0x5e0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[249]]

FIFO Memory Aperture0

Offset: 0x5e4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[250]]

FIFO Memory Aperture0

Offset: 0x5e8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[251]]

FIFO Memory Aperture0

Offset: 0x5ec, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[252]]

FIFO Memory Aperture0

Offset: 0x5f0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[253]]

FIFO Memory Aperture0

Offset: 0x5f4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[254]]

FIFO Memory Aperture0

Offset: 0x5f8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

FIFO[[255]]

FIFO Memory Aperture0

Offset: 0x5fc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields

DATA

Bits 0-31: Data to Read or Data to Write.

MATRIX

0x400e0400: AHB Bus Matrix

2/107 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MATRIX_MCFG[[0]]
0x4 MATRIX_MCFG[[1]]
0x8 MATRIX_MCFG[[2]]
0xc MATRIX_MCFG[[3]]
0x10 MATRIX_MCFG[[4]]
0x14 MATRIX_MCFG[[5]]
0x40 MATRIX_SCFG[[0]]
0x44 MATRIX_SCFG[[1]]
0x48 MATRIX_SCFG[[2]]
0x4c MATRIX_SCFG[[3]]
0x50 MATRIX_SCFG[[4]]
0x54 MATRIX_SCFG[[5]]
0x58 MATRIX_SCFG[[6]]
0x5c MATRIX_SCFG[[7]]
0x60 MATRIX_SCFG[[8]]
0x80 MATRIX_PRAS0
0x88 MATRIX_PRAS1
0x90 MATRIX_PRAS2
0x98 MATRIX_PRAS3
0xa0 MATRIX_PRAS4
0xa8 MATRIX_PRAS5
0xb0 MATRIX_PRAS6
0xb8 MATRIX_PRAS7
0xc0 MATRIX_PRAS8
0x100 MATRIX_MRCR
0x114 CCFG_SYSIO
0x1e4 MATRIX_WPMR
0x1e8 MATRIX_WPSR

MATRIX_MCFG[[0]]

Master Configuration Register

Offset: 0x0, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ULBT
rw
Toggle Fields

ULBT

Bits 0-2: Undefined Length Burst Type.

MATRIX_MCFG[[1]]

Master Configuration Register

Offset: 0x4, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ULBT
rw
Toggle Fields

ULBT

Bits 0-2: Undefined Length Burst Type.

MATRIX_MCFG[[2]]

Master Configuration Register

Offset: 0x8, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ULBT
rw
Toggle Fields

ULBT

Bits 0-2: Undefined Length Burst Type.

MATRIX_MCFG[[3]]

Master Configuration Register

Offset: 0xc, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ULBT
rw
Toggle Fields

ULBT

Bits 0-2: Undefined Length Burst Type.

MATRIX_MCFG[[4]]

Master Configuration Register

Offset: 0x10, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ULBT
rw
Toggle Fields

ULBT

Bits 0-2: Undefined Length Burst Type.

MATRIX_MCFG[[5]]

Master Configuration Register

Offset: 0x14, reset: None, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ULBT
rw
Toggle Fields

ULBT

Bits 0-2: Undefined Length Burst Type.

MATRIX_SCFG[[0]]

Slave Configuration Register

Offset: 0x40, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[1]]

Slave Configuration Register

Offset: 0x44, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[2]]

Slave Configuration Register

Offset: 0x48, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[3]]

Slave Configuration Register

Offset: 0x4c, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[4]]

Slave Configuration Register

Offset: 0x50, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[5]]

Slave Configuration Register

Offset: 0x54, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[6]]

Slave Configuration Register

Offset: 0x58, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[7]]

Slave Configuration Register

Offset: 0x5c, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_SCFG[[8]]

Slave Configuration Register

Offset: 0x60, reset: None, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARBT
rw 		FIXED_DEFMSTR
rw 		DEFMSTR_TYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLOT_CYCLE
rw
Toggle Fields

SLOT_CYCLE

Bits 0-7: Maximum Number of Allowed Cycles for a Burst.

DEFMSTR_TYPE

Bits 16-17: Default Master Type.

FIXED_DEFMSTR

Bits 18-20: Fixed Default Master.

ARBT

Bits 24-25: Arbitration Type.

MATRIX_PRAS0

Priority Register A for Slave 0

Offset: 0x80, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS1

Priority Register A for Slave 1

Offset: 0x88, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS2

Priority Register A for Slave 2

Offset: 0x90, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS3

Priority Register A for Slave 3

Offset: 0x98, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS4

Priority Register A for Slave 4

Offset: 0xa0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS5

Priority Register A for Slave 5

Offset: 0xa8, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS6

Priority Register A for Slave 6

Offset: 0xb0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS7

Priority Register A for Slave 7

Offset: 0xb8, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_PRAS8

Priority Register A for Slave 8

Offset: 0xc0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M5PR
rw 		M4PR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3PR
rw 		M2PR
rw 		M1PR
rw 		M0PR
rw
Toggle Fields

M0PR

Bits 0-1: Master 0 Priority.

M1PR

Bits 4-5: Master 1 Priority.

M2PR

Bits 8-9: Master 2 Priority.

M3PR

Bits 12-13: Master 3 Priority.

M4PR

Bits 16-17: Master 4 Priority.

M5PR

Bits 20-21: Master 5 Priority.

MATRIX_MRCR

Master Remap Control Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCB5
rw 		RCB4
rw 		RCB3
rw 		RCB2
rw 		RCB1
rw 		RCB0
rw
Toggle Fields

RCB0

Bit 0: Remap Command Bit for AHB Master 0.

RCB1

Bit 1: Remap Command Bit for AHB Master 1.

RCB2

Bit 2: Remap Command Bit for AHB Master 2.

RCB3

Bit 3: Remap Command Bit for AHB Master 3.

RCB4

Bits 4-5: Remap Command Bit for AHB Master 4.

RCB5

Bit 6: Remap Command Bit for AHB Master 5.

CCFG_SYSIO

System I/O Configuration register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSIO12
rw
Toggle Fields

SYSIO12

Bit 12: PC0 or ERASE Assignment.

MATRIX_WPMR

Write Protect Mode Register

Offset: 0x1e4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect ENable.

WPKEY

Bits 8-31: Write Protect KEY (Write-only).

MATRIX_WPSR

Write Protect Status Register

Offset: 0x1e8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

PIOA

0x400e0e00: Parallel Input/Output Controller A

450/1285 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PER
0x4 PDR
0x8 PSR
0x10 OER
0x14 ODR
0x18 OSR
0x20 IFER
0x24 IFDR
0x28 IFSR
0x30 SODR
0x34 CODR
0x38 ODSR
0x3c PDSR
0x40 IER
0x44 IDR
0x48 IMR
0x4c ISR
0x50 MDER
0x54 MDDR
0x58 MDSR
0x60 PUDR
0x64 PUER
0x68 PUSR
0x70 ABSR
0x80 SCIFSR
0x84 DIFSR
0x88 IFDGSR
0x8c SCDR
0xa0 OWER
0xa4 OWDR
0xa8 OWSR
0xb0 AIMER
0xb4 AIMDR
0xb8 AIMMR
0xc0 ESR
0xc4 LSR
0xc8 ELSR
0xd0 FELLSR
0xd4 REHLSR
0xd8 FRLHSR
0xe0 LOCKSR
0xe4 WPMR
0xe8 WPSR

PER

PIO Enable Register

Offset: 0x0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Enable.

P1

Bit 1: PIO Enable.

P2

Bit 2: PIO Enable.

P3

Bit 3: PIO Enable.

P4

Bit 4: PIO Enable.

P5

Bit 5: PIO Enable.

P6

Bit 6: PIO Enable.

P7

Bit 7: PIO Enable.

P8

Bit 8: PIO Enable.

P9

Bit 9: PIO Enable.

P10

Bit 10: PIO Enable.

P11

Bit 11: PIO Enable.

P12

Bit 12: PIO Enable.

P13

Bit 13: PIO Enable.

P14

Bit 14: PIO Enable.

P15

Bit 15: PIO Enable.

P16

Bit 16: PIO Enable.

P17

Bit 17: PIO Enable.

P18

Bit 18: PIO Enable.

P19

Bit 19: PIO Enable.

P20

Bit 20: PIO Enable.

P21

Bit 21: PIO Enable.

P22

Bit 22: PIO Enable.

P23

Bit 23: PIO Enable.

P24

Bit 24: PIO Enable.

P25

Bit 25: PIO Enable.

P26

Bit 26: PIO Enable.

P27

Bit 27: PIO Enable.

P28

Bit 28: PIO Enable.

P29

Bit 29: PIO Enable.

P30

Bit 30: PIO Enable.

P31

Bit 31: PIO Enable.

PDR

PIO Disable Register

Offset: 0x4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Disable.

P1

Bit 1: PIO Disable.

P2

Bit 2: PIO Disable.

P3

Bit 3: PIO Disable.

P4

Bit 4: PIO Disable.

P5

Bit 5: PIO Disable.

P6

Bit 6: PIO Disable.

P7

Bit 7: PIO Disable.

P8

Bit 8: PIO Disable.

P9

Bit 9: PIO Disable.

P10

Bit 10: PIO Disable.

P11

Bit 11: PIO Disable.

P12

Bit 12: PIO Disable.

P13

Bit 13: PIO Disable.

P14

Bit 14: PIO Disable.

P15

Bit 15: PIO Disable.

P16

Bit 16: PIO Disable.

P17

Bit 17: PIO Disable.

P18

Bit 18: PIO Disable.

P19

Bit 19: PIO Disable.

P20

Bit 20: PIO Disable.

P21

Bit 21: PIO Disable.

P22

Bit 22: PIO Disable.

P23

Bit 23: PIO Disable.

P24

Bit 24: PIO Disable.

P25

Bit 25: PIO Disable.

P26

Bit 26: PIO Disable.

P27

Bit 27: PIO Disable.

P28

Bit 28: PIO Disable.

P29

Bit 29: PIO Disable.

P30

Bit 30: PIO Disable.

P31

Bit 31: PIO Disable.

PSR

PIO Status Register

Offset: 0x8, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: PIO Status.

P1

Bit 1: PIO Status.

P2

Bit 2: PIO Status.

P3

Bit 3: PIO Status.

P4

Bit 4: PIO Status.

P5

Bit 5: PIO Status.

P6

Bit 6: PIO Status.

P7

Bit 7: PIO Status.

P8

Bit 8: PIO Status.

P9

Bit 9: PIO Status.

P10

Bit 10: PIO Status.

P11

Bit 11: PIO Status.

P12

Bit 12: PIO Status.

P13

Bit 13: PIO Status.

P14

Bit 14: PIO Status.

P15

Bit 15: PIO Status.

P16

Bit 16: PIO Status.

P17

Bit 17: PIO Status.

P18

Bit 18: PIO Status.

P19

Bit 19: PIO Status.

P20

Bit 20: PIO Status.

P21

Bit 21: PIO Status.

P22

Bit 22: PIO Status.

P23

Bit 23: PIO Status.

P24

Bit 24: PIO Status.

P25

Bit 25: PIO Status.

P26

Bit 26: PIO Status.

P27

Bit 27: PIO Status.

P28

Bit 28: PIO Status.

P29

Bit 29: PIO Status.

P30

Bit 30: PIO Status.

P31

Bit 31: PIO Status.

OER

Output Enable Register

Offset: 0x10, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Enable.

P1

Bit 1: Output Enable.

P2

Bit 2: Output Enable.

P3

Bit 3: Output Enable.

P4

Bit 4: Output Enable.

P5

Bit 5: Output Enable.

P6

Bit 6: Output Enable.

P7

Bit 7: Output Enable.

P8

Bit 8: Output Enable.

P9

Bit 9: Output Enable.

P10

Bit 10: Output Enable.

P11

Bit 11: Output Enable.

P12

Bit 12: Output Enable.

P13

Bit 13: Output Enable.

P14

Bit 14: Output Enable.

P15

Bit 15: Output Enable.

P16

Bit 16: Output Enable.

P17

Bit 17: Output Enable.

P18

Bit 18: Output Enable.

P19

Bit 19: Output Enable.

P20

Bit 20: Output Enable.

P21

Bit 21: Output Enable.

P22

Bit 22: Output Enable.

P23

Bit 23: Output Enable.

P24

Bit 24: Output Enable.

P25

Bit 25: Output Enable.

P26

Bit 26: Output Enable.

P27

Bit 27: Output Enable.

P28

Bit 28: Output Enable.

P29

Bit 29: Output Enable.

P30

Bit 30: Output Enable.

P31

Bit 31: Output Enable.

ODR

Output Disable Register

Offset: 0x14, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Disable.

P1

Bit 1: Output Disable.

P2

Bit 2: Output Disable.

P3

Bit 3: Output Disable.

P4

Bit 4: Output Disable.

P5

Bit 5: Output Disable.

P6

Bit 6: Output Disable.

P7

Bit 7: Output Disable.

P8

Bit 8: Output Disable.

P9

Bit 9: Output Disable.

P10

Bit 10: Output Disable.

P11

Bit 11: Output Disable.

P12

Bit 12: Output Disable.

P13

Bit 13: Output Disable.

P14

Bit 14: Output Disable.

P15

Bit 15: Output Disable.

P16

Bit 16: Output Disable.

P17

Bit 17: Output Disable.

P18

Bit 18: Output Disable.

P19

Bit 19: Output Disable.

P20

Bit 20: Output Disable.

P21

Bit 21: Output Disable.

P22

Bit 22: Output Disable.

P23

Bit 23: Output Disable.

P24

Bit 24: Output Disable.

P25

Bit 25: Output Disable.

P26

Bit 26: Output Disable.

P27

Bit 27: Output Disable.

P28

Bit 28: Output Disable.

P29

Bit 29: Output Disable.

P30

Bit 30: Output Disable.

P31

Bit 31: Output Disable.

OSR

Output Status Register

Offset: 0x18, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Status.

P1

Bit 1: Output Status.

P2

Bit 2: Output Status.

P3

Bit 3: Output Status.

P4

Bit 4: Output Status.

P5

Bit 5: Output Status.

P6

Bit 6: Output Status.

P7

Bit 7: Output Status.

P8

Bit 8: Output Status.

P9

Bit 9: Output Status.

P10

Bit 10: Output Status.

P11

Bit 11: Output Status.

P12

Bit 12: Output Status.

P13

Bit 13: Output Status.

P14

Bit 14: Output Status.

P15

Bit 15: Output Status.

P16

Bit 16: Output Status.

P17

Bit 17: Output Status.

P18

Bit 18: Output Status.

P19

Bit 19: Output Status.

P20

Bit 20: Output Status.

P21

Bit 21: Output Status.

P22

Bit 22: Output Status.

P23

Bit 23: Output Status.

P24

Bit 24: Output Status.

P25

Bit 25: Output Status.

P26

Bit 26: Output Status.

P27

Bit 27: Output Status.

P28

Bit 28: Output Status.

P29

Bit 29: Output Status.

P30

Bit 30: Output Status.

P31

Bit 31: Output Status.

IFER

Glitch Input Filter Enable Register

Offset: 0x20, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Enable.

P1

Bit 1: Input Filter Enable.

P2

Bit 2: Input Filter Enable.

P3

Bit 3: Input Filter Enable.

P4

Bit 4: Input Filter Enable.

P5

Bit 5: Input Filter Enable.

P6

Bit 6: Input Filter Enable.

P7

Bit 7: Input Filter Enable.

P8

Bit 8: Input Filter Enable.

P9

Bit 9: Input Filter Enable.

P10

Bit 10: Input Filter Enable.

P11

Bit 11: Input Filter Enable.

P12

Bit 12: Input Filter Enable.

P13

Bit 13: Input Filter Enable.

P14

Bit 14: Input Filter Enable.

P15

Bit 15: Input Filter Enable.

P16

Bit 16: Input Filter Enable.

P17

Bit 17: Input Filter Enable.

P18

Bit 18: Input Filter Enable.

P19

Bit 19: Input Filter Enable.

P20

Bit 20: Input Filter Enable.

P21

Bit 21: Input Filter Enable.

P22

Bit 22: Input Filter Enable.

P23

Bit 23: Input Filter Enable.

P24

Bit 24: Input Filter Enable.

P25

Bit 25: Input Filter Enable.

P26

Bit 26: Input Filter Enable.

P27

Bit 27: Input Filter Enable.

P28

Bit 28: Input Filter Enable.

P29

Bit 29: Input Filter Enable.

P30

Bit 30: Input Filter Enable.

P31

Bit 31: Input Filter Enable.

IFDR

Glitch Input Filter Disable Register

Offset: 0x24, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Disable.

P1

Bit 1: Input Filter Disable.

P2

Bit 2: Input Filter Disable.

P3

Bit 3: Input Filter Disable.

P4

Bit 4: Input Filter Disable.

P5

Bit 5: Input Filter Disable.

P6

Bit 6: Input Filter Disable.

P7

Bit 7: Input Filter Disable.

P8

Bit 8: Input Filter Disable.

P9

Bit 9: Input Filter Disable.

P10

Bit 10: Input Filter Disable.

P11

Bit 11: Input Filter Disable.

P12

Bit 12: Input Filter Disable.

P13

Bit 13: Input Filter Disable.

P14

Bit 14: Input Filter Disable.

P15

Bit 15: Input Filter Disable.

P16

Bit 16: Input Filter Disable.

P17

Bit 17: Input Filter Disable.

P18

Bit 18: Input Filter Disable.

P19

Bit 19: Input Filter Disable.

P20

Bit 20: Input Filter Disable.

P21

Bit 21: Input Filter Disable.

P22

Bit 22: Input Filter Disable.

P23

Bit 23: Input Filter Disable.

P24

Bit 24: Input Filter Disable.

P25

Bit 25: Input Filter Disable.

P26

Bit 26: Input Filter Disable.

P27

Bit 27: Input Filter Disable.

P28

Bit 28: Input Filter Disable.

P29

Bit 29: Input Filter Disable.

P30

Bit 30: Input Filter Disable.

P31

Bit 31: Input Filter Disable.

IFSR

Glitch Input Filter Status Register

Offset: 0x28, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Filer Status.

P1

Bit 1: Input Filer Status.

P2

Bit 2: Input Filer Status.

P3

Bit 3: Input Filer Status.

P4

Bit 4: Input Filer Status.

P5

Bit 5: Input Filer Status.

P6

Bit 6: Input Filer Status.

P7

Bit 7: Input Filer Status.

P8

Bit 8: Input Filer Status.

P9

Bit 9: Input Filer Status.

P10

Bit 10: Input Filer Status.

P11

Bit 11: Input Filer Status.

P12

Bit 12: Input Filer Status.

P13

Bit 13: Input Filer Status.

P14

Bit 14: Input Filer Status.

P15

Bit 15: Input Filer Status.

P16

Bit 16: Input Filer Status.

P17

Bit 17: Input Filer Status.

P18

Bit 18: Input Filer Status.

P19

Bit 19: Input Filer Status.

P20

Bit 20: Input Filer Status.

P21

Bit 21: Input Filer Status.

P22

Bit 22: Input Filer Status.

P23

Bit 23: Input Filer Status.

P24

Bit 24: Input Filer Status.

P25

Bit 25: Input Filer Status.

P26

Bit 26: Input Filer Status.

P27

Bit 27: Input Filer Status.

P28

Bit 28: Input Filer Status.

P29

Bit 29: Input Filer Status.

P30

Bit 30: Input Filer Status.

P31

Bit 31: Input Filer Status.

SODR

Set Output Data Register

Offset: 0x30, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Set Output Data.

P1

Bit 1: Set Output Data.

P2

Bit 2: Set Output Data.

P3

Bit 3: Set Output Data.

P4

Bit 4: Set Output Data.

P5

Bit 5: Set Output Data.

P6

Bit 6: Set Output Data.

P7

Bit 7: Set Output Data.

P8

Bit 8: Set Output Data.

P9

Bit 9: Set Output Data.

P10

Bit 10: Set Output Data.

P11

Bit 11: Set Output Data.

P12

Bit 12: Set Output Data.

P13

Bit 13: Set Output Data.

P14

Bit 14: Set Output Data.

P15

Bit 15: Set Output Data.

P16

Bit 16: Set Output Data.

P17

Bit 17: Set Output Data.

P18

Bit 18: Set Output Data.

P19

Bit 19: Set Output Data.

P20

Bit 20: Set Output Data.

P21

Bit 21: Set Output Data.

P22

Bit 22: Set Output Data.

P23

Bit 23: Set Output Data.

P24

Bit 24: Set Output Data.

P25

Bit 25: Set Output Data.

P26

Bit 26: Set Output Data.

P27

Bit 27: Set Output Data.

P28

Bit 28: Set Output Data.

P29

Bit 29: Set Output Data.

P30

Bit 30: Set Output Data.

P31

Bit 31: Set Output Data.

CODR

Clear Output Data Register

Offset: 0x34, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Clear Output Data.

P1

Bit 1: Clear Output Data.

P2

Bit 2: Clear Output Data.

P3

Bit 3: Clear Output Data.

P4

Bit 4: Clear Output Data.

P5

Bit 5: Clear Output Data.

P6

Bit 6: Clear Output Data.

P7

Bit 7: Clear Output Data.

P8

Bit 8: Clear Output Data.

P9

Bit 9: Clear Output Data.

P10

Bit 10: Clear Output Data.

P11

Bit 11: Clear Output Data.

P12

Bit 12: Clear Output Data.

P13

Bit 13: Clear Output Data.

P14

Bit 14: Clear Output Data.

P15

Bit 15: Clear Output Data.

P16

Bit 16: Clear Output Data.

P17

Bit 17: Clear Output Data.

P18

Bit 18: Clear Output Data.

P19

Bit 19: Clear Output Data.

P20

Bit 20: Clear Output Data.

P21

Bit 21: Clear Output Data.

P22

Bit 22: Clear Output Data.

P23

Bit 23: Clear Output Data.

P24

Bit 24: Clear Output Data.

P25

Bit 25: Clear Output Data.

P26

Bit 26: Clear Output Data.

P27

Bit 27: Clear Output Data.

P28

Bit 28: Clear Output Data.

P29

Bit 29: Clear Output Data.

P30

Bit 30: Clear Output Data.

P31

Bit 31: Clear Output Data.

ODSR

Output Data Status Register

Offset: 0x38, reset: None, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

PDSR

Pin Data Status Register

Offset: 0x3c, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

IER

Interrupt Enable Register

Offset: 0x40, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Enable.

P1

Bit 1: Input Change Interrupt Enable.

P2

Bit 2: Input Change Interrupt Enable.

P3

Bit 3: Input Change Interrupt Enable.

P4

Bit 4: Input Change Interrupt Enable.

P5

Bit 5: Input Change Interrupt Enable.

P6

Bit 6: Input Change Interrupt Enable.

P7

Bit 7: Input Change Interrupt Enable.

P8

Bit 8: Input Change Interrupt Enable.

P9

Bit 9: Input Change Interrupt Enable.

P10

Bit 10: Input Change Interrupt Enable.

P11

Bit 11: Input Change Interrupt Enable.

P12

Bit 12: Input Change Interrupt Enable.

P13

Bit 13: Input Change Interrupt Enable.

P14

Bit 14: Input Change Interrupt Enable.

P15

Bit 15: Input Change Interrupt Enable.

P16

Bit 16: Input Change Interrupt Enable.

P17

Bit 17: Input Change Interrupt Enable.

P18

Bit 18: Input Change Interrupt Enable.

P19

Bit 19: Input Change Interrupt Enable.

P20

Bit 20: Input Change Interrupt Enable.

P21

Bit 21: Input Change Interrupt Enable.

P22

Bit 22: Input Change Interrupt Enable.

P23

Bit 23: Input Change Interrupt Enable.

P24

Bit 24: Input Change Interrupt Enable.

P25

Bit 25: Input Change Interrupt Enable.

P26

Bit 26: Input Change Interrupt Enable.

P27

Bit 27: Input Change Interrupt Enable.

P28

Bit 28: Input Change Interrupt Enable.

P29

Bit 29: Input Change Interrupt Enable.

P30

Bit 30: Input Change Interrupt Enable.

P31

Bit 31: Input Change Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x44, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Disable.

P1

Bit 1: Input Change Interrupt Disable.

P2

Bit 2: Input Change Interrupt Disable.

P3

Bit 3: Input Change Interrupt Disable.

P4

Bit 4: Input Change Interrupt Disable.

P5

Bit 5: Input Change Interrupt Disable.

P6

Bit 6: Input Change Interrupt Disable.

P7

Bit 7: Input Change Interrupt Disable.

P8

Bit 8: Input Change Interrupt Disable.

P9

Bit 9: Input Change Interrupt Disable.

P10

Bit 10: Input Change Interrupt Disable.

P11

Bit 11: Input Change Interrupt Disable.

P12

Bit 12: Input Change Interrupt Disable.

P13

Bit 13: Input Change Interrupt Disable.

P14

Bit 14: Input Change Interrupt Disable.

P15

Bit 15: Input Change Interrupt Disable.

P16

Bit 16: Input Change Interrupt Disable.

P17

Bit 17: Input Change Interrupt Disable.

P18

Bit 18: Input Change Interrupt Disable.

P19

Bit 19: Input Change Interrupt Disable.

P20

Bit 20: Input Change Interrupt Disable.

P21

Bit 21: Input Change Interrupt Disable.

P22

Bit 22: Input Change Interrupt Disable.

P23

Bit 23: Input Change Interrupt Disable.

P24

Bit 24: Input Change Interrupt Disable.

P25

Bit 25: Input Change Interrupt Disable.

P26

Bit 26: Input Change Interrupt Disable.

P27

Bit 27: Input Change Interrupt Disable.

P28

Bit 28: Input Change Interrupt Disable.

P29

Bit 29: Input Change Interrupt Disable.

P30

Bit 30: Input Change Interrupt Disable.

P31

Bit 31: Input Change Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x48, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Mask.

P1

Bit 1: Input Change Interrupt Mask.

P2

Bit 2: Input Change Interrupt Mask.

P3

Bit 3: Input Change Interrupt Mask.

P4

Bit 4: Input Change Interrupt Mask.

P5

Bit 5: Input Change Interrupt Mask.

P6

Bit 6: Input Change Interrupt Mask.

P7

Bit 7: Input Change Interrupt Mask.

P8

Bit 8: Input Change Interrupt Mask.

P9

Bit 9: Input Change Interrupt Mask.

P10

Bit 10: Input Change Interrupt Mask.

P11

Bit 11: Input Change Interrupt Mask.

P12

Bit 12: Input Change Interrupt Mask.

P13

Bit 13: Input Change Interrupt Mask.

P14

Bit 14: Input Change Interrupt Mask.

P15

Bit 15: Input Change Interrupt Mask.

P16

Bit 16: Input Change Interrupt Mask.

P17

Bit 17: Input Change Interrupt Mask.

P18

Bit 18: Input Change Interrupt Mask.

P19

Bit 19: Input Change Interrupt Mask.

P20

Bit 20: Input Change Interrupt Mask.

P21

Bit 21: Input Change Interrupt Mask.

P22

Bit 22: Input Change Interrupt Mask.

P23

Bit 23: Input Change Interrupt Mask.

P24

Bit 24: Input Change Interrupt Mask.

P25

Bit 25: Input Change Interrupt Mask.

P26

Bit 26: Input Change Interrupt Mask.

P27

Bit 27: Input Change Interrupt Mask.

P28

Bit 28: Input Change Interrupt Mask.

P29

Bit 29: Input Change Interrupt Mask.

P30

Bit 30: Input Change Interrupt Mask.

P31

Bit 31: Input Change Interrupt Mask.

ISR

Interrupt Status Register

Offset: 0x4c, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Status.

P1

Bit 1: Input Change Interrupt Status.

P2

Bit 2: Input Change Interrupt Status.

P3

Bit 3: Input Change Interrupt Status.

P4

Bit 4: Input Change Interrupt Status.

P5

Bit 5: Input Change Interrupt Status.

P6

Bit 6: Input Change Interrupt Status.

P7

Bit 7: Input Change Interrupt Status.

P8

Bit 8: Input Change Interrupt Status.

P9

Bit 9: Input Change Interrupt Status.

P10

Bit 10: Input Change Interrupt Status.

P11

Bit 11: Input Change Interrupt Status.

P12

Bit 12: Input Change Interrupt Status.

P13

Bit 13: Input Change Interrupt Status.

P14

Bit 14: Input Change Interrupt Status.

P15

Bit 15: Input Change Interrupt Status.

P16

Bit 16: Input Change Interrupt Status.

P17

Bit 17: Input Change Interrupt Status.

P18

Bit 18: Input Change Interrupt Status.

P19

Bit 19: Input Change Interrupt Status.

P20

Bit 20: Input Change Interrupt Status.

P21

Bit 21: Input Change Interrupt Status.

P22

Bit 22: Input Change Interrupt Status.

P23

Bit 23: Input Change Interrupt Status.

P24

Bit 24: Input Change Interrupt Status.

P25

Bit 25: Input Change Interrupt Status.

P26

Bit 26: Input Change Interrupt Status.

P27

Bit 27: Input Change Interrupt Status.

P28

Bit 28: Input Change Interrupt Status.

P29

Bit 29: Input Change Interrupt Status.

P30

Bit 30: Input Change Interrupt Status.

P31

Bit 31: Input Change Interrupt Status.

MDER

Multi-driver Enable Register

Offset: 0x50, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Enable..

P1

Bit 1: Multi Drive Enable..

P2

Bit 2: Multi Drive Enable..

P3

Bit 3: Multi Drive Enable..

P4

Bit 4: Multi Drive Enable..

P5

Bit 5: Multi Drive Enable..

P6

Bit 6: Multi Drive Enable..

P7

Bit 7: Multi Drive Enable..

P8

Bit 8: Multi Drive Enable..

P9

Bit 9: Multi Drive Enable..

P10

Bit 10: Multi Drive Enable..

P11

Bit 11: Multi Drive Enable..

P12

Bit 12: Multi Drive Enable..

P13

Bit 13: Multi Drive Enable..

P14

Bit 14: Multi Drive Enable..

P15

Bit 15: Multi Drive Enable..

P16

Bit 16: Multi Drive Enable..

P17

Bit 17: Multi Drive Enable..

P18

Bit 18: Multi Drive Enable..

P19

Bit 19: Multi Drive Enable..

P20

Bit 20: Multi Drive Enable..

P21

Bit 21: Multi Drive Enable..

P22

Bit 22: Multi Drive Enable..

P23

Bit 23: Multi Drive Enable..

P24

Bit 24: Multi Drive Enable..

P25

Bit 25: Multi Drive Enable..

P26

Bit 26: Multi Drive Enable..

P27

Bit 27: Multi Drive Enable..

P28

Bit 28: Multi Drive Enable..

P29

Bit 29: Multi Drive Enable..

P30

Bit 30: Multi Drive Enable..

P31

Bit 31: Multi Drive Enable..

MDDR

Multi-driver Disable Register

Offset: 0x54, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Disable..

P1

Bit 1: Multi Drive Disable..

P2

Bit 2: Multi Drive Disable..

P3

Bit 3: Multi Drive Disable..

P4

Bit 4: Multi Drive Disable..

P5

Bit 5: Multi Drive Disable..

P6

Bit 6: Multi Drive Disable..

P7

Bit 7: Multi Drive Disable..

P8

Bit 8: Multi Drive Disable..

P9

Bit 9: Multi Drive Disable..

P10

Bit 10: Multi Drive Disable..

P11

Bit 11: Multi Drive Disable..

P12

Bit 12: Multi Drive Disable..

P13

Bit 13: Multi Drive Disable..

P14

Bit 14: Multi Drive Disable..

P15

Bit 15: Multi Drive Disable..

P16

Bit 16: Multi Drive Disable..

P17

Bit 17: Multi Drive Disable..

P18

Bit 18: Multi Drive Disable..

P19

Bit 19: Multi Drive Disable..

P20

Bit 20: Multi Drive Disable..

P21

Bit 21: Multi Drive Disable..

P22

Bit 22: Multi Drive Disable..

P23

Bit 23: Multi Drive Disable..

P24

Bit 24: Multi Drive Disable..

P25

Bit 25: Multi Drive Disable..

P26

Bit 26: Multi Drive Disable..

P27

Bit 27: Multi Drive Disable..

P28

Bit 28: Multi Drive Disable..

P29

Bit 29: Multi Drive Disable..

P30

Bit 30: Multi Drive Disable..

P31

Bit 31: Multi Drive Disable..

MDSR

Multi-driver Status Register

Offset: 0x58, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Multi Drive Status..

P1

Bit 1: Multi Drive Status..

P2

Bit 2: Multi Drive Status..

P3

Bit 3: Multi Drive Status..

P4

Bit 4: Multi Drive Status..

P5

Bit 5: Multi Drive Status..

P6

Bit 6: Multi Drive Status..

P7

Bit 7: Multi Drive Status..

P8

Bit 8: Multi Drive Status..

P9

Bit 9: Multi Drive Status..

P10

Bit 10: Multi Drive Status..

P11

Bit 11: Multi Drive Status..

P12

Bit 12: Multi Drive Status..

P13

Bit 13: Multi Drive Status..

P14

Bit 14: Multi Drive Status..

P15

Bit 15: Multi Drive Status..

P16

Bit 16: Multi Drive Status..

P17

Bit 17: Multi Drive Status..

P18

Bit 18: Multi Drive Status..

P19

Bit 19: Multi Drive Status..

P20

Bit 20: Multi Drive Status..

P21

Bit 21: Multi Drive Status..

P22

Bit 22: Multi Drive Status..

P23

Bit 23: Multi Drive Status..

P24

Bit 24: Multi Drive Status..

P25

Bit 25: Multi Drive Status..

P26

Bit 26: Multi Drive Status..

P27

Bit 27: Multi Drive Status..

P28

Bit 28: Multi Drive Status..

P29

Bit 29: Multi Drive Status..

P30

Bit 30: Multi Drive Status..

P31

Bit 31: Multi Drive Status..

PUDR

Pull-up Disable Register

Offset: 0x60, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Disable..

P1

Bit 1: Pull Up Disable..

P2

Bit 2: Pull Up Disable..

P3

Bit 3: Pull Up Disable..

P4

Bit 4: Pull Up Disable..

P5

Bit 5: Pull Up Disable..

P6

Bit 6: Pull Up Disable..

P7

Bit 7: Pull Up Disable..

P8

Bit 8: Pull Up Disable..

P9

Bit 9: Pull Up Disable..

P10

Bit 10: Pull Up Disable..

P11

Bit 11: Pull Up Disable..

P12

Bit 12: Pull Up Disable..

P13

Bit 13: Pull Up Disable..

P14

Bit 14: Pull Up Disable..

P15

Bit 15: Pull Up Disable..

P16

Bit 16: Pull Up Disable..

P17

Bit 17: Pull Up Disable..

P18

Bit 18: Pull Up Disable..

P19

Bit 19: Pull Up Disable..

P20

Bit 20: Pull Up Disable..

P21

Bit 21: Pull Up Disable..

P22

Bit 22: Pull Up Disable..

P23

Bit 23: Pull Up Disable..

P24

Bit 24: Pull Up Disable..

P25

Bit 25: Pull Up Disable..

P26

Bit 26: Pull Up Disable..

P27

Bit 27: Pull Up Disable..

P28

Bit 28: Pull Up Disable..

P29

Bit 29: Pull Up Disable..

P30

Bit 30: Pull Up Disable..

P31

Bit 31: Pull Up Disable..

PUER

Pull-up Enable Register

Offset: 0x64, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Enable..

P1

Bit 1: Pull Up Enable..

P2

Bit 2: Pull Up Enable..

P3

Bit 3: Pull Up Enable..

P4

Bit 4: Pull Up Enable..

P5

Bit 5: Pull Up Enable..

P6

Bit 6: Pull Up Enable..

P7

Bit 7: Pull Up Enable..

P8

Bit 8: Pull Up Enable..

P9

Bit 9: Pull Up Enable..

P10

Bit 10: Pull Up Enable..

P11

Bit 11: Pull Up Enable..

P12

Bit 12: Pull Up Enable..

P13

Bit 13: Pull Up Enable..

P14

Bit 14: Pull Up Enable..

P15

Bit 15: Pull Up Enable..

P16

Bit 16: Pull Up Enable..

P17

Bit 17: Pull Up Enable..

P18

Bit 18: Pull Up Enable..

P19

Bit 19: Pull Up Enable..

P20

Bit 20: Pull Up Enable..

P21

Bit 21: Pull Up Enable..

P22

Bit 22: Pull Up Enable..

P23

Bit 23: Pull Up Enable..

P24

Bit 24: Pull Up Enable..

P25

Bit 25: Pull Up Enable..

P26

Bit 26: Pull Up Enable..

P27

Bit 27: Pull Up Enable..

P28

Bit 28: Pull Up Enable..

P29

Bit 29: Pull Up Enable..

P30

Bit 30: Pull Up Enable..

P31

Bit 31: Pull Up Enable..

PUSR

Pad Pull-up Status Register

Offset: 0x68, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Pull Up Status..

P1

Bit 1: Pull Up Status..

P2

Bit 2: Pull Up Status..

P3

Bit 3: Pull Up Status..

P4

Bit 4: Pull Up Status..

P5

Bit 5: Pull Up Status..

P6

Bit 6: Pull Up Status..

P7

Bit 7: Pull Up Status..

P8

Bit 8: Pull Up Status..

P9

Bit 9: Pull Up Status..

P10

Bit 10: Pull Up Status..

P11

Bit 11: Pull Up Status..

P12

Bit 12: Pull Up Status..

P13

Bit 13: Pull Up Status..

P14

Bit 14: Pull Up Status..

P15

Bit 15: Pull Up Status..

P16

Bit 16: Pull Up Status..

P17

Bit 17: Pull Up Status..

P18

Bit 18: Pull Up Status..

P19

Bit 19: Pull Up Status..

P20

Bit 20: Pull Up Status..

P21

Bit 21: Pull Up Status..

P22

Bit 22: Pull Up Status..

P23

Bit 23: Pull Up Status..

P24

Bit 24: Pull Up Status..

P25

Bit 25: Pull Up Status..

P26

Bit 26: Pull Up Status..

P27

Bit 27: Pull Up Status..

P28

Bit 28: Pull Up Status..

P29

Bit 29: Pull Up Status..

P30

Bit 30: Pull Up Status..

P31

Bit 31: Pull Up Status..

ABSR

Peripheral AB Select Register

Offset: 0x70, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Peripheral A Select..

P1

Bit 1: Peripheral A Select..

P2

Bit 2: Peripheral A Select..

P3

Bit 3: Peripheral A Select..

P4

Bit 4: Peripheral A Select..

P5

Bit 5: Peripheral A Select..

P6

Bit 6: Peripheral A Select..

P7

Bit 7: Peripheral A Select..

P8

Bit 8: Peripheral A Select..

P9

Bit 9: Peripheral A Select..

P10

Bit 10: Peripheral A Select..

P11

Bit 11: Peripheral A Select..

P12

Bit 12: Peripheral A Select..

P13

Bit 13: Peripheral A Select..

P14

Bit 14: Peripheral A Select..

P15

Bit 15: Peripheral A Select..

P16

Bit 16: Peripheral A Select..

P17

Bit 17: Peripheral A Select..

P18

Bit 18: Peripheral A Select..

P19

Bit 19: Peripheral A Select..

P20

Bit 20: Peripheral A Select..

P21

Bit 21: Peripheral A Select..

P22

Bit 22: Peripheral A Select..

P23

Bit 23: Peripheral A Select..

P24

Bit 24: Peripheral A Select..

P25

Bit 25: Peripheral A Select..

P26

Bit 26: Peripheral A Select..

P27

Bit 27: Peripheral A Select..

P28

Bit 28: Peripheral A Select..

P29

Bit 29: Peripheral A Select..

P30

Bit 30: Peripheral A Select..

P31

Bit 31: Peripheral A Select..

SCIFSR

System Clock Glitch Input Filter Select Register

Offset: 0x80, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: System Clock Glitch Filtering Select..

P1

Bit 1: System Clock Glitch Filtering Select..

P2

Bit 2: System Clock Glitch Filtering Select..

P3

Bit 3: System Clock Glitch Filtering Select..

P4

Bit 4: System Clock Glitch Filtering Select..

P5

Bit 5: System Clock Glitch Filtering Select..

P6

Bit 6: System Clock Glitch Filtering Select..

P7

Bit 7: System Clock Glitch Filtering Select..

P8

Bit 8: System Clock Glitch Filtering Select..

P9

Bit 9: System Clock Glitch Filtering Select..

P10

Bit 10: System Clock Glitch Filtering Select..

P11

Bit 11: System Clock Glitch Filtering Select..

P12

Bit 12: System Clock Glitch Filtering Select..

P13

Bit 13: System Clock Glitch Filtering Select..

P14

Bit 14: System Clock Glitch Filtering Select..

P15

Bit 15: System Clock Glitch Filtering Select..

P16

Bit 16: System Clock Glitch Filtering Select..

P17

Bit 17: System Clock Glitch Filtering Select..

P18

Bit 18: System Clock Glitch Filtering Select..

P19

Bit 19: System Clock Glitch Filtering Select..

P20

Bit 20: System Clock Glitch Filtering Select..

P21

Bit 21: System Clock Glitch Filtering Select..

P22

Bit 22: System Clock Glitch Filtering Select..

P23

Bit 23: System Clock Glitch Filtering Select..

P24

Bit 24: System Clock Glitch Filtering Select..

P25

Bit 25: System Clock Glitch Filtering Select..

P26

Bit 26: System Clock Glitch Filtering Select..

P27

Bit 27: System Clock Glitch Filtering Select..

P28

Bit 28: System Clock Glitch Filtering Select..

P29

Bit 29: System Clock Glitch Filtering Select..

P30

Bit 30: System Clock Glitch Filtering Select..

P31

Bit 31: System Clock Glitch Filtering Select..

DIFSR

Debouncing Input Filter Select Register

Offset: 0x84, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Debouncing Filtering Select..

P1

Bit 1: Debouncing Filtering Select..

P2

Bit 2: Debouncing Filtering Select..

P3

Bit 3: Debouncing Filtering Select..

P4

Bit 4: Debouncing Filtering Select..

P5

Bit 5: Debouncing Filtering Select..

P6

Bit 6: Debouncing Filtering Select..

P7

Bit 7: Debouncing Filtering Select..

P8

Bit 8: Debouncing Filtering Select..

P9

Bit 9: Debouncing Filtering Select..

P10

Bit 10: Debouncing Filtering Select..

P11

Bit 11: Debouncing Filtering Select..

P12

Bit 12: Debouncing Filtering Select..

P13

Bit 13: Debouncing Filtering Select..

P14

Bit 14: Debouncing Filtering Select..

P15

Bit 15: Debouncing Filtering Select..

P16

Bit 16: Debouncing Filtering Select..

P17

Bit 17: Debouncing Filtering Select..

P18

Bit 18: Debouncing Filtering Select..

P19

Bit 19: Debouncing Filtering Select..

P20

Bit 20: Debouncing Filtering Select..

P21

Bit 21: Debouncing Filtering Select..

P22

Bit 22: Debouncing Filtering Select..

P23

Bit 23: Debouncing Filtering Select..

P24

Bit 24: Debouncing Filtering Select..

P25

Bit 25: Debouncing Filtering Select..

P26

Bit 26: Debouncing Filtering Select..

P27

Bit 27: Debouncing Filtering Select..

P28

Bit 28: Debouncing Filtering Select..

P29

Bit 29: Debouncing Filtering Select..

P30

Bit 30: Debouncing Filtering Select..

P31

Bit 31: Debouncing Filtering Select..

IFDGSR

Glitch or Debouncing Input Filter Clock Selection Status Register

Offset: 0x88, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Glitch or Debouncing Filter Selection Status.

P1

Bit 1: Glitch or Debouncing Filter Selection Status.

P2

Bit 2: Glitch or Debouncing Filter Selection Status.

P3

Bit 3: Glitch or Debouncing Filter Selection Status.

P4

Bit 4: Glitch or Debouncing Filter Selection Status.

P5

Bit 5: Glitch or Debouncing Filter Selection Status.

P6

Bit 6: Glitch or Debouncing Filter Selection Status.

P7

Bit 7: Glitch or Debouncing Filter Selection Status.

P8

Bit 8: Glitch or Debouncing Filter Selection Status.

P9

Bit 9: Glitch or Debouncing Filter Selection Status.

P10

Bit 10: Glitch or Debouncing Filter Selection Status.

P11

Bit 11: Glitch or Debouncing Filter Selection Status.

P12

Bit 12: Glitch or Debouncing Filter Selection Status.

P13

Bit 13: Glitch or Debouncing Filter Selection Status.

P14

Bit 14: Glitch or Debouncing Filter Selection Status.

P15

Bit 15: Glitch or Debouncing Filter Selection Status.

P16

Bit 16: Glitch or Debouncing Filter Selection Status.

P17

Bit 17: Glitch or Debouncing Filter Selection Status.

P18

Bit 18: Glitch or Debouncing Filter Selection Status.

P19

Bit 19: Glitch or Debouncing Filter Selection Status.

P20

Bit 20: Glitch or Debouncing Filter Selection Status.

P21

Bit 21: Glitch or Debouncing Filter Selection Status.

P22

Bit 22: Glitch or Debouncing Filter Selection Status.

P23

Bit 23: Glitch or Debouncing Filter Selection Status.

P24

Bit 24: Glitch or Debouncing Filter Selection Status.

P25

Bit 25: Glitch or Debouncing Filter Selection Status.

P26

Bit 26: Glitch or Debouncing Filter Selection Status.

P27

Bit 27: Glitch or Debouncing Filter Selection Status.

P28

Bit 28: Glitch or Debouncing Filter Selection Status.

P29

Bit 29: Glitch or Debouncing Filter Selection Status.

P30

Bit 30: Glitch or Debouncing Filter Selection Status.

P31

Bit 31: Glitch or Debouncing Filter Selection Status.

SCDR

Slow Clock Divider Debouncing Register

Offset: 0x8c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-13: Slow Clock Divider Selection for Debouncing.

OWER

Output Write Enable

Offset: 0xa0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Enable..

P1

Bit 1: Output Write Enable..

P2

Bit 2: Output Write Enable..

P3

Bit 3: Output Write Enable..

P4

Bit 4: Output Write Enable..

P5

Bit 5: Output Write Enable..

P6

Bit 6: Output Write Enable..

P7

Bit 7: Output Write Enable..

P8

Bit 8: Output Write Enable..

P9

Bit 9: Output Write Enable..

P10

Bit 10: Output Write Enable..

P11

Bit 11: Output Write Enable..

P12

Bit 12: Output Write Enable..

P13

Bit 13: Output Write Enable..

P14

Bit 14: Output Write Enable..

P15

Bit 15: Output Write Enable..

P16

Bit 16: Output Write Enable..

P17

Bit 17: Output Write Enable..

P18

Bit 18: Output Write Enable..

P19

Bit 19: Output Write Enable..

P20

Bit 20: Output Write Enable..

P21

Bit 21: Output Write Enable..

P22

Bit 22: Output Write Enable..

P23

Bit 23: Output Write Enable..

P24

Bit 24: Output Write Enable..

P25

Bit 25: Output Write Enable..

P26

Bit 26: Output Write Enable..

P27

Bit 27: Output Write Enable..

P28

Bit 28: Output Write Enable..

P29

Bit 29: Output Write Enable..

P30

Bit 30: Output Write Enable..

P31

Bit 31: Output Write Enable..

OWDR

Output Write Disable

Offset: 0xa4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Disable..

P1

Bit 1: Output Write Disable..

P2

Bit 2: Output Write Disable..

P3

Bit 3: Output Write Disable..

P4

Bit 4: Output Write Disable..

P5

Bit 5: Output Write Disable..

P6

Bit 6: Output Write Disable..

P7

Bit 7: Output Write Disable..

P8

Bit 8: Output Write Disable..

P9

Bit 9: Output Write Disable..

P10

Bit 10: Output Write Disable..

P11

Bit 11: Output Write Disable..

P12

Bit 12: Output Write Disable..

P13

Bit 13: Output Write Disable..

P14

Bit 14: Output Write Disable..

P15

Bit 15: Output Write Disable..

P16

Bit 16: Output Write Disable..

P17

Bit 17: Output Write Disable..

P18

Bit 18: Output Write Disable..

P19

Bit 19: Output Write Disable..

P20

Bit 20: Output Write Disable..

P21

Bit 21: Output Write Disable..

P22

Bit 22: Output Write Disable..

P23

Bit 23: Output Write Disable..

P24

Bit 24: Output Write Disable..

P25

Bit 25: Output Write Disable..

P26

Bit 26: Output Write Disable..

P27

Bit 27: Output Write Disable..

P28

Bit 28: Output Write Disable..

P29

Bit 29: Output Write Disable..

P30

Bit 30: Output Write Disable..

P31

Bit 31: Output Write Disable..

OWSR

Output Write Status Register

Offset: 0xa8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Write Status..

P1

Bit 1: Output Write Status..

P2

Bit 2: Output Write Status..

P3

Bit 3: Output Write Status..

P4

Bit 4: Output Write Status..

P5

Bit 5: Output Write Status..

P6

Bit 6: Output Write Status..

P7

Bit 7: Output Write Status..

P8

Bit 8: Output Write Status..

P9

Bit 9: Output Write Status..

P10

Bit 10: Output Write Status..

P11

Bit 11: Output Write Status..

P12

Bit 12: Output Write Status..

P13

Bit 13: Output Write Status..

P14

Bit 14: Output Write Status..

P15

Bit 15: Output Write Status..

P16

Bit 16: Output Write Status..

P17

Bit 17: Output Write Status..

P18

Bit 18: Output Write Status..

P19

Bit 19: Output Write Status..

P20

Bit 20: Output Write Status..

P21

Bit 21: Output Write Status..

P22

Bit 22: Output Write Status..

P23

Bit 23: Output Write Status..

P24

Bit 24: Output Write Status..

P25

Bit 25: Output Write Status..

P26

Bit 26: Output Write Status..

P27

Bit 27: Output Write Status..

P28

Bit 28: Output Write Status..

P29

Bit 29: Output Write Status..

P30

Bit 30: Output Write Status..

P31

Bit 31: Output Write Status..

AIMER

Additional Interrupt Modes Enable Register

Offset: 0xb0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Enable..

P1

Bit 1: Additional Interrupt Modes Enable..

P2

Bit 2: Additional Interrupt Modes Enable..

P3

Bit 3: Additional Interrupt Modes Enable..

P4

Bit 4: Additional Interrupt Modes Enable..

P5

Bit 5: Additional Interrupt Modes Enable..

P6

Bit 6: Additional Interrupt Modes Enable..

P7

Bit 7: Additional Interrupt Modes Enable..

P8

Bit 8: Additional Interrupt Modes Enable..

P9

Bit 9: Additional Interrupt Modes Enable..

P10

Bit 10: Additional Interrupt Modes Enable..

P11

Bit 11: Additional Interrupt Modes Enable..

P12

Bit 12: Additional Interrupt Modes Enable..

P13

Bit 13: Additional Interrupt Modes Enable..

P14

Bit 14: Additional Interrupt Modes Enable..

P15

Bit 15: Additional Interrupt Modes Enable..

P16

Bit 16: Additional Interrupt Modes Enable..

P17

Bit 17: Additional Interrupt Modes Enable..

P18

Bit 18: Additional Interrupt Modes Enable..

P19

Bit 19: Additional Interrupt Modes Enable..

P20

Bit 20: Additional Interrupt Modes Enable..

P21

Bit 21: Additional Interrupt Modes Enable..

P22

Bit 22: Additional Interrupt Modes Enable..

P23

Bit 23: Additional Interrupt Modes Enable..

P24

Bit 24: Additional Interrupt Modes Enable..

P25

Bit 25: Additional Interrupt Modes Enable..

P26

Bit 26: Additional Interrupt Modes Enable..

P27

Bit 27: Additional Interrupt Modes Enable..

P28

Bit 28: Additional Interrupt Modes Enable..

P29

Bit 29: Additional Interrupt Modes Enable..

P30

Bit 30: Additional Interrupt Modes Enable..

P31

Bit 31: Additional Interrupt Modes Enable..

AIMDR

Additional Interrupt Modes Disables Register

Offset: 0xb4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Disable..

P1

Bit 1: Additional Interrupt Modes Disable..

P2

Bit 2: Additional Interrupt Modes Disable..

P3

Bit 3: Additional Interrupt Modes Disable..

P4

Bit 4: Additional Interrupt Modes Disable..

P5

Bit 5: Additional Interrupt Modes Disable..

P6

Bit 6: Additional Interrupt Modes Disable..

P7

Bit 7: Additional Interrupt Modes Disable..

P8

Bit 8: Additional Interrupt Modes Disable..

P9

Bit 9: Additional Interrupt Modes Disable..

P10

Bit 10: Additional Interrupt Modes Disable..

P11

Bit 11: Additional Interrupt Modes Disable..

P12

Bit 12: Additional Interrupt Modes Disable..

P13

Bit 13: Additional Interrupt Modes Disable..

P14

Bit 14: Additional Interrupt Modes Disable..

P15

Bit 15: Additional Interrupt Modes Disable..

P16

Bit 16: Additional Interrupt Modes Disable..

P17

Bit 17: Additional Interrupt Modes Disable..

P18

Bit 18: Additional Interrupt Modes Disable..

P19

Bit 19: Additional Interrupt Modes Disable..

P20

Bit 20: Additional Interrupt Modes Disable..

P21

Bit 21: Additional Interrupt Modes Disable..

P22

Bit 22: Additional Interrupt Modes Disable..

P23

Bit 23: Additional Interrupt Modes Disable..

P24

Bit 24: Additional Interrupt Modes Disable..

P25

Bit 25: Additional Interrupt Modes Disable..

P26

Bit 26: Additional Interrupt Modes Disable..

P27

Bit 27: Additional Interrupt Modes Disable..

P28

Bit 28: Additional Interrupt Modes Disable..

P29

Bit 29: Additional Interrupt Modes Disable..

P30

Bit 30: Additional Interrupt Modes Disable..

P31

Bit 31: Additional Interrupt Modes Disable..

AIMMR

Additional Interrupt Modes Mask Register

Offset: 0xb8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Peripheral CD Status..

P1

Bit 1: Peripheral CD Status..

P2

Bit 2: Peripheral CD Status..

P3

Bit 3: Peripheral CD Status..

P4

Bit 4: Peripheral CD Status..

P5

Bit 5: Peripheral CD Status..

P6

Bit 6: Peripheral CD Status..

P7

Bit 7: Peripheral CD Status..

P8

Bit 8: Peripheral CD Status..

P9

Bit 9: Peripheral CD Status..

P10

Bit 10: Peripheral CD Status..

P11

Bit 11: Peripheral CD Status..

P12

Bit 12: Peripheral CD Status..

P13

Bit 13: Peripheral CD Status..

P14

Bit 14: Peripheral CD Status..

P15

Bit 15: Peripheral CD Status..

P16

Bit 16: Peripheral CD Status..

P17

Bit 17: Peripheral CD Status..

P18

Bit 18: Peripheral CD Status..

P19

Bit 19: Peripheral CD Status..

P20

Bit 20: Peripheral CD Status..

P21

Bit 21: Peripheral CD Status..

P22

Bit 22: Peripheral CD Status..

P23

Bit 23: Peripheral CD Status..

P24

Bit 24: Peripheral CD Status..

P25

Bit 25: Peripheral CD Status..

P26

Bit 26: Peripheral CD Status..

P27

Bit 27: Peripheral CD Status..

P28

Bit 28: Peripheral CD Status..

P29

Bit 29: Peripheral CD Status..

P30

Bit 30: Peripheral CD Status..

P31

Bit 31: Peripheral CD Status..

ESR

Edge Select Register

Offset: 0xc0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Edge Interrupt Selection..

P1

Bit 1: Edge Interrupt Selection..

P2

Bit 2: Edge Interrupt Selection..

P3

Bit 3: Edge Interrupt Selection..

P4

Bit 4: Edge Interrupt Selection..

P5

Bit 5: Edge Interrupt Selection..

P6

Bit 6: Edge Interrupt Selection..

P7

Bit 7: Edge Interrupt Selection..

P8

Bit 8: Edge Interrupt Selection..

P9

Bit 9: Edge Interrupt Selection..

P10

Bit 10: Edge Interrupt Selection..

P11

Bit 11: Edge Interrupt Selection..

P12

Bit 12: Edge Interrupt Selection..

P13

Bit 13: Edge Interrupt Selection..

P14

Bit 14: Edge Interrupt Selection..

P15

Bit 15: Edge Interrupt Selection..

P16

Bit 16: Edge Interrupt Selection..

P17

Bit 17: Edge Interrupt Selection..

P18

Bit 18: Edge Interrupt Selection..

P19

Bit 19: Edge Interrupt Selection..

P20

Bit 20: Edge Interrupt Selection..

P21

Bit 21: Edge Interrupt Selection..

P22

Bit 22: Edge Interrupt Selection..

P23

Bit 23: Edge Interrupt Selection..

P24

Bit 24: Edge Interrupt Selection..

P25

Bit 25: Edge Interrupt Selection..

P26

Bit 26: Edge Interrupt Selection..

P27

Bit 27: Edge Interrupt Selection..

P28

Bit 28: Edge Interrupt Selection..

P29

Bit 29: Edge Interrupt Selection..

P30

Bit 30: Edge Interrupt Selection..

P31

Bit 31: Edge Interrupt Selection..

LSR

Level Select Register

Offset: 0xc4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Level Interrupt Selection..

P1

Bit 1: Level Interrupt Selection..

P2

Bit 2: Level Interrupt Selection..

P3

Bit 3: Level Interrupt Selection..

P4

Bit 4: Level Interrupt Selection..

P5

Bit 5: Level Interrupt Selection..

P6

Bit 6: Level Interrupt Selection..

P7

Bit 7: Level Interrupt Selection..

P8

Bit 8: Level Interrupt Selection..

P9

Bit 9: Level Interrupt Selection..

P10

Bit 10: Level Interrupt Selection..

P11

Bit 11: Level Interrupt Selection..

P12

Bit 12: Level Interrupt Selection..

P13

Bit 13: Level Interrupt Selection..

P14

Bit 14: Level Interrupt Selection..

P15

Bit 15: Level Interrupt Selection..

P16

Bit 16: Level Interrupt Selection..

P17

Bit 17: Level Interrupt Selection..

P18

Bit 18: Level Interrupt Selection..

P19

Bit 19: Level Interrupt Selection..

P20

Bit 20: Level Interrupt Selection..

P21

Bit 21: Level Interrupt Selection..

P22

Bit 22: Level Interrupt Selection..

P23

Bit 23: Level Interrupt Selection..

P24

Bit 24: Level Interrupt Selection..

P25

Bit 25: Level Interrupt Selection..

P26

Bit 26: Level Interrupt Selection..

P27

Bit 27: Level Interrupt Selection..

P28

Bit 28: Level Interrupt Selection..

P29

Bit 29: Level Interrupt Selection..

P30

Bit 30: Level Interrupt Selection..

P31

Bit 31: Level Interrupt Selection..

ELSR

Edge/Level Status Register

Offset: 0xc8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge/Level Interrupt source selection..

P1

Bit 1: Edge/Level Interrupt source selection..

P2

Bit 2: Edge/Level Interrupt source selection..

P3

Bit 3: Edge/Level Interrupt source selection..

P4

Bit 4: Edge/Level Interrupt source selection..

P5

Bit 5: Edge/Level Interrupt source selection..

P6

Bit 6: Edge/Level Interrupt source selection..

P7

Bit 7: Edge/Level Interrupt source selection..

P8

Bit 8: Edge/Level Interrupt source selection..

P9

Bit 9: Edge/Level Interrupt source selection..

P10

Bit 10: Edge/Level Interrupt source selection..

P11

Bit 11: Edge/Level Interrupt source selection..

P12

Bit 12: Edge/Level Interrupt source selection..

P13

Bit 13: Edge/Level Interrupt source selection..

P14

Bit 14: Edge/Level Interrupt source selection..

P15

Bit 15: Edge/Level Interrupt source selection..

P16

Bit 16: Edge/Level Interrupt source selection..

P17

Bit 17: Edge/Level Interrupt source selection..

P18

Bit 18: Edge/Level Interrupt source selection..

P19

Bit 19: Edge/Level Interrupt source selection..

P20

Bit 20: Edge/Level Interrupt source selection..

P21

Bit 21: Edge/Level Interrupt source selection..

P22

Bit 22: Edge/Level Interrupt source selection..

P23

Bit 23: Edge/Level Interrupt source selection..

P24

Bit 24: Edge/Level Interrupt source selection..

P25

Bit 25: Edge/Level Interrupt source selection..

P26

Bit 26: Edge/Level Interrupt source selection..

P27

Bit 27: Edge/Level Interrupt source selection..

P28

Bit 28: Edge/Level Interrupt source selection..

P29

Bit 29: Edge/Level Interrupt source selection..

P30

Bit 30: Edge/Level Interrupt source selection..

P31

Bit 31: Edge/Level Interrupt source selection..

FELLSR

Falling Edge/Low Level Select Register

Offset: 0xd0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Falling Edge/Low Level Interrupt Selection..

P1

Bit 1: Falling Edge/Low Level Interrupt Selection..

P2

Bit 2: Falling Edge/Low Level Interrupt Selection..

P3

Bit 3: Falling Edge/Low Level Interrupt Selection..

P4

Bit 4: Falling Edge/Low Level Interrupt Selection..

P5

Bit 5: Falling Edge/Low Level Interrupt Selection..

P6

Bit 6: Falling Edge/Low Level Interrupt Selection..

P7

Bit 7: Falling Edge/Low Level Interrupt Selection..

P8

Bit 8: Falling Edge/Low Level Interrupt Selection..

P9

Bit 9: Falling Edge/Low Level Interrupt Selection..

P10

Bit 10: Falling Edge/Low Level Interrupt Selection..

P11

Bit 11: Falling Edge/Low Level Interrupt Selection..

P12

Bit 12: Falling Edge/Low Level Interrupt Selection..

P13

Bit 13: Falling Edge/Low Level Interrupt Selection..

P14

Bit 14: Falling Edge/Low Level Interrupt Selection..

P15

Bit 15: Falling Edge/Low Level Interrupt Selection..

P16

Bit 16: Falling Edge/Low Level Interrupt Selection..

P17

Bit 17: Falling Edge/Low Level Interrupt Selection..

P18

Bit 18: Falling Edge/Low Level Interrupt Selection..

P19

Bit 19: Falling Edge/Low Level Interrupt Selection..

P20

Bit 20: Falling Edge/Low Level Interrupt Selection..

P21

Bit 21: Falling Edge/Low Level Interrupt Selection..

P22

Bit 22: Falling Edge/Low Level Interrupt Selection..

P23

Bit 23: Falling Edge/Low Level Interrupt Selection..

P24

Bit 24: Falling Edge/Low Level Interrupt Selection..

P25

Bit 25: Falling Edge/Low Level Interrupt Selection..

P26

Bit 26: Falling Edge/Low Level Interrupt Selection..

P27

Bit 27: Falling Edge/Low Level Interrupt Selection..

P28

Bit 28: Falling Edge/Low Level Interrupt Selection..

P29

Bit 29: Falling Edge/Low Level Interrupt Selection..

P30

Bit 30: Falling Edge/Low Level Interrupt Selection..

P31

Bit 31: Falling Edge/Low Level Interrupt Selection..

REHLSR

Rising Edge/ High Level Select Register

Offset: 0xd4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Rising Edge /High Level Interrupt Selection..

P1

Bit 1: Rising Edge /High Level Interrupt Selection..

P2

Bit 2: Rising Edge /High Level Interrupt Selection..

P3

Bit 3: Rising Edge /High Level Interrupt Selection..

P4

Bit 4: Rising Edge /High Level Interrupt Selection..

P5

Bit 5: Rising Edge /High Level Interrupt Selection..

P6

Bit 6: Rising Edge /High Level Interrupt Selection..

P7

Bit 7: Rising Edge /High Level Interrupt Selection..

P8

Bit 8: Rising Edge /High Level Interrupt Selection..

P9

Bit 9: Rising Edge /High Level Interrupt Selection..

P10

Bit 10: Rising Edge /High Level Interrupt Selection..

P11

Bit 11: Rising Edge /High Level Interrupt Selection..

P12

Bit 12: Rising Edge /High Level Interrupt Selection..

P13

Bit 13: Rising Edge /High Level Interrupt Selection..

P14

Bit 14: Rising Edge /High Level Interrupt Selection..

P15

Bit 15: Rising Edge /High Level Interrupt Selection..

P16

Bit 16: Rising Edge /High Level Interrupt Selection..

P17

Bit 17: Rising Edge /High Level Interrupt Selection..

P18

Bit 18: Rising Edge /High Level Interrupt Selection..

P19

Bit 19: Rising Edge /High Level Interrupt Selection..

P20

Bit 20: Rising Edge /High Level Interrupt Selection..

P21

Bit 21: Rising Edge /High Level Interrupt Selection..

P22

Bit 22: Rising Edge /High Level Interrupt Selection..

P23

Bit 23: Rising Edge /High Level Interrupt Selection..

P24

Bit 24: Rising Edge /High Level Interrupt Selection..

P25

Bit 25: Rising Edge /High Level Interrupt Selection..

P26

Bit 26: Rising Edge /High Level Interrupt Selection..

P27

Bit 27: Rising Edge /High Level Interrupt Selection..

P28

Bit 28: Rising Edge /High Level Interrupt Selection..

P29

Bit 29: Rising Edge /High Level Interrupt Selection..

P30

Bit 30: Rising Edge /High Level Interrupt Selection..

P31

Bit 31: Rising Edge /High Level Interrupt Selection..

FRLHSR

Fall/Rise - Low/High Status Register

Offset: 0xd8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge /Level Interrupt Source Selection..

P1

Bit 1: Edge /Level Interrupt Source Selection..

P2

Bit 2: Edge /Level Interrupt Source Selection..

P3

Bit 3: Edge /Level Interrupt Source Selection..

P4

Bit 4: Edge /Level Interrupt Source Selection..

P5

Bit 5: Edge /Level Interrupt Source Selection..

P6

Bit 6: Edge /Level Interrupt Source Selection..

P7

Bit 7: Edge /Level Interrupt Source Selection..

P8

Bit 8: Edge /Level Interrupt Source Selection..

P9

Bit 9: Edge /Level Interrupt Source Selection..

P10

Bit 10: Edge /Level Interrupt Source Selection..

P11

Bit 11: Edge /Level Interrupt Source Selection..

P12

Bit 12: Edge /Level Interrupt Source Selection..

P13

Bit 13: Edge /Level Interrupt Source Selection..

P14

Bit 14: Edge /Level Interrupt Source Selection..

P15

Bit 15: Edge /Level Interrupt Source Selection..

P16

Bit 16: Edge /Level Interrupt Source Selection..

P17

Bit 17: Edge /Level Interrupt Source Selection..

P18

Bit 18: Edge /Level Interrupt Source Selection..

P19

Bit 19: Edge /Level Interrupt Source Selection..

P20

Bit 20: Edge /Level Interrupt Source Selection..

P21

Bit 21: Edge /Level Interrupt Source Selection..

P22

Bit 22: Edge /Level Interrupt Source Selection..

P23

Bit 23: Edge /Level Interrupt Source Selection..

P24

Bit 24: Edge /Level Interrupt Source Selection..

P25

Bit 25: Edge /Level Interrupt Source Selection..

P26

Bit 26: Edge /Level Interrupt Source Selection..

P27

Bit 27: Edge /Level Interrupt Source Selection..

P28

Bit 28: Edge /Level Interrupt Source Selection..

P29

Bit 29: Edge /Level Interrupt Source Selection..

P30

Bit 30: Edge /Level Interrupt Source Selection..

P31

Bit 31: Edge /Level Interrupt Source Selection..

LOCKSR

Lock Status

Offset: 0xe0, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Lock Status..

P1

Bit 1: Lock Status..

P2

Bit 2: Lock Status..

P3

Bit 3: Lock Status..

P4

Bit 4: Lock Status..

P5

Bit 5: Lock Status..

P6

Bit 6: Lock Status..

P7

Bit 7: Lock Status..

P8

Bit 8: Lock Status..

P9

Bit 9: Lock Status..

P10

Bit 10: Lock Status..

P11

Bit 11: Lock Status..

P12

Bit 12: Lock Status..

P13

Bit 13: Lock Status..

P14

Bit 14: Lock Status..

P15

Bit 15: Lock Status..

P16

Bit 16: Lock Status..

P17

Bit 17: Lock Status..

P18

Bit 18: Lock Status..

P19

Bit 19: Lock Status..

P20

Bit 20: Lock Status..

P21

Bit 21: Lock Status..

P22

Bit 22: Lock Status..

P23

Bit 23: Lock Status..

P24

Bit 24: Lock Status..

P25

Bit 25: Lock Status..

P26

Bit 26: Lock Status..

P27

Bit 27: Lock Status..

P28

Bit 28: Lock Status..

P29

Bit 29: Lock Status..

P30

Bit 30: Lock Status..

P31

Bit 31: Lock Status..

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

PIOB

0x400e1000: Parallel Input/Output Controller B

450/1285 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PER
0x4 PDR
0x8 PSR
0x10 OER
0x14 ODR
0x18 OSR
0x20 IFER
0x24 IFDR
0x28 IFSR
0x30 SODR
0x34 CODR
0x38 ODSR
0x3c PDSR
0x40 IER
0x44 IDR
0x48 IMR
0x4c ISR
0x50 MDER
0x54 MDDR
0x58 MDSR
0x60 PUDR
0x64 PUER
0x68 PUSR
0x70 ABSR
0x80 SCIFSR
0x84 DIFSR
0x88 IFDGSR
0x8c SCDR
0xa0 OWER
0xa4 OWDR
0xa8 OWSR
0xb0 AIMER
0xb4 AIMDR
0xb8 AIMMR
0xc0 ESR
0xc4 LSR
0xc8 ELSR
0xd0 FELLSR
0xd4 REHLSR
0xd8 FRLHSR
0xe0 LOCKSR
0xe4 WPMR
0xe8 WPSR

PER

PIO Enable Register

Offset: 0x0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Enable.

P1

Bit 1: PIO Enable.

P2

Bit 2: PIO Enable.

P3

Bit 3: PIO Enable.

P4

Bit 4: PIO Enable.

P5

Bit 5: PIO Enable.

P6

Bit 6: PIO Enable.

P7

Bit 7: PIO Enable.

P8

Bit 8: PIO Enable.

P9

Bit 9: PIO Enable.

P10

Bit 10: PIO Enable.

P11

Bit 11: PIO Enable.

P12

Bit 12: PIO Enable.

P13

Bit 13: PIO Enable.

P14

Bit 14: PIO Enable.

P15

Bit 15: PIO Enable.

P16

Bit 16: PIO Enable.

P17

Bit 17: PIO Enable.

P18

Bit 18: PIO Enable.

P19

Bit 19: PIO Enable.

P20

Bit 20: PIO Enable.

P21

Bit 21: PIO Enable.

P22

Bit 22: PIO Enable.

P23

Bit 23: PIO Enable.

P24

Bit 24: PIO Enable.

P25

Bit 25: PIO Enable.

P26

Bit 26: PIO Enable.

P27

Bit 27: PIO Enable.

P28

Bit 28: PIO Enable.

P29

Bit 29: PIO Enable.

P30

Bit 30: PIO Enable.

P31

Bit 31: PIO Enable.

PDR

PIO Disable Register

Offset: 0x4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Disable.

P1

Bit 1: PIO Disable.

P2

Bit 2: PIO Disable.

P3

Bit 3: PIO Disable.

P4

Bit 4: PIO Disable.

P5

Bit 5: PIO Disable.

P6

Bit 6: PIO Disable.

P7

Bit 7: PIO Disable.

P8

Bit 8: PIO Disable.

P9

Bit 9: PIO Disable.

P10

Bit 10: PIO Disable.

P11

Bit 11: PIO Disable.

P12

Bit 12: PIO Disable.

P13

Bit 13: PIO Disable.

P14

Bit 14: PIO Disable.

P15

Bit 15: PIO Disable.

P16

Bit 16: PIO Disable.

P17

Bit 17: PIO Disable.

P18

Bit 18: PIO Disable.

P19

Bit 19: PIO Disable.

P20

Bit 20: PIO Disable.

P21

Bit 21: PIO Disable.

P22

Bit 22: PIO Disable.

P23

Bit 23: PIO Disable.

P24

Bit 24: PIO Disable.

P25

Bit 25: PIO Disable.

P26

Bit 26: PIO Disable.

P27

Bit 27: PIO Disable.

P28

Bit 28: PIO Disable.

P29

Bit 29: PIO Disable.

P30

Bit 30: PIO Disable.

P31

Bit 31: PIO Disable.

PSR

PIO Status Register

Offset: 0x8, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: PIO Status.

P1

Bit 1: PIO Status.

P2

Bit 2: PIO Status.

P3

Bit 3: PIO Status.

P4

Bit 4: PIO Status.

P5

Bit 5: PIO Status.

P6

Bit 6: PIO Status.

P7

Bit 7: PIO Status.

P8

Bit 8: PIO Status.

P9

Bit 9: PIO Status.

P10

Bit 10: PIO Status.

P11

Bit 11: PIO Status.

P12

Bit 12: PIO Status.

P13

Bit 13: PIO Status.

P14

Bit 14: PIO Status.

P15

Bit 15: PIO Status.

P16

Bit 16: PIO Status.

P17

Bit 17: PIO Status.

P18

Bit 18: PIO Status.

P19

Bit 19: PIO Status.

P20

Bit 20: PIO Status.

P21

Bit 21: PIO Status.

P22

Bit 22: PIO Status.

P23

Bit 23: PIO Status.

P24

Bit 24: PIO Status.

P25

Bit 25: PIO Status.

P26

Bit 26: PIO Status.

P27

Bit 27: PIO Status.

P28

Bit 28: PIO Status.

P29

Bit 29: PIO Status.

P30

Bit 30: PIO Status.

P31

Bit 31: PIO Status.

OER

Output Enable Register

Offset: 0x10, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Enable.

P1

Bit 1: Output Enable.

P2

Bit 2: Output Enable.

P3

Bit 3: Output Enable.

P4

Bit 4: Output Enable.

P5

Bit 5: Output Enable.

P6

Bit 6: Output Enable.

P7

Bit 7: Output Enable.

P8

Bit 8: Output Enable.

P9

Bit 9: Output Enable.

P10

Bit 10: Output Enable.

P11

Bit 11: Output Enable.

P12

Bit 12: Output Enable.

P13

Bit 13: Output Enable.

P14

Bit 14: Output Enable.

P15

Bit 15: Output Enable.

P16

Bit 16: Output Enable.

P17

Bit 17: Output Enable.

P18

Bit 18: Output Enable.

P19

Bit 19: Output Enable.

P20

Bit 20: Output Enable.

P21

Bit 21: Output Enable.

P22

Bit 22: Output Enable.

P23

Bit 23: Output Enable.

P24

Bit 24: Output Enable.

P25

Bit 25: Output Enable.

P26

Bit 26: Output Enable.

P27

Bit 27: Output Enable.

P28

Bit 28: Output Enable.

P29

Bit 29: Output Enable.

P30

Bit 30: Output Enable.

P31

Bit 31: Output Enable.

ODR

Output Disable Register

Offset: 0x14, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Disable.

P1

Bit 1: Output Disable.

P2

Bit 2: Output Disable.

P3

Bit 3: Output Disable.

P4

Bit 4: Output Disable.

P5

Bit 5: Output Disable.

P6

Bit 6: Output Disable.

P7

Bit 7: Output Disable.

P8

Bit 8: Output Disable.

P9

Bit 9: Output Disable.

P10

Bit 10: Output Disable.

P11

Bit 11: Output Disable.

P12

Bit 12: Output Disable.

P13

Bit 13: Output Disable.

P14

Bit 14: Output Disable.

P15

Bit 15: Output Disable.

P16

Bit 16: Output Disable.

P17

Bit 17: Output Disable.

P18

Bit 18: Output Disable.

P19

Bit 19: Output Disable.

P20

Bit 20: Output Disable.

P21

Bit 21: Output Disable.

P22

Bit 22: Output Disable.

P23

Bit 23: Output Disable.

P24

Bit 24: Output Disable.

P25

Bit 25: Output Disable.

P26

Bit 26: Output Disable.

P27

Bit 27: Output Disable.

P28

Bit 28: Output Disable.

P29

Bit 29: Output Disable.

P30

Bit 30: Output Disable.

P31

Bit 31: Output Disable.

OSR

Output Status Register

Offset: 0x18, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Status.

P1

Bit 1: Output Status.

P2

Bit 2: Output Status.

P3

Bit 3: Output Status.

P4

Bit 4: Output Status.

P5

Bit 5: Output Status.

P6

Bit 6: Output Status.

P7

Bit 7: Output Status.

P8

Bit 8: Output Status.

P9

Bit 9: Output Status.

P10

Bit 10: Output Status.

P11

Bit 11: Output Status.

P12

Bit 12: Output Status.

P13

Bit 13: Output Status.

P14

Bit 14: Output Status.

P15

Bit 15: Output Status.

P16

Bit 16: Output Status.

P17

Bit 17: Output Status.

P18

Bit 18: Output Status.

P19

Bit 19: Output Status.

P20

Bit 20: Output Status.

P21

Bit 21: Output Status.

P22

Bit 22: Output Status.

P23

Bit 23: Output Status.

P24

Bit 24: Output Status.

P25

Bit 25: Output Status.

P26

Bit 26: Output Status.

P27

Bit 27: Output Status.

P28

Bit 28: Output Status.

P29

Bit 29: Output Status.

P30

Bit 30: Output Status.

P31

Bit 31: Output Status.

IFER

Glitch Input Filter Enable Register

Offset: 0x20, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Enable.

P1

Bit 1: Input Filter Enable.

P2

Bit 2: Input Filter Enable.

P3

Bit 3: Input Filter Enable.

P4

Bit 4: Input Filter Enable.

P5

Bit 5: Input Filter Enable.

P6

Bit 6: Input Filter Enable.

P7

Bit 7: Input Filter Enable.

P8

Bit 8: Input Filter Enable.

P9

Bit 9: Input Filter Enable.

P10

Bit 10: Input Filter Enable.

P11

Bit 11: Input Filter Enable.

P12

Bit 12: Input Filter Enable.

P13

Bit 13: Input Filter Enable.

P14

Bit 14: Input Filter Enable.

P15

Bit 15: Input Filter Enable.

P16

Bit 16: Input Filter Enable.

P17

Bit 17: Input Filter Enable.

P18

Bit 18: Input Filter Enable.

P19

Bit 19: Input Filter Enable.

P20

Bit 20: Input Filter Enable.

P21

Bit 21: Input Filter Enable.

P22

Bit 22: Input Filter Enable.

P23

Bit 23: Input Filter Enable.

P24

Bit 24: Input Filter Enable.

P25

Bit 25: Input Filter Enable.

P26

Bit 26: Input Filter Enable.

P27

Bit 27: Input Filter Enable.

P28

Bit 28: Input Filter Enable.

P29

Bit 29: Input Filter Enable.

P30

Bit 30: Input Filter Enable.

P31

Bit 31: Input Filter Enable.

IFDR

Glitch Input Filter Disable Register

Offset: 0x24, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Disable.

P1

Bit 1: Input Filter Disable.

P2

Bit 2: Input Filter Disable.

P3

Bit 3: Input Filter Disable.

P4

Bit 4: Input Filter Disable.

P5

Bit 5: Input Filter Disable.

P6

Bit 6: Input Filter Disable.

P7

Bit 7: Input Filter Disable.

P8

Bit 8: Input Filter Disable.

P9

Bit 9: Input Filter Disable.

P10

Bit 10: Input Filter Disable.

P11

Bit 11: Input Filter Disable.

P12

Bit 12: Input Filter Disable.

P13

Bit 13: Input Filter Disable.

P14

Bit 14: Input Filter Disable.

P15

Bit 15: Input Filter Disable.

P16

Bit 16: Input Filter Disable.

P17

Bit 17: Input Filter Disable.

P18

Bit 18: Input Filter Disable.

P19

Bit 19: Input Filter Disable.

P20

Bit 20: Input Filter Disable.

P21

Bit 21: Input Filter Disable.

P22

Bit 22: Input Filter Disable.

P23

Bit 23: Input Filter Disable.

P24

Bit 24: Input Filter Disable.

P25

Bit 25: Input Filter Disable.

P26

Bit 26: Input Filter Disable.

P27

Bit 27: Input Filter Disable.

P28

Bit 28: Input Filter Disable.

P29

Bit 29: Input Filter Disable.

P30

Bit 30: Input Filter Disable.

P31

Bit 31: Input Filter Disable.

IFSR

Glitch Input Filter Status Register

Offset: 0x28, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Filer Status.

P1

Bit 1: Input Filer Status.

P2

Bit 2: Input Filer Status.

P3

Bit 3: Input Filer Status.

P4

Bit 4: Input Filer Status.

P5

Bit 5: Input Filer Status.

P6

Bit 6: Input Filer Status.

P7

Bit 7: Input Filer Status.

P8

Bit 8: Input Filer Status.

P9

Bit 9: Input Filer Status.

P10

Bit 10: Input Filer Status.

P11

Bit 11: Input Filer Status.

P12

Bit 12: Input Filer Status.

P13

Bit 13: Input Filer Status.

P14

Bit 14: Input Filer Status.

P15

Bit 15: Input Filer Status.

P16

Bit 16: Input Filer Status.

P17

Bit 17: Input Filer Status.

P18

Bit 18: Input Filer Status.

P19

Bit 19: Input Filer Status.

P20

Bit 20: Input Filer Status.

P21

Bit 21: Input Filer Status.

P22

Bit 22: Input Filer Status.

P23

Bit 23: Input Filer Status.

P24

Bit 24: Input Filer Status.

P25

Bit 25: Input Filer Status.

P26

Bit 26: Input Filer Status.

P27

Bit 27: Input Filer Status.

P28

Bit 28: Input Filer Status.

P29

Bit 29: Input Filer Status.

P30

Bit 30: Input Filer Status.

P31

Bit 31: Input Filer Status.

SODR

Set Output Data Register

Offset: 0x30, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Set Output Data.

P1

Bit 1: Set Output Data.

P2

Bit 2: Set Output Data.

P3

Bit 3: Set Output Data.

P4

Bit 4: Set Output Data.

P5

Bit 5: Set Output Data.

P6

Bit 6: Set Output Data.

P7

Bit 7: Set Output Data.

P8

Bit 8: Set Output Data.

P9

Bit 9: Set Output Data.

P10

Bit 10: Set Output Data.

P11

Bit 11: Set Output Data.

P12

Bit 12: Set Output Data.

P13

Bit 13: Set Output Data.

P14

Bit 14: Set Output Data.

P15

Bit 15: Set Output Data.

P16

Bit 16: Set Output Data.

P17

Bit 17: Set Output Data.

P18

Bit 18: Set Output Data.

P19

Bit 19: Set Output Data.

P20

Bit 20: Set Output Data.

P21

Bit 21: Set Output Data.

P22

Bit 22: Set Output Data.

P23

Bit 23: Set Output Data.

P24

Bit 24: Set Output Data.

P25

Bit 25: Set Output Data.

P26

Bit 26: Set Output Data.

P27

Bit 27: Set Output Data.

P28

Bit 28: Set Output Data.

P29

Bit 29: Set Output Data.

P30

Bit 30: Set Output Data.

P31

Bit 31: Set Output Data.

CODR

Clear Output Data Register

Offset: 0x34, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Clear Output Data.

P1

Bit 1: Clear Output Data.

P2

Bit 2: Clear Output Data.

P3

Bit 3: Clear Output Data.

P4

Bit 4: Clear Output Data.

P5

Bit 5: Clear Output Data.

P6

Bit 6: Clear Output Data.

P7

Bit 7: Clear Output Data.

P8

Bit 8: Clear Output Data.

P9

Bit 9: Clear Output Data.

P10

Bit 10: Clear Output Data.

P11

Bit 11: Clear Output Data.

P12

Bit 12: Clear Output Data.

P13

Bit 13: Clear Output Data.

P14

Bit 14: Clear Output Data.

P15

Bit 15: Clear Output Data.

P16

Bit 16: Clear Output Data.

P17

Bit 17: Clear Output Data.

P18

Bit 18: Clear Output Data.

P19

Bit 19: Clear Output Data.

P20

Bit 20: Clear Output Data.

P21

Bit 21: Clear Output Data.

P22

Bit 22: Clear Output Data.

P23

Bit 23: Clear Output Data.

P24

Bit 24: Clear Output Data.

P25

Bit 25: Clear Output Data.

P26

Bit 26: Clear Output Data.

P27

Bit 27: Clear Output Data.

P28

Bit 28: Clear Output Data.

P29

Bit 29: Clear Output Data.

P30

Bit 30: Clear Output Data.

P31

Bit 31: Clear Output Data.

ODSR

Output Data Status Register

Offset: 0x38, reset: None, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

PDSR

Pin Data Status Register

Offset: 0x3c, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

IER

Interrupt Enable Register

Offset: 0x40, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Enable.

P1

Bit 1: Input Change Interrupt Enable.

P2

Bit 2: Input Change Interrupt Enable.

P3

Bit 3: Input Change Interrupt Enable.

P4

Bit 4: Input Change Interrupt Enable.

P5

Bit 5: Input Change Interrupt Enable.

P6

Bit 6: Input Change Interrupt Enable.

P7

Bit 7: Input Change Interrupt Enable.

P8

Bit 8: Input Change Interrupt Enable.

P9

Bit 9: Input Change Interrupt Enable.

P10

Bit 10: Input Change Interrupt Enable.

P11

Bit 11: Input Change Interrupt Enable.

P12

Bit 12: Input Change Interrupt Enable.

P13

Bit 13: Input Change Interrupt Enable.

P14

Bit 14: Input Change Interrupt Enable.

P15

Bit 15: Input Change Interrupt Enable.

P16

Bit 16: Input Change Interrupt Enable.

P17

Bit 17: Input Change Interrupt Enable.

P18

Bit 18: Input Change Interrupt Enable.

P19

Bit 19: Input Change Interrupt Enable.

P20

Bit 20: Input Change Interrupt Enable.

P21

Bit 21: Input Change Interrupt Enable.

P22

Bit 22: Input Change Interrupt Enable.

P23

Bit 23: Input Change Interrupt Enable.

P24

Bit 24: Input Change Interrupt Enable.

P25

Bit 25: Input Change Interrupt Enable.

P26

Bit 26: Input Change Interrupt Enable.

P27

Bit 27: Input Change Interrupt Enable.

P28

Bit 28: Input Change Interrupt Enable.

P29

Bit 29: Input Change Interrupt Enable.

P30

Bit 30: Input Change Interrupt Enable.

P31

Bit 31: Input Change Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x44, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Disable.

P1

Bit 1: Input Change Interrupt Disable.

P2

Bit 2: Input Change Interrupt Disable.

P3

Bit 3: Input Change Interrupt Disable.

P4

Bit 4: Input Change Interrupt Disable.

P5

Bit 5: Input Change Interrupt Disable.

P6

Bit 6: Input Change Interrupt Disable.

P7

Bit 7: Input Change Interrupt Disable.

P8

Bit 8: Input Change Interrupt Disable.

P9

Bit 9: Input Change Interrupt Disable.

P10

Bit 10: Input Change Interrupt Disable.

P11

Bit 11: Input Change Interrupt Disable.

P12

Bit 12: Input Change Interrupt Disable.

P13

Bit 13: Input Change Interrupt Disable.

P14

Bit 14: Input Change Interrupt Disable.

P15

Bit 15: Input Change Interrupt Disable.

P16

Bit 16: Input Change Interrupt Disable.

P17

Bit 17: Input Change Interrupt Disable.

P18

Bit 18: Input Change Interrupt Disable.

P19

Bit 19: Input Change Interrupt Disable.

P20

Bit 20: Input Change Interrupt Disable.

P21

Bit 21: Input Change Interrupt Disable.

P22

Bit 22: Input Change Interrupt Disable.

P23

Bit 23: Input Change Interrupt Disable.

P24

Bit 24: Input Change Interrupt Disable.

P25

Bit 25: Input Change Interrupt Disable.

P26

Bit 26: Input Change Interrupt Disable.

P27

Bit 27: Input Change Interrupt Disable.

P28

Bit 28: Input Change Interrupt Disable.

P29

Bit 29: Input Change Interrupt Disable.

P30

Bit 30: Input Change Interrupt Disable.

P31

Bit 31: Input Change Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x48, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Mask.

P1

Bit 1: Input Change Interrupt Mask.

P2

Bit 2: Input Change Interrupt Mask.

P3

Bit 3: Input Change Interrupt Mask.

P4

Bit 4: Input Change Interrupt Mask.

P5

Bit 5: Input Change Interrupt Mask.

P6

Bit 6: Input Change Interrupt Mask.

P7

Bit 7: Input Change Interrupt Mask.

P8

Bit 8: Input Change Interrupt Mask.

P9

Bit 9: Input Change Interrupt Mask.

P10

Bit 10: Input Change Interrupt Mask.

P11

Bit 11: Input Change Interrupt Mask.

P12

Bit 12: Input Change Interrupt Mask.

P13

Bit 13: Input Change Interrupt Mask.

P14

Bit 14: Input Change Interrupt Mask.

P15

Bit 15: Input Change Interrupt Mask.

P16

Bit 16: Input Change Interrupt Mask.

P17

Bit 17: Input Change Interrupt Mask.

P18

Bit 18: Input Change Interrupt Mask.

P19

Bit 19: Input Change Interrupt Mask.

P20

Bit 20: Input Change Interrupt Mask.

P21

Bit 21: Input Change Interrupt Mask.

P22

Bit 22: Input Change Interrupt Mask.

P23

Bit 23: Input Change Interrupt Mask.

P24

Bit 24: Input Change Interrupt Mask.

P25

Bit 25: Input Change Interrupt Mask.

P26

Bit 26: Input Change Interrupt Mask.

P27

Bit 27: Input Change Interrupt Mask.

P28

Bit 28: Input Change Interrupt Mask.

P29

Bit 29: Input Change Interrupt Mask.

P30

Bit 30: Input Change Interrupt Mask.

P31

Bit 31: Input Change Interrupt Mask.

ISR

Interrupt Status Register

Offset: 0x4c, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Status.

P1

Bit 1: Input Change Interrupt Status.

P2

Bit 2: Input Change Interrupt Status.

P3

Bit 3: Input Change Interrupt Status.

P4

Bit 4: Input Change Interrupt Status.

P5

Bit 5: Input Change Interrupt Status.

P6

Bit 6: Input Change Interrupt Status.

P7

Bit 7: Input Change Interrupt Status.

P8

Bit 8: Input Change Interrupt Status.

P9

Bit 9: Input Change Interrupt Status.

P10

Bit 10: Input Change Interrupt Status.

P11

Bit 11: Input Change Interrupt Status.

P12

Bit 12: Input Change Interrupt Status.

P13

Bit 13: Input Change Interrupt Status.

P14

Bit 14: Input Change Interrupt Status.

P15

Bit 15: Input Change Interrupt Status.

P16

Bit 16: Input Change Interrupt Status.

P17

Bit 17: Input Change Interrupt Status.

P18

Bit 18: Input Change Interrupt Status.

P19

Bit 19: Input Change Interrupt Status.

P20

Bit 20: Input Change Interrupt Status.

P21

Bit 21: Input Change Interrupt Status.

P22

Bit 22: Input Change Interrupt Status.

P23

Bit 23: Input Change Interrupt Status.

P24

Bit 24: Input Change Interrupt Status.

P25

Bit 25: Input Change Interrupt Status.

P26

Bit 26: Input Change Interrupt Status.

P27

Bit 27: Input Change Interrupt Status.

P28

Bit 28: Input Change Interrupt Status.

P29

Bit 29: Input Change Interrupt Status.

P30

Bit 30: Input Change Interrupt Status.

P31

Bit 31: Input Change Interrupt Status.

MDER

Multi-driver Enable Register

Offset: 0x50, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Enable..

P1

Bit 1: Multi Drive Enable..

P2

Bit 2: Multi Drive Enable..

P3

Bit 3: Multi Drive Enable..

P4

Bit 4: Multi Drive Enable..

P5

Bit 5: Multi Drive Enable..

P6

Bit 6: Multi Drive Enable..

P7

Bit 7: Multi Drive Enable..

P8

Bit 8: Multi Drive Enable..

P9

Bit 9: Multi Drive Enable..

P10

Bit 10: Multi Drive Enable..

P11

Bit 11: Multi Drive Enable..

P12

Bit 12: Multi Drive Enable..

P13

Bit 13: Multi Drive Enable..

P14

Bit 14: Multi Drive Enable..

P15

Bit 15: Multi Drive Enable..

P16

Bit 16: Multi Drive Enable..

P17

Bit 17: Multi Drive Enable..

P18

Bit 18: Multi Drive Enable..

P19

Bit 19: Multi Drive Enable..

P20

Bit 20: Multi Drive Enable..

P21

Bit 21: Multi Drive Enable..

P22

Bit 22: Multi Drive Enable..

P23

Bit 23: Multi Drive Enable..

P24

Bit 24: Multi Drive Enable..

P25

Bit 25: Multi Drive Enable..

P26

Bit 26: Multi Drive Enable..

P27

Bit 27: Multi Drive Enable..

P28

Bit 28: Multi Drive Enable..

P29

Bit 29: Multi Drive Enable..

P30

Bit 30: Multi Drive Enable..

P31

Bit 31: Multi Drive Enable..

MDDR

Multi-driver Disable Register

Offset: 0x54, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Disable..

P1

Bit 1: Multi Drive Disable..

P2

Bit 2: Multi Drive Disable..

P3

Bit 3: Multi Drive Disable..

P4

Bit 4: Multi Drive Disable..

P5

Bit 5: Multi Drive Disable..

P6

Bit 6: Multi Drive Disable..

P7

Bit 7: Multi Drive Disable..

P8

Bit 8: Multi Drive Disable..

P9

Bit 9: Multi Drive Disable..

P10

Bit 10: Multi Drive Disable..

P11

Bit 11: Multi Drive Disable..

P12

Bit 12: Multi Drive Disable..

P13

Bit 13: Multi Drive Disable..

P14

Bit 14: Multi Drive Disable..

P15

Bit 15: Multi Drive Disable..

P16

Bit 16: Multi Drive Disable..

P17

Bit 17: Multi Drive Disable..

P18

Bit 18: Multi Drive Disable..

P19

Bit 19: Multi Drive Disable..

P20

Bit 20: Multi Drive Disable..

P21

Bit 21: Multi Drive Disable..

P22

Bit 22: Multi Drive Disable..

P23

Bit 23: Multi Drive Disable..

P24

Bit 24: Multi Drive Disable..

P25

Bit 25: Multi Drive Disable..

P26

Bit 26: Multi Drive Disable..

P27

Bit 27: Multi Drive Disable..

P28

Bit 28: Multi Drive Disable..

P29

Bit 29: Multi Drive Disable..

P30

Bit 30: Multi Drive Disable..

P31

Bit 31: Multi Drive Disable..

MDSR

Multi-driver Status Register

Offset: 0x58, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Multi Drive Status..

P1

Bit 1: Multi Drive Status..

P2

Bit 2: Multi Drive Status..

P3

Bit 3: Multi Drive Status..

P4

Bit 4: Multi Drive Status..

P5

Bit 5: Multi Drive Status..

P6

Bit 6: Multi Drive Status..

P7

Bit 7: Multi Drive Status..

P8

Bit 8: Multi Drive Status..

P9

Bit 9: Multi Drive Status..

P10

Bit 10: Multi Drive Status..

P11

Bit 11: Multi Drive Status..

P12

Bit 12: Multi Drive Status..

P13

Bit 13: Multi Drive Status..

P14

Bit 14: Multi Drive Status..

P15

Bit 15: Multi Drive Status..

P16

Bit 16: Multi Drive Status..

P17

Bit 17: Multi Drive Status..

P18

Bit 18: Multi Drive Status..

P19

Bit 19: Multi Drive Status..

P20

Bit 20: Multi Drive Status..

P21

Bit 21: Multi Drive Status..

P22

Bit 22: Multi Drive Status..

P23

Bit 23: Multi Drive Status..

P24

Bit 24: Multi Drive Status..

P25

Bit 25: Multi Drive Status..

P26

Bit 26: Multi Drive Status..

P27

Bit 27: Multi Drive Status..

P28

Bit 28: Multi Drive Status..

P29

Bit 29: Multi Drive Status..

P30

Bit 30: Multi Drive Status..

P31

Bit 31: Multi Drive Status..

PUDR

Pull-up Disable Register

Offset: 0x60, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Disable..

P1

Bit 1: Pull Up Disable..

P2

Bit 2: Pull Up Disable..

P3

Bit 3: Pull Up Disable..

P4

Bit 4: Pull Up Disable..

P5

Bit 5: Pull Up Disable..

P6

Bit 6: Pull Up Disable..

P7

Bit 7: Pull Up Disable..

P8

Bit 8: Pull Up Disable..

P9

Bit 9: Pull Up Disable..

P10

Bit 10: Pull Up Disable..

P11

Bit 11: Pull Up Disable..

P12

Bit 12: Pull Up Disable..

P13

Bit 13: Pull Up Disable..

P14

Bit 14: Pull Up Disable..

P15

Bit 15: Pull Up Disable..

P16

Bit 16: Pull Up Disable..

P17

Bit 17: Pull Up Disable..

P18

Bit 18: Pull Up Disable..

P19

Bit 19: Pull Up Disable..

P20

Bit 20: Pull Up Disable..

P21

Bit 21: Pull Up Disable..

P22

Bit 22: Pull Up Disable..

P23

Bit 23: Pull Up Disable..

P24

Bit 24: Pull Up Disable..

P25

Bit 25: Pull Up Disable..

P26

Bit 26: Pull Up Disable..

P27

Bit 27: Pull Up Disable..

P28

Bit 28: Pull Up Disable..

P29

Bit 29: Pull Up Disable..

P30

Bit 30: Pull Up Disable..

P31

Bit 31: Pull Up Disable..

PUER

Pull-up Enable Register

Offset: 0x64, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Enable..

P1

Bit 1: Pull Up Enable..

P2

Bit 2: Pull Up Enable..

P3

Bit 3: Pull Up Enable..

P4

Bit 4: Pull Up Enable..

P5

Bit 5: Pull Up Enable..

P6

Bit 6: Pull Up Enable..

P7

Bit 7: Pull Up Enable..

P8

Bit 8: Pull Up Enable..

P9

Bit 9: Pull Up Enable..

P10

Bit 10: Pull Up Enable..

P11

Bit 11: Pull Up Enable..

P12

Bit 12: Pull Up Enable..

P13

Bit 13: Pull Up Enable..

P14

Bit 14: Pull Up Enable..

P15

Bit 15: Pull Up Enable..

P16

Bit 16: Pull Up Enable..

P17

Bit 17: Pull Up Enable..

P18

Bit 18: Pull Up Enable..

P19

Bit 19: Pull Up Enable..

P20

Bit 20: Pull Up Enable..

P21

Bit 21: Pull Up Enable..

P22

Bit 22: Pull Up Enable..

P23

Bit 23: Pull Up Enable..

P24

Bit 24: Pull Up Enable..

P25

Bit 25: Pull Up Enable..

P26

Bit 26: Pull Up Enable..

P27

Bit 27: Pull Up Enable..

P28

Bit 28: Pull Up Enable..

P29

Bit 29: Pull Up Enable..

P30

Bit 30: Pull Up Enable..

P31

Bit 31: Pull Up Enable..

PUSR

Pad Pull-up Status Register

Offset: 0x68, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Pull Up Status..

P1

Bit 1: Pull Up Status..

P2

Bit 2: Pull Up Status..

P3

Bit 3: Pull Up Status..

P4

Bit 4: Pull Up Status..

P5

Bit 5: Pull Up Status..

P6

Bit 6: Pull Up Status..

P7

Bit 7: Pull Up Status..

P8

Bit 8: Pull Up Status..

P9

Bit 9: Pull Up Status..

P10

Bit 10: Pull Up Status..

P11

Bit 11: Pull Up Status..

P12

Bit 12: Pull Up Status..

P13

Bit 13: Pull Up Status..

P14

Bit 14: Pull Up Status..

P15

Bit 15: Pull Up Status..

P16

Bit 16: Pull Up Status..

P17

Bit 17: Pull Up Status..

P18

Bit 18: Pull Up Status..

P19

Bit 19: Pull Up Status..

P20

Bit 20: Pull Up Status..

P21

Bit 21: Pull Up Status..

P22

Bit 22: Pull Up Status..

P23

Bit 23: Pull Up Status..

P24

Bit 24: Pull Up Status..

P25

Bit 25: Pull Up Status..

P26

Bit 26: Pull Up Status..

P27

Bit 27: Pull Up Status..

P28

Bit 28: Pull Up Status..

P29

Bit 29: Pull Up Status..

P30

Bit 30: Pull Up Status..

P31

Bit 31: Pull Up Status..

ABSR

Peripheral AB Select Register

Offset: 0x70, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Peripheral A Select..

P1

Bit 1: Peripheral A Select..

P2

Bit 2: Peripheral A Select..

P3

Bit 3: Peripheral A Select..

P4

Bit 4: Peripheral A Select..

P5

Bit 5: Peripheral A Select..

P6

Bit 6: Peripheral A Select..

P7

Bit 7: Peripheral A Select..

P8

Bit 8: Peripheral A Select..

P9

Bit 9: Peripheral A Select..

P10

Bit 10: Peripheral A Select..

P11

Bit 11: Peripheral A Select..

P12

Bit 12: Peripheral A Select..

P13

Bit 13: Peripheral A Select..

P14

Bit 14: Peripheral A Select..

P15

Bit 15: Peripheral A Select..

P16

Bit 16: Peripheral A Select..

P17

Bit 17: Peripheral A Select..

P18

Bit 18: Peripheral A Select..

P19

Bit 19: Peripheral A Select..

P20

Bit 20: Peripheral A Select..

P21

Bit 21: Peripheral A Select..

P22

Bit 22: Peripheral A Select..

P23

Bit 23: Peripheral A Select..

P24

Bit 24: Peripheral A Select..

P25

Bit 25: Peripheral A Select..

P26

Bit 26: Peripheral A Select..

P27

Bit 27: Peripheral A Select..

P28

Bit 28: Peripheral A Select..

P29

Bit 29: Peripheral A Select..

P30

Bit 30: Peripheral A Select..

P31

Bit 31: Peripheral A Select..

SCIFSR

System Clock Glitch Input Filter Select Register

Offset: 0x80, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: System Clock Glitch Filtering Select..

P1

Bit 1: System Clock Glitch Filtering Select..

P2

Bit 2: System Clock Glitch Filtering Select..

P3

Bit 3: System Clock Glitch Filtering Select..

P4

Bit 4: System Clock Glitch Filtering Select..

P5

Bit 5: System Clock Glitch Filtering Select..

P6

Bit 6: System Clock Glitch Filtering Select..

P7

Bit 7: System Clock Glitch Filtering Select..

P8

Bit 8: System Clock Glitch Filtering Select..

P9

Bit 9: System Clock Glitch Filtering Select..

P10

Bit 10: System Clock Glitch Filtering Select..

P11

Bit 11: System Clock Glitch Filtering Select..

P12

Bit 12: System Clock Glitch Filtering Select..

P13

Bit 13: System Clock Glitch Filtering Select..

P14

Bit 14: System Clock Glitch Filtering Select..

P15

Bit 15: System Clock Glitch Filtering Select..

P16

Bit 16: System Clock Glitch Filtering Select..

P17

Bit 17: System Clock Glitch Filtering Select..

P18

Bit 18: System Clock Glitch Filtering Select..

P19

Bit 19: System Clock Glitch Filtering Select..

P20

Bit 20: System Clock Glitch Filtering Select..

P21

Bit 21: System Clock Glitch Filtering Select..

P22

Bit 22: System Clock Glitch Filtering Select..

P23

Bit 23: System Clock Glitch Filtering Select..

P24

Bit 24: System Clock Glitch Filtering Select..

P25

Bit 25: System Clock Glitch Filtering Select..

P26

Bit 26: System Clock Glitch Filtering Select..

P27

Bit 27: System Clock Glitch Filtering Select..

P28

Bit 28: System Clock Glitch Filtering Select..

P29

Bit 29: System Clock Glitch Filtering Select..

P30

Bit 30: System Clock Glitch Filtering Select..

P31

Bit 31: System Clock Glitch Filtering Select..

DIFSR

Debouncing Input Filter Select Register

Offset: 0x84, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Debouncing Filtering Select..

P1

Bit 1: Debouncing Filtering Select..

P2

Bit 2: Debouncing Filtering Select..

P3

Bit 3: Debouncing Filtering Select..

P4

Bit 4: Debouncing Filtering Select..

P5

Bit 5: Debouncing Filtering Select..

P6

Bit 6: Debouncing Filtering Select..

P7

Bit 7: Debouncing Filtering Select..

P8

Bit 8: Debouncing Filtering Select..

P9

Bit 9: Debouncing Filtering Select..

P10

Bit 10: Debouncing Filtering Select..

P11

Bit 11: Debouncing Filtering Select..

P12

Bit 12: Debouncing Filtering Select..

P13

Bit 13: Debouncing Filtering Select..

P14

Bit 14: Debouncing Filtering Select..

P15

Bit 15: Debouncing Filtering Select..

P16

Bit 16: Debouncing Filtering Select..

P17

Bit 17: Debouncing Filtering Select..

P18

Bit 18: Debouncing Filtering Select..

P19

Bit 19: Debouncing Filtering Select..

P20

Bit 20: Debouncing Filtering Select..

P21

Bit 21: Debouncing Filtering Select..

P22

Bit 22: Debouncing Filtering Select..

P23

Bit 23: Debouncing Filtering Select..

P24

Bit 24: Debouncing Filtering Select..

P25

Bit 25: Debouncing Filtering Select..

P26

Bit 26: Debouncing Filtering Select..

P27

Bit 27: Debouncing Filtering Select..

P28

Bit 28: Debouncing Filtering Select..

P29

Bit 29: Debouncing Filtering Select..

P30

Bit 30: Debouncing Filtering Select..

P31

Bit 31: Debouncing Filtering Select..

IFDGSR

Glitch or Debouncing Input Filter Clock Selection Status Register

Offset: 0x88, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Glitch or Debouncing Filter Selection Status.

P1

Bit 1: Glitch or Debouncing Filter Selection Status.

P2

Bit 2: Glitch or Debouncing Filter Selection Status.

P3

Bit 3: Glitch or Debouncing Filter Selection Status.

P4

Bit 4: Glitch or Debouncing Filter Selection Status.

P5

Bit 5: Glitch or Debouncing Filter Selection Status.

P6

Bit 6: Glitch or Debouncing Filter Selection Status.

P7

Bit 7: Glitch or Debouncing Filter Selection Status.

P8

Bit 8: Glitch or Debouncing Filter Selection Status.

P9

Bit 9: Glitch or Debouncing Filter Selection Status.

P10

Bit 10: Glitch or Debouncing Filter Selection Status.

P11

Bit 11: Glitch or Debouncing Filter Selection Status.

P12

Bit 12: Glitch or Debouncing Filter Selection Status.

P13

Bit 13: Glitch or Debouncing Filter Selection Status.

P14

Bit 14: Glitch or Debouncing Filter Selection Status.

P15

Bit 15: Glitch or Debouncing Filter Selection Status.

P16

Bit 16: Glitch or Debouncing Filter Selection Status.

P17

Bit 17: Glitch or Debouncing Filter Selection Status.

P18

Bit 18: Glitch or Debouncing Filter Selection Status.

P19

Bit 19: Glitch or Debouncing Filter Selection Status.

P20

Bit 20: Glitch or Debouncing Filter Selection Status.

P21

Bit 21: Glitch or Debouncing Filter Selection Status.

P22

Bit 22: Glitch or Debouncing Filter Selection Status.

P23

Bit 23: Glitch or Debouncing Filter Selection Status.

P24

Bit 24: Glitch or Debouncing Filter Selection Status.

P25

Bit 25: Glitch or Debouncing Filter Selection Status.

P26

Bit 26: Glitch or Debouncing Filter Selection Status.

P27

Bit 27: Glitch or Debouncing Filter Selection Status.

P28

Bit 28: Glitch or Debouncing Filter Selection Status.

P29

Bit 29: Glitch or Debouncing Filter Selection Status.

P30

Bit 30: Glitch or Debouncing Filter Selection Status.

P31

Bit 31: Glitch or Debouncing Filter Selection Status.

SCDR

Slow Clock Divider Debouncing Register

Offset: 0x8c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-13: Slow Clock Divider Selection for Debouncing.

OWER

Output Write Enable

Offset: 0xa0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Enable..

P1

Bit 1: Output Write Enable..

P2

Bit 2: Output Write Enable..

P3

Bit 3: Output Write Enable..

P4

Bit 4: Output Write Enable..

P5

Bit 5: Output Write Enable..

P6

Bit 6: Output Write Enable..

P7

Bit 7: Output Write Enable..

P8

Bit 8: Output Write Enable..

P9

Bit 9: Output Write Enable..

P10

Bit 10: Output Write Enable..

P11

Bit 11: Output Write Enable..

P12

Bit 12: Output Write Enable..

P13

Bit 13: Output Write Enable..

P14

Bit 14: Output Write Enable..

P15

Bit 15: Output Write Enable..

P16

Bit 16: Output Write Enable..

P17

Bit 17: Output Write Enable..

P18

Bit 18: Output Write Enable..

P19

Bit 19: Output Write Enable..

P20

Bit 20: Output Write Enable..

P21

Bit 21: Output Write Enable..

P22

Bit 22: Output Write Enable..

P23

Bit 23: Output Write Enable..

P24

Bit 24: Output Write Enable..

P25

Bit 25: Output Write Enable..

P26

Bit 26: Output Write Enable..

P27

Bit 27: Output Write Enable..

P28

Bit 28: Output Write Enable..

P29

Bit 29: Output Write Enable..

P30

Bit 30: Output Write Enable..

P31

Bit 31: Output Write Enable..

OWDR

Output Write Disable

Offset: 0xa4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Disable..

P1

Bit 1: Output Write Disable..

P2

Bit 2: Output Write Disable..

P3

Bit 3: Output Write Disable..

P4

Bit 4: Output Write Disable..

P5

Bit 5: Output Write Disable..

P6

Bit 6: Output Write Disable..

P7

Bit 7: Output Write Disable..

P8

Bit 8: Output Write Disable..

P9

Bit 9: Output Write Disable..

P10

Bit 10: Output Write Disable..

P11

Bit 11: Output Write Disable..

P12

Bit 12: Output Write Disable..

P13

Bit 13: Output Write Disable..

P14

Bit 14: Output Write Disable..

P15

Bit 15: Output Write Disable..

P16

Bit 16: Output Write Disable..

P17

Bit 17: Output Write Disable..

P18

Bit 18: Output Write Disable..

P19

Bit 19: Output Write Disable..

P20

Bit 20: Output Write Disable..

P21

Bit 21: Output Write Disable..

P22

Bit 22: Output Write Disable..

P23

Bit 23: Output Write Disable..

P24

Bit 24: Output Write Disable..

P25

Bit 25: Output Write Disable..

P26

Bit 26: Output Write Disable..

P27

Bit 27: Output Write Disable..

P28

Bit 28: Output Write Disable..

P29

Bit 29: Output Write Disable..

P30

Bit 30: Output Write Disable..

P31

Bit 31: Output Write Disable..

OWSR

Output Write Status Register

Offset: 0xa8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Write Status..

P1

Bit 1: Output Write Status..

P2

Bit 2: Output Write Status..

P3

Bit 3: Output Write Status..

P4

Bit 4: Output Write Status..

P5

Bit 5: Output Write Status..

P6

Bit 6: Output Write Status..

P7

Bit 7: Output Write Status..

P8

Bit 8: Output Write Status..

P9

Bit 9: Output Write Status..

P10

Bit 10: Output Write Status..

P11

Bit 11: Output Write Status..

P12

Bit 12: Output Write Status..

P13

Bit 13: Output Write Status..

P14

Bit 14: Output Write Status..

P15

Bit 15: Output Write Status..

P16

Bit 16: Output Write Status..

P17

Bit 17: Output Write Status..

P18

Bit 18: Output Write Status..

P19

Bit 19: Output Write Status..

P20

Bit 20: Output Write Status..

P21

Bit 21: Output Write Status..

P22

Bit 22: Output Write Status..

P23

Bit 23: Output Write Status..

P24

Bit 24: Output Write Status..

P25

Bit 25: Output Write Status..

P26

Bit 26: Output Write Status..

P27

Bit 27: Output Write Status..

P28

Bit 28: Output Write Status..

P29

Bit 29: Output Write Status..

P30

Bit 30: Output Write Status..

P31

Bit 31: Output Write Status..

AIMER

Additional Interrupt Modes Enable Register

Offset: 0xb0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Enable..

P1

Bit 1: Additional Interrupt Modes Enable..

P2

Bit 2: Additional Interrupt Modes Enable..

P3

Bit 3: Additional Interrupt Modes Enable..

P4

Bit 4: Additional Interrupt Modes Enable..

P5

Bit 5: Additional Interrupt Modes Enable..

P6

Bit 6: Additional Interrupt Modes Enable..

P7

Bit 7: Additional Interrupt Modes Enable..

P8

Bit 8: Additional Interrupt Modes Enable..

P9

Bit 9: Additional Interrupt Modes Enable..

P10

Bit 10: Additional Interrupt Modes Enable..

P11

Bit 11: Additional Interrupt Modes Enable..

P12

Bit 12: Additional Interrupt Modes Enable..

P13

Bit 13: Additional Interrupt Modes Enable..

P14

Bit 14: Additional Interrupt Modes Enable..

P15

Bit 15: Additional Interrupt Modes Enable..

P16

Bit 16: Additional Interrupt Modes Enable..

P17

Bit 17: Additional Interrupt Modes Enable..

P18

Bit 18: Additional Interrupt Modes Enable..

P19

Bit 19: Additional Interrupt Modes Enable..

P20

Bit 20: Additional Interrupt Modes Enable..

P21

Bit 21: Additional Interrupt Modes Enable..

P22

Bit 22: Additional Interrupt Modes Enable..

P23

Bit 23: Additional Interrupt Modes Enable..

P24

Bit 24: Additional Interrupt Modes Enable..

P25

Bit 25: Additional Interrupt Modes Enable..

P26

Bit 26: Additional Interrupt Modes Enable..

P27

Bit 27: Additional Interrupt Modes Enable..

P28

Bit 28: Additional Interrupt Modes Enable..

P29

Bit 29: Additional Interrupt Modes Enable..

P30

Bit 30: Additional Interrupt Modes Enable..

P31

Bit 31: Additional Interrupt Modes Enable..

AIMDR

Additional Interrupt Modes Disables Register

Offset: 0xb4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Disable..

P1

Bit 1: Additional Interrupt Modes Disable..

P2

Bit 2: Additional Interrupt Modes Disable..

P3

Bit 3: Additional Interrupt Modes Disable..

P4

Bit 4: Additional Interrupt Modes Disable..

P5

Bit 5: Additional Interrupt Modes Disable..

P6

Bit 6: Additional Interrupt Modes Disable..

P7

Bit 7: Additional Interrupt Modes Disable..

P8

Bit 8: Additional Interrupt Modes Disable..

P9

Bit 9: Additional Interrupt Modes Disable..

P10

Bit 10: Additional Interrupt Modes Disable..

P11

Bit 11: Additional Interrupt Modes Disable..

P12

Bit 12: Additional Interrupt Modes Disable..

P13

Bit 13: Additional Interrupt Modes Disable..

P14

Bit 14: Additional Interrupt Modes Disable..

P15

Bit 15: Additional Interrupt Modes Disable..

P16

Bit 16: Additional Interrupt Modes Disable..

P17

Bit 17: Additional Interrupt Modes Disable..

P18

Bit 18: Additional Interrupt Modes Disable..

P19

Bit 19: Additional Interrupt Modes Disable..

P20

Bit 20: Additional Interrupt Modes Disable..

P21

Bit 21: Additional Interrupt Modes Disable..

P22

Bit 22: Additional Interrupt Modes Disable..

P23

Bit 23: Additional Interrupt Modes Disable..

P24

Bit 24: Additional Interrupt Modes Disable..

P25

Bit 25: Additional Interrupt Modes Disable..

P26

Bit 26: Additional Interrupt Modes Disable..

P27

Bit 27: Additional Interrupt Modes Disable..

P28

Bit 28: Additional Interrupt Modes Disable..

P29

Bit 29: Additional Interrupt Modes Disable..

P30

Bit 30: Additional Interrupt Modes Disable..

P31

Bit 31: Additional Interrupt Modes Disable..

AIMMR

Additional Interrupt Modes Mask Register

Offset: 0xb8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Peripheral CD Status..

P1

Bit 1: Peripheral CD Status..

P2

Bit 2: Peripheral CD Status..

P3

Bit 3: Peripheral CD Status..

P4

Bit 4: Peripheral CD Status..

P5

Bit 5: Peripheral CD Status..

P6

Bit 6: Peripheral CD Status..

P7

Bit 7: Peripheral CD Status..

P8

Bit 8: Peripheral CD Status..

P9

Bit 9: Peripheral CD Status..

P10

Bit 10: Peripheral CD Status..

P11

Bit 11: Peripheral CD Status..

P12

Bit 12: Peripheral CD Status..

P13

Bit 13: Peripheral CD Status..

P14

Bit 14: Peripheral CD Status..

P15

Bit 15: Peripheral CD Status..

P16

Bit 16: Peripheral CD Status..

P17

Bit 17: Peripheral CD Status..

P18

Bit 18: Peripheral CD Status..

P19

Bit 19: Peripheral CD Status..

P20

Bit 20: Peripheral CD Status..

P21

Bit 21: Peripheral CD Status..

P22

Bit 22: Peripheral CD Status..

P23

Bit 23: Peripheral CD Status..

P24

Bit 24: Peripheral CD Status..

P25

Bit 25: Peripheral CD Status..

P26

Bit 26: Peripheral CD Status..

P27

Bit 27: Peripheral CD Status..

P28

Bit 28: Peripheral CD Status..

P29

Bit 29: Peripheral CD Status..

P30

Bit 30: Peripheral CD Status..

P31

Bit 31: Peripheral CD Status..

ESR

Edge Select Register

Offset: 0xc0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Edge Interrupt Selection..

P1

Bit 1: Edge Interrupt Selection..

P2

Bit 2: Edge Interrupt Selection..

P3

Bit 3: Edge Interrupt Selection..

P4

Bit 4: Edge Interrupt Selection..

P5

Bit 5: Edge Interrupt Selection..

P6

Bit 6: Edge Interrupt Selection..

P7

Bit 7: Edge Interrupt Selection..

P8

Bit 8: Edge Interrupt Selection..

P9

Bit 9: Edge Interrupt Selection..

P10

Bit 10: Edge Interrupt Selection..

P11

Bit 11: Edge Interrupt Selection..

P12

Bit 12: Edge Interrupt Selection..

P13

Bit 13: Edge Interrupt Selection..

P14

Bit 14: Edge Interrupt Selection..

P15

Bit 15: Edge Interrupt Selection..

P16

Bit 16: Edge Interrupt Selection..

P17

Bit 17: Edge Interrupt Selection..

P18

Bit 18: Edge Interrupt Selection..

P19

Bit 19: Edge Interrupt Selection..

P20

Bit 20: Edge Interrupt Selection..

P21

Bit 21: Edge Interrupt Selection..

P22

Bit 22: Edge Interrupt Selection..

P23

Bit 23: Edge Interrupt Selection..

P24

Bit 24: Edge Interrupt Selection..

P25

Bit 25: Edge Interrupt Selection..

P26

Bit 26: Edge Interrupt Selection..

P27

Bit 27: Edge Interrupt Selection..

P28

Bit 28: Edge Interrupt Selection..

P29

Bit 29: Edge Interrupt Selection..

P30

Bit 30: Edge Interrupt Selection..

P31

Bit 31: Edge Interrupt Selection..

LSR

Level Select Register

Offset: 0xc4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Level Interrupt Selection..

P1

Bit 1: Level Interrupt Selection..

P2

Bit 2: Level Interrupt Selection..

P3

Bit 3: Level Interrupt Selection..

P4

Bit 4: Level Interrupt Selection..

P5

Bit 5: Level Interrupt Selection..

P6

Bit 6: Level Interrupt Selection..

P7

Bit 7: Level Interrupt Selection..

P8

Bit 8: Level Interrupt Selection..

P9

Bit 9: Level Interrupt Selection..

P10

Bit 10: Level Interrupt Selection..

P11

Bit 11: Level Interrupt Selection..

P12

Bit 12: Level Interrupt Selection..

P13

Bit 13: Level Interrupt Selection..

P14

Bit 14: Level Interrupt Selection..

P15

Bit 15: Level Interrupt Selection..

P16

Bit 16: Level Interrupt Selection..

P17

Bit 17: Level Interrupt Selection..

P18

Bit 18: Level Interrupt Selection..

P19

Bit 19: Level Interrupt Selection..

P20

Bit 20: Level Interrupt Selection..

P21

Bit 21: Level Interrupt Selection..

P22

Bit 22: Level Interrupt Selection..

P23

Bit 23: Level Interrupt Selection..

P24

Bit 24: Level Interrupt Selection..

P25

Bit 25: Level Interrupt Selection..

P26

Bit 26: Level Interrupt Selection..

P27

Bit 27: Level Interrupt Selection..

P28

Bit 28: Level Interrupt Selection..

P29

Bit 29: Level Interrupt Selection..

P30

Bit 30: Level Interrupt Selection..

P31

Bit 31: Level Interrupt Selection..

ELSR

Edge/Level Status Register

Offset: 0xc8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge/Level Interrupt source selection..

P1

Bit 1: Edge/Level Interrupt source selection..

P2

Bit 2: Edge/Level Interrupt source selection..

P3

Bit 3: Edge/Level Interrupt source selection..

P4

Bit 4: Edge/Level Interrupt source selection..

P5

Bit 5: Edge/Level Interrupt source selection..

P6

Bit 6: Edge/Level Interrupt source selection..

P7

Bit 7: Edge/Level Interrupt source selection..

P8

Bit 8: Edge/Level Interrupt source selection..

P9

Bit 9: Edge/Level Interrupt source selection..

P10

Bit 10: Edge/Level Interrupt source selection..

P11

Bit 11: Edge/Level Interrupt source selection..

P12

Bit 12: Edge/Level Interrupt source selection..

P13

Bit 13: Edge/Level Interrupt source selection..

P14

Bit 14: Edge/Level Interrupt source selection..

P15

Bit 15: Edge/Level Interrupt source selection..

P16

Bit 16: Edge/Level Interrupt source selection..

P17

Bit 17: Edge/Level Interrupt source selection..

P18

Bit 18: Edge/Level Interrupt source selection..

P19

Bit 19: Edge/Level Interrupt source selection..

P20

Bit 20: Edge/Level Interrupt source selection..

P21

Bit 21: Edge/Level Interrupt source selection..

P22

Bit 22: Edge/Level Interrupt source selection..

P23

Bit 23: Edge/Level Interrupt source selection..

P24

Bit 24: Edge/Level Interrupt source selection..

P25

Bit 25: Edge/Level Interrupt source selection..

P26

Bit 26: Edge/Level Interrupt source selection..

P27

Bit 27: Edge/Level Interrupt source selection..

P28

Bit 28: Edge/Level Interrupt source selection..

P29

Bit 29: Edge/Level Interrupt source selection..

P30

Bit 30: Edge/Level Interrupt source selection..

P31

Bit 31: Edge/Level Interrupt source selection..

FELLSR

Falling Edge/Low Level Select Register

Offset: 0xd0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Falling Edge/Low Level Interrupt Selection..

P1

Bit 1: Falling Edge/Low Level Interrupt Selection..

P2

Bit 2: Falling Edge/Low Level Interrupt Selection..

P3

Bit 3: Falling Edge/Low Level Interrupt Selection..

P4

Bit 4: Falling Edge/Low Level Interrupt Selection..

P5

Bit 5: Falling Edge/Low Level Interrupt Selection..

P6

Bit 6: Falling Edge/Low Level Interrupt Selection..

P7

Bit 7: Falling Edge/Low Level Interrupt Selection..

P8

Bit 8: Falling Edge/Low Level Interrupt Selection..

P9

Bit 9: Falling Edge/Low Level Interrupt Selection..

P10

Bit 10: Falling Edge/Low Level Interrupt Selection..

P11

Bit 11: Falling Edge/Low Level Interrupt Selection..

P12

Bit 12: Falling Edge/Low Level Interrupt Selection..

P13

Bit 13: Falling Edge/Low Level Interrupt Selection..

P14

Bit 14: Falling Edge/Low Level Interrupt Selection..

P15

Bit 15: Falling Edge/Low Level Interrupt Selection..

P16

Bit 16: Falling Edge/Low Level Interrupt Selection..

P17

Bit 17: Falling Edge/Low Level Interrupt Selection..

P18

Bit 18: Falling Edge/Low Level Interrupt Selection..

P19

Bit 19: Falling Edge/Low Level Interrupt Selection..

P20

Bit 20: Falling Edge/Low Level Interrupt Selection..

P21

Bit 21: Falling Edge/Low Level Interrupt Selection..

P22

Bit 22: Falling Edge/Low Level Interrupt Selection..

P23

Bit 23: Falling Edge/Low Level Interrupt Selection..

P24

Bit 24: Falling Edge/Low Level Interrupt Selection..

P25

Bit 25: Falling Edge/Low Level Interrupt Selection..

P26

Bit 26: Falling Edge/Low Level Interrupt Selection..

P27

Bit 27: Falling Edge/Low Level Interrupt Selection..

P28

Bit 28: Falling Edge/Low Level Interrupt Selection..

P29

Bit 29: Falling Edge/Low Level Interrupt Selection..

P30

Bit 30: Falling Edge/Low Level Interrupt Selection..

P31

Bit 31: Falling Edge/Low Level Interrupt Selection..

REHLSR

Rising Edge/ High Level Select Register

Offset: 0xd4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Rising Edge /High Level Interrupt Selection..

P1

Bit 1: Rising Edge /High Level Interrupt Selection..

P2

Bit 2: Rising Edge /High Level Interrupt Selection..

P3

Bit 3: Rising Edge /High Level Interrupt Selection..

P4

Bit 4: Rising Edge /High Level Interrupt Selection..

P5

Bit 5: Rising Edge /High Level Interrupt Selection..

P6

Bit 6: Rising Edge /High Level Interrupt Selection..

P7

Bit 7: Rising Edge /High Level Interrupt Selection..

P8

Bit 8: Rising Edge /High Level Interrupt Selection..

P9

Bit 9: Rising Edge /High Level Interrupt Selection..

P10

Bit 10: Rising Edge /High Level Interrupt Selection..

P11

Bit 11: Rising Edge /High Level Interrupt Selection..

P12

Bit 12: Rising Edge /High Level Interrupt Selection..

P13

Bit 13: Rising Edge /High Level Interrupt Selection..

P14

Bit 14: Rising Edge /High Level Interrupt Selection..

P15

Bit 15: Rising Edge /High Level Interrupt Selection..

P16

Bit 16: Rising Edge /High Level Interrupt Selection..

P17

Bit 17: Rising Edge /High Level Interrupt Selection..

P18

Bit 18: Rising Edge /High Level Interrupt Selection..

P19

Bit 19: Rising Edge /High Level Interrupt Selection..

P20

Bit 20: Rising Edge /High Level Interrupt Selection..

P21

Bit 21: Rising Edge /High Level Interrupt Selection..

P22

Bit 22: Rising Edge /High Level Interrupt Selection..

P23

Bit 23: Rising Edge /High Level Interrupt Selection..

P24

Bit 24: Rising Edge /High Level Interrupt Selection..

P25

Bit 25: Rising Edge /High Level Interrupt Selection..

P26

Bit 26: Rising Edge /High Level Interrupt Selection..

P27

Bit 27: Rising Edge /High Level Interrupt Selection..

P28

Bit 28: Rising Edge /High Level Interrupt Selection..

P29

Bit 29: Rising Edge /High Level Interrupt Selection..

P30

Bit 30: Rising Edge /High Level Interrupt Selection..

P31

Bit 31: Rising Edge /High Level Interrupt Selection..

FRLHSR

Fall/Rise - Low/High Status Register

Offset: 0xd8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge /Level Interrupt Source Selection..

P1

Bit 1: Edge /Level Interrupt Source Selection..

P2

Bit 2: Edge /Level Interrupt Source Selection..

P3

Bit 3: Edge /Level Interrupt Source Selection..

P4

Bit 4: Edge /Level Interrupt Source Selection..

P5

Bit 5: Edge /Level Interrupt Source Selection..

P6

Bit 6: Edge /Level Interrupt Source Selection..

P7

Bit 7: Edge /Level Interrupt Source Selection..

P8

Bit 8: Edge /Level Interrupt Source Selection..

P9

Bit 9: Edge /Level Interrupt Source Selection..

P10

Bit 10: Edge /Level Interrupt Source Selection..

P11

Bit 11: Edge /Level Interrupt Source Selection..

P12

Bit 12: Edge /Level Interrupt Source Selection..

P13

Bit 13: Edge /Level Interrupt Source Selection..

P14

Bit 14: Edge /Level Interrupt Source Selection..

P15

Bit 15: Edge /Level Interrupt Source Selection..

P16

Bit 16: Edge /Level Interrupt Source Selection..

P17

Bit 17: Edge /Level Interrupt Source Selection..

P18

Bit 18: Edge /Level Interrupt Source Selection..

P19

Bit 19: Edge /Level Interrupt Source Selection..

P20

Bit 20: Edge /Level Interrupt Source Selection..

P21

Bit 21: Edge /Level Interrupt Source Selection..

P22

Bit 22: Edge /Level Interrupt Source Selection..

P23

Bit 23: Edge /Level Interrupt Source Selection..

P24

Bit 24: Edge /Level Interrupt Source Selection..

P25

Bit 25: Edge /Level Interrupt Source Selection..

P26

Bit 26: Edge /Level Interrupt Source Selection..

P27

Bit 27: Edge /Level Interrupt Source Selection..

P28

Bit 28: Edge /Level Interrupt Source Selection..

P29

Bit 29: Edge /Level Interrupt Source Selection..

P30

Bit 30: Edge /Level Interrupt Source Selection..

P31

Bit 31: Edge /Level Interrupt Source Selection..

LOCKSR

Lock Status

Offset: 0xe0, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Lock Status..

P1

Bit 1: Lock Status..

P2

Bit 2: Lock Status..

P3

Bit 3: Lock Status..

P4

Bit 4: Lock Status..

P5

Bit 5: Lock Status..

P6

Bit 6: Lock Status..

P7

Bit 7: Lock Status..

P8

Bit 8: Lock Status..

P9

Bit 9: Lock Status..

P10

Bit 10: Lock Status..

P11

Bit 11: Lock Status..

P12

Bit 12: Lock Status..

P13

Bit 13: Lock Status..

P14

Bit 14: Lock Status..

P15

Bit 15: Lock Status..

P16

Bit 16: Lock Status..

P17

Bit 17: Lock Status..

P18

Bit 18: Lock Status..

P19

Bit 19: Lock Status..

P20

Bit 20: Lock Status..

P21

Bit 21: Lock Status..

P22

Bit 22: Lock Status..

P23

Bit 23: Lock Status..

P24

Bit 24: Lock Status..

P25

Bit 25: Lock Status..

P26

Bit 26: Lock Status..

P27

Bit 27: Lock Status..

P28

Bit 28: Lock Status..

P29

Bit 29: Lock Status..

P30

Bit 30: Lock Status..

P31

Bit 31: Lock Status..

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

PIOC

0x400e1200: Parallel Input/Output Controller C

450/1285 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PER
0x4 PDR
0x8 PSR
0x10 OER
0x14 ODR
0x18 OSR
0x20 IFER
0x24 IFDR
0x28 IFSR
0x30 SODR
0x34 CODR
0x38 ODSR
0x3c PDSR
0x40 IER
0x44 IDR
0x48 IMR
0x4c ISR
0x50 MDER
0x54 MDDR
0x58 MDSR
0x60 PUDR
0x64 PUER
0x68 PUSR
0x70 ABSR
0x80 SCIFSR
0x84 DIFSR
0x88 IFDGSR
0x8c SCDR
0xa0 OWER
0xa4 OWDR
0xa8 OWSR
0xb0 AIMER
0xb4 AIMDR
0xb8 AIMMR
0xc0 ESR
0xc4 LSR
0xc8 ELSR
0xd0 FELLSR
0xd4 REHLSR
0xd8 FRLHSR
0xe0 LOCKSR
0xe4 WPMR
0xe8 WPSR

PER

PIO Enable Register

Offset: 0x0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Enable.

P1

Bit 1: PIO Enable.

P2

Bit 2: PIO Enable.

P3

Bit 3: PIO Enable.

P4

Bit 4: PIO Enable.

P5

Bit 5: PIO Enable.

P6

Bit 6: PIO Enable.

P7

Bit 7: PIO Enable.

P8

Bit 8: PIO Enable.

P9

Bit 9: PIO Enable.

P10

Bit 10: PIO Enable.

P11

Bit 11: PIO Enable.

P12

Bit 12: PIO Enable.

P13

Bit 13: PIO Enable.

P14

Bit 14: PIO Enable.

P15

Bit 15: PIO Enable.

P16

Bit 16: PIO Enable.

P17

Bit 17: PIO Enable.

P18

Bit 18: PIO Enable.

P19

Bit 19: PIO Enable.

P20

Bit 20: PIO Enable.

P21

Bit 21: PIO Enable.

P22

Bit 22: PIO Enable.

P23

Bit 23: PIO Enable.

P24

Bit 24: PIO Enable.

P25

Bit 25: PIO Enable.

P26

Bit 26: PIO Enable.

P27

Bit 27: PIO Enable.

P28

Bit 28: PIO Enable.

P29

Bit 29: PIO Enable.

P30

Bit 30: PIO Enable.

P31

Bit 31: PIO Enable.

PDR

PIO Disable Register

Offset: 0x4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Disable.

P1

Bit 1: PIO Disable.

P2

Bit 2: PIO Disable.

P3

Bit 3: PIO Disable.

P4

Bit 4: PIO Disable.

P5

Bit 5: PIO Disable.

P6

Bit 6: PIO Disable.

P7

Bit 7: PIO Disable.

P8

Bit 8: PIO Disable.

P9

Bit 9: PIO Disable.

P10

Bit 10: PIO Disable.

P11

Bit 11: PIO Disable.

P12

Bit 12: PIO Disable.

P13

Bit 13: PIO Disable.

P14

Bit 14: PIO Disable.

P15

Bit 15: PIO Disable.

P16

Bit 16: PIO Disable.

P17

Bit 17: PIO Disable.

P18

Bit 18: PIO Disable.

P19

Bit 19: PIO Disable.

P20

Bit 20: PIO Disable.

P21

Bit 21: PIO Disable.

P22

Bit 22: PIO Disable.

P23

Bit 23: PIO Disable.

P24

Bit 24: PIO Disable.

P25

Bit 25: PIO Disable.

P26

Bit 26: PIO Disable.

P27

Bit 27: PIO Disable.

P28

Bit 28: PIO Disable.

P29

Bit 29: PIO Disable.

P30

Bit 30: PIO Disable.

P31

Bit 31: PIO Disable.

PSR

PIO Status Register

Offset: 0x8, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: PIO Status.

P1

Bit 1: PIO Status.

P2

Bit 2: PIO Status.

P3

Bit 3: PIO Status.

P4

Bit 4: PIO Status.

P5

Bit 5: PIO Status.

P6

Bit 6: PIO Status.

P7

Bit 7: PIO Status.

P8

Bit 8: PIO Status.

P9

Bit 9: PIO Status.

P10

Bit 10: PIO Status.

P11

Bit 11: PIO Status.

P12

Bit 12: PIO Status.

P13

Bit 13: PIO Status.

P14

Bit 14: PIO Status.

P15

Bit 15: PIO Status.

P16

Bit 16: PIO Status.

P17

Bit 17: PIO Status.

P18

Bit 18: PIO Status.

P19

Bit 19: PIO Status.

P20

Bit 20: PIO Status.

P21

Bit 21: PIO Status.

P22

Bit 22: PIO Status.

P23

Bit 23: PIO Status.

P24

Bit 24: PIO Status.

P25

Bit 25: PIO Status.

P26

Bit 26: PIO Status.

P27

Bit 27: PIO Status.

P28

Bit 28: PIO Status.

P29

Bit 29: PIO Status.

P30

Bit 30: PIO Status.

P31

Bit 31: PIO Status.

OER

Output Enable Register

Offset: 0x10, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Enable.

P1

Bit 1: Output Enable.

P2

Bit 2: Output Enable.

P3

Bit 3: Output Enable.

P4

Bit 4: Output Enable.

P5

Bit 5: Output Enable.

P6

Bit 6: Output Enable.

P7

Bit 7: Output Enable.

P8

Bit 8: Output Enable.

P9

Bit 9: Output Enable.

P10

Bit 10: Output Enable.

P11

Bit 11: Output Enable.

P12

Bit 12: Output Enable.

P13

Bit 13: Output Enable.

P14

Bit 14: Output Enable.

P15

Bit 15: Output Enable.

P16

Bit 16: Output Enable.

P17

Bit 17: Output Enable.

P18

Bit 18: Output Enable.

P19

Bit 19: Output Enable.

P20

Bit 20: Output Enable.

P21

Bit 21: Output Enable.

P22

Bit 22: Output Enable.

P23

Bit 23: Output Enable.

P24

Bit 24: Output Enable.

P25

Bit 25: Output Enable.

P26

Bit 26: Output Enable.

P27

Bit 27: Output Enable.

P28

Bit 28: Output Enable.

P29

Bit 29: Output Enable.

P30

Bit 30: Output Enable.

P31

Bit 31: Output Enable.

ODR

Output Disable Register

Offset: 0x14, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Disable.

P1

Bit 1: Output Disable.

P2

Bit 2: Output Disable.

P3

Bit 3: Output Disable.

P4

Bit 4: Output Disable.

P5

Bit 5: Output Disable.

P6

Bit 6: Output Disable.

P7

Bit 7: Output Disable.

P8

Bit 8: Output Disable.

P9

Bit 9: Output Disable.

P10

Bit 10: Output Disable.

P11

Bit 11: Output Disable.

P12

Bit 12: Output Disable.

P13

Bit 13: Output Disable.

P14

Bit 14: Output Disable.

P15

Bit 15: Output Disable.

P16

Bit 16: Output Disable.

P17

Bit 17: Output Disable.

P18

Bit 18: Output Disable.

P19

Bit 19: Output Disable.

P20

Bit 20: Output Disable.

P21

Bit 21: Output Disable.

P22

Bit 22: Output Disable.

P23

Bit 23: Output Disable.

P24

Bit 24: Output Disable.

P25

Bit 25: Output Disable.

P26

Bit 26: Output Disable.

P27

Bit 27: Output Disable.

P28

Bit 28: Output Disable.

P29

Bit 29: Output Disable.

P30

Bit 30: Output Disable.

P31

Bit 31: Output Disable.

OSR

Output Status Register

Offset: 0x18, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Status.

P1

Bit 1: Output Status.

P2

Bit 2: Output Status.

P3

Bit 3: Output Status.

P4

Bit 4: Output Status.

P5

Bit 5: Output Status.

P6

Bit 6: Output Status.

P7

Bit 7: Output Status.

P8

Bit 8: Output Status.

P9

Bit 9: Output Status.

P10

Bit 10: Output Status.

P11

Bit 11: Output Status.

P12

Bit 12: Output Status.

P13

Bit 13: Output Status.

P14

Bit 14: Output Status.

P15

Bit 15: Output Status.

P16

Bit 16: Output Status.

P17

Bit 17: Output Status.

P18

Bit 18: Output Status.

P19

Bit 19: Output Status.

P20

Bit 20: Output Status.

P21

Bit 21: Output Status.

P22

Bit 22: Output Status.

P23

Bit 23: Output Status.

P24

Bit 24: Output Status.

P25

Bit 25: Output Status.

P26

Bit 26: Output Status.

P27

Bit 27: Output Status.

P28

Bit 28: Output Status.

P29

Bit 29: Output Status.

P30

Bit 30: Output Status.

P31

Bit 31: Output Status.

IFER

Glitch Input Filter Enable Register

Offset: 0x20, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Enable.

P1

Bit 1: Input Filter Enable.

P2

Bit 2: Input Filter Enable.

P3

Bit 3: Input Filter Enable.

P4

Bit 4: Input Filter Enable.

P5

Bit 5: Input Filter Enable.

P6

Bit 6: Input Filter Enable.

P7

Bit 7: Input Filter Enable.

P8

Bit 8: Input Filter Enable.

P9

Bit 9: Input Filter Enable.

P10

Bit 10: Input Filter Enable.

P11

Bit 11: Input Filter Enable.

P12

Bit 12: Input Filter Enable.

P13

Bit 13: Input Filter Enable.

P14

Bit 14: Input Filter Enable.

P15

Bit 15: Input Filter Enable.

P16

Bit 16: Input Filter Enable.

P17

Bit 17: Input Filter Enable.

P18

Bit 18: Input Filter Enable.

P19

Bit 19: Input Filter Enable.

P20

Bit 20: Input Filter Enable.

P21

Bit 21: Input Filter Enable.

P22

Bit 22: Input Filter Enable.

P23

Bit 23: Input Filter Enable.

P24

Bit 24: Input Filter Enable.

P25

Bit 25: Input Filter Enable.

P26

Bit 26: Input Filter Enable.

P27

Bit 27: Input Filter Enable.

P28

Bit 28: Input Filter Enable.

P29

Bit 29: Input Filter Enable.

P30

Bit 30: Input Filter Enable.

P31

Bit 31: Input Filter Enable.

IFDR

Glitch Input Filter Disable Register

Offset: 0x24, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Disable.

P1

Bit 1: Input Filter Disable.

P2

Bit 2: Input Filter Disable.

P3

Bit 3: Input Filter Disable.

P4

Bit 4: Input Filter Disable.

P5

Bit 5: Input Filter Disable.

P6

Bit 6: Input Filter Disable.

P7

Bit 7: Input Filter Disable.

P8

Bit 8: Input Filter Disable.

P9

Bit 9: Input Filter Disable.

P10

Bit 10: Input Filter Disable.

P11

Bit 11: Input Filter Disable.

P12

Bit 12: Input Filter Disable.

P13

Bit 13: Input Filter Disable.

P14

Bit 14: Input Filter Disable.

P15

Bit 15: Input Filter Disable.

P16

Bit 16: Input Filter Disable.

P17

Bit 17: Input Filter Disable.

P18

Bit 18: Input Filter Disable.

P19

Bit 19: Input Filter Disable.

P20

Bit 20: Input Filter Disable.

P21

Bit 21: Input Filter Disable.

P22

Bit 22: Input Filter Disable.

P23

Bit 23: Input Filter Disable.

P24

Bit 24: Input Filter Disable.

P25

Bit 25: Input Filter Disable.

P26

Bit 26: Input Filter Disable.

P27

Bit 27: Input Filter Disable.

P28

Bit 28: Input Filter Disable.

P29

Bit 29: Input Filter Disable.

P30

Bit 30: Input Filter Disable.

P31

Bit 31: Input Filter Disable.

IFSR

Glitch Input Filter Status Register

Offset: 0x28, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Filer Status.

P1

Bit 1: Input Filer Status.

P2

Bit 2: Input Filer Status.

P3

Bit 3: Input Filer Status.

P4

Bit 4: Input Filer Status.

P5

Bit 5: Input Filer Status.

P6

Bit 6: Input Filer Status.

P7

Bit 7: Input Filer Status.

P8

Bit 8: Input Filer Status.

P9

Bit 9: Input Filer Status.

P10

Bit 10: Input Filer Status.

P11

Bit 11: Input Filer Status.

P12

Bit 12: Input Filer Status.

P13

Bit 13: Input Filer Status.

P14

Bit 14: Input Filer Status.

P15

Bit 15: Input Filer Status.

P16

Bit 16: Input Filer Status.

P17

Bit 17: Input Filer Status.

P18

Bit 18: Input Filer Status.

P19

Bit 19: Input Filer Status.

P20

Bit 20: Input Filer Status.

P21

Bit 21: Input Filer Status.

P22

Bit 22: Input Filer Status.

P23

Bit 23: Input Filer Status.

P24

Bit 24: Input Filer Status.

P25

Bit 25: Input Filer Status.

P26

Bit 26: Input Filer Status.

P27

Bit 27: Input Filer Status.

P28

Bit 28: Input Filer Status.

P29

Bit 29: Input Filer Status.

P30

Bit 30: Input Filer Status.

P31

Bit 31: Input Filer Status.

SODR

Set Output Data Register

Offset: 0x30, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Set Output Data.

P1

Bit 1: Set Output Data.

P2

Bit 2: Set Output Data.

P3

Bit 3: Set Output Data.

P4

Bit 4: Set Output Data.

P5

Bit 5: Set Output Data.

P6

Bit 6: Set Output Data.

P7

Bit 7: Set Output Data.

P8

Bit 8: Set Output Data.

P9

Bit 9: Set Output Data.

P10

Bit 10: Set Output Data.

P11

Bit 11: Set Output Data.

P12

Bit 12: Set Output Data.

P13

Bit 13: Set Output Data.

P14

Bit 14: Set Output Data.

P15

Bit 15: Set Output Data.

P16

Bit 16: Set Output Data.

P17

Bit 17: Set Output Data.

P18

Bit 18: Set Output Data.

P19

Bit 19: Set Output Data.

P20

Bit 20: Set Output Data.

P21

Bit 21: Set Output Data.

P22

Bit 22: Set Output Data.

P23

Bit 23: Set Output Data.

P24

Bit 24: Set Output Data.

P25

Bit 25: Set Output Data.

P26

Bit 26: Set Output Data.

P27

Bit 27: Set Output Data.

P28

Bit 28: Set Output Data.

P29

Bit 29: Set Output Data.

P30

Bit 30: Set Output Data.

P31

Bit 31: Set Output Data.

CODR

Clear Output Data Register

Offset: 0x34, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Clear Output Data.

P1

Bit 1: Clear Output Data.

P2

Bit 2: Clear Output Data.

P3

Bit 3: Clear Output Data.

P4

Bit 4: Clear Output Data.

P5

Bit 5: Clear Output Data.

P6

Bit 6: Clear Output Data.

P7

Bit 7: Clear Output Data.

P8

Bit 8: Clear Output Data.

P9

Bit 9: Clear Output Data.

P10

Bit 10: Clear Output Data.

P11

Bit 11: Clear Output Data.

P12

Bit 12: Clear Output Data.

P13

Bit 13: Clear Output Data.

P14

Bit 14: Clear Output Data.

P15

Bit 15: Clear Output Data.

P16

Bit 16: Clear Output Data.

P17

Bit 17: Clear Output Data.

P18

Bit 18: Clear Output Data.

P19

Bit 19: Clear Output Data.

P20

Bit 20: Clear Output Data.

P21

Bit 21: Clear Output Data.

P22

Bit 22: Clear Output Data.

P23

Bit 23: Clear Output Data.

P24

Bit 24: Clear Output Data.

P25

Bit 25: Clear Output Data.

P26

Bit 26: Clear Output Data.

P27

Bit 27: Clear Output Data.

P28

Bit 28: Clear Output Data.

P29

Bit 29: Clear Output Data.

P30

Bit 30: Clear Output Data.

P31

Bit 31: Clear Output Data.

ODSR

Output Data Status Register

Offset: 0x38, reset: None, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

PDSR

Pin Data Status Register

Offset: 0x3c, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

IER

Interrupt Enable Register

Offset: 0x40, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Enable.

P1

Bit 1: Input Change Interrupt Enable.

P2

Bit 2: Input Change Interrupt Enable.

P3

Bit 3: Input Change Interrupt Enable.

P4

Bit 4: Input Change Interrupt Enable.

P5

Bit 5: Input Change Interrupt Enable.

P6

Bit 6: Input Change Interrupt Enable.

P7

Bit 7: Input Change Interrupt Enable.

P8

Bit 8: Input Change Interrupt Enable.

P9

Bit 9: Input Change Interrupt Enable.

P10

Bit 10: Input Change Interrupt Enable.

P11

Bit 11: Input Change Interrupt Enable.

P12

Bit 12: Input Change Interrupt Enable.

P13

Bit 13: Input Change Interrupt Enable.

P14

Bit 14: Input Change Interrupt Enable.

P15

Bit 15: Input Change Interrupt Enable.

P16

Bit 16: Input Change Interrupt Enable.

P17

Bit 17: Input Change Interrupt Enable.

P18

Bit 18: Input Change Interrupt Enable.

P19

Bit 19: Input Change Interrupt Enable.

P20

Bit 20: Input Change Interrupt Enable.

P21

Bit 21: Input Change Interrupt Enable.

P22

Bit 22: Input Change Interrupt Enable.

P23

Bit 23: Input Change Interrupt Enable.

P24

Bit 24: Input Change Interrupt Enable.

P25

Bit 25: Input Change Interrupt Enable.

P26

Bit 26: Input Change Interrupt Enable.

P27

Bit 27: Input Change Interrupt Enable.

P28

Bit 28: Input Change Interrupt Enable.

P29

Bit 29: Input Change Interrupt Enable.

P30

Bit 30: Input Change Interrupt Enable.

P31

Bit 31: Input Change Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x44, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Disable.

P1

Bit 1: Input Change Interrupt Disable.

P2

Bit 2: Input Change Interrupt Disable.

P3

Bit 3: Input Change Interrupt Disable.

P4

Bit 4: Input Change Interrupt Disable.

P5

Bit 5: Input Change Interrupt Disable.

P6

Bit 6: Input Change Interrupt Disable.

P7

Bit 7: Input Change Interrupt Disable.

P8

Bit 8: Input Change Interrupt Disable.

P9

Bit 9: Input Change Interrupt Disable.

P10

Bit 10: Input Change Interrupt Disable.

P11

Bit 11: Input Change Interrupt Disable.

P12

Bit 12: Input Change Interrupt Disable.

P13

Bit 13: Input Change Interrupt Disable.

P14

Bit 14: Input Change Interrupt Disable.

P15

Bit 15: Input Change Interrupt Disable.

P16

Bit 16: Input Change Interrupt Disable.

P17

Bit 17: Input Change Interrupt Disable.

P18

Bit 18: Input Change Interrupt Disable.

P19

Bit 19: Input Change Interrupt Disable.

P20

Bit 20: Input Change Interrupt Disable.

P21

Bit 21: Input Change Interrupt Disable.

P22

Bit 22: Input Change Interrupt Disable.

P23

Bit 23: Input Change Interrupt Disable.

P24

Bit 24: Input Change Interrupt Disable.

P25

Bit 25: Input Change Interrupt Disable.

P26

Bit 26: Input Change Interrupt Disable.

P27

Bit 27: Input Change Interrupt Disable.

P28

Bit 28: Input Change Interrupt Disable.

P29

Bit 29: Input Change Interrupt Disable.

P30

Bit 30: Input Change Interrupt Disable.

P31

Bit 31: Input Change Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x48, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Mask.

P1

Bit 1: Input Change Interrupt Mask.

P2

Bit 2: Input Change Interrupt Mask.

P3

Bit 3: Input Change Interrupt Mask.

P4

Bit 4: Input Change Interrupt Mask.

P5

Bit 5: Input Change Interrupt Mask.

P6

Bit 6: Input Change Interrupt Mask.

P7

Bit 7: Input Change Interrupt Mask.

P8

Bit 8: Input Change Interrupt Mask.

P9

Bit 9: Input Change Interrupt Mask.

P10

Bit 10: Input Change Interrupt Mask.

P11

Bit 11: Input Change Interrupt Mask.

P12

Bit 12: Input Change Interrupt Mask.

P13

Bit 13: Input Change Interrupt Mask.

P14

Bit 14: Input Change Interrupt Mask.

P15

Bit 15: Input Change Interrupt Mask.

P16

Bit 16: Input Change Interrupt Mask.

P17

Bit 17: Input Change Interrupt Mask.

P18

Bit 18: Input Change Interrupt Mask.

P19

Bit 19: Input Change Interrupt Mask.

P20

Bit 20: Input Change Interrupt Mask.

P21

Bit 21: Input Change Interrupt Mask.

P22

Bit 22: Input Change Interrupt Mask.

P23

Bit 23: Input Change Interrupt Mask.

P24

Bit 24: Input Change Interrupt Mask.

P25

Bit 25: Input Change Interrupt Mask.

P26

Bit 26: Input Change Interrupt Mask.

P27

Bit 27: Input Change Interrupt Mask.

P28

Bit 28: Input Change Interrupt Mask.

P29

Bit 29: Input Change Interrupt Mask.

P30

Bit 30: Input Change Interrupt Mask.

P31

Bit 31: Input Change Interrupt Mask.

ISR

Interrupt Status Register

Offset: 0x4c, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Status.

P1

Bit 1: Input Change Interrupt Status.

P2

Bit 2: Input Change Interrupt Status.

P3

Bit 3: Input Change Interrupt Status.

P4

Bit 4: Input Change Interrupt Status.

P5

Bit 5: Input Change Interrupt Status.

P6

Bit 6: Input Change Interrupt Status.

P7

Bit 7: Input Change Interrupt Status.

P8

Bit 8: Input Change Interrupt Status.

P9

Bit 9: Input Change Interrupt Status.

P10

Bit 10: Input Change Interrupt Status.

P11

Bit 11: Input Change Interrupt Status.

P12

Bit 12: Input Change Interrupt Status.

P13

Bit 13: Input Change Interrupt Status.

P14

Bit 14: Input Change Interrupt Status.

P15

Bit 15: Input Change Interrupt Status.

P16

Bit 16: Input Change Interrupt Status.

P17

Bit 17: Input Change Interrupt Status.

P18

Bit 18: Input Change Interrupt Status.

P19

Bit 19: Input Change Interrupt Status.

P20

Bit 20: Input Change Interrupt Status.

P21

Bit 21: Input Change Interrupt Status.

P22

Bit 22: Input Change Interrupt Status.

P23

Bit 23: Input Change Interrupt Status.

P24

Bit 24: Input Change Interrupt Status.

P25

Bit 25: Input Change Interrupt Status.

P26

Bit 26: Input Change Interrupt Status.

P27

Bit 27: Input Change Interrupt Status.

P28

Bit 28: Input Change Interrupt Status.

P29

Bit 29: Input Change Interrupt Status.

P30

Bit 30: Input Change Interrupt Status.

P31

Bit 31: Input Change Interrupt Status.

MDER

Multi-driver Enable Register

Offset: 0x50, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Enable..

P1

Bit 1: Multi Drive Enable..

P2

Bit 2: Multi Drive Enable..

P3

Bit 3: Multi Drive Enable..

P4

Bit 4: Multi Drive Enable..

P5

Bit 5: Multi Drive Enable..

P6

Bit 6: Multi Drive Enable..

P7

Bit 7: Multi Drive Enable..

P8

Bit 8: Multi Drive Enable..

P9

Bit 9: Multi Drive Enable..

P10

Bit 10: Multi Drive Enable..

P11

Bit 11: Multi Drive Enable..

P12

Bit 12: Multi Drive Enable..

P13

Bit 13: Multi Drive Enable..

P14

Bit 14: Multi Drive Enable..

P15

Bit 15: Multi Drive Enable..

P16

Bit 16: Multi Drive Enable..

P17

Bit 17: Multi Drive Enable..

P18

Bit 18: Multi Drive Enable..

P19

Bit 19: Multi Drive Enable..

P20

Bit 20: Multi Drive Enable..

P21

Bit 21: Multi Drive Enable..

P22

Bit 22: Multi Drive Enable..

P23

Bit 23: Multi Drive Enable..

P24

Bit 24: Multi Drive Enable..

P25

Bit 25: Multi Drive Enable..

P26

Bit 26: Multi Drive Enable..

P27

Bit 27: Multi Drive Enable..

P28

Bit 28: Multi Drive Enable..

P29

Bit 29: Multi Drive Enable..

P30

Bit 30: Multi Drive Enable..

P31

Bit 31: Multi Drive Enable..

MDDR

Multi-driver Disable Register

Offset: 0x54, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Disable..

P1

Bit 1: Multi Drive Disable..

P2

Bit 2: Multi Drive Disable..

P3

Bit 3: Multi Drive Disable..

P4

Bit 4: Multi Drive Disable..

P5

Bit 5: Multi Drive Disable..

P6

Bit 6: Multi Drive Disable..

P7

Bit 7: Multi Drive Disable..

P8

Bit 8: Multi Drive Disable..

P9

Bit 9: Multi Drive Disable..

P10

Bit 10: Multi Drive Disable..

P11

Bit 11: Multi Drive Disable..

P12

Bit 12: Multi Drive Disable..

P13

Bit 13: Multi Drive Disable..

P14

Bit 14: Multi Drive Disable..

P15

Bit 15: Multi Drive Disable..

P16

Bit 16: Multi Drive Disable..

P17

Bit 17: Multi Drive Disable..

P18

Bit 18: Multi Drive Disable..

P19

Bit 19: Multi Drive Disable..

P20

Bit 20: Multi Drive Disable..

P21

Bit 21: Multi Drive Disable..

P22

Bit 22: Multi Drive Disable..

P23

Bit 23: Multi Drive Disable..

P24

Bit 24: Multi Drive Disable..

P25

Bit 25: Multi Drive Disable..

P26

Bit 26: Multi Drive Disable..

P27

Bit 27: Multi Drive Disable..

P28

Bit 28: Multi Drive Disable..

P29

Bit 29: Multi Drive Disable..

P30

Bit 30: Multi Drive Disable..

P31

Bit 31: Multi Drive Disable..

MDSR

Multi-driver Status Register

Offset: 0x58, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Multi Drive Status..

P1

Bit 1: Multi Drive Status..

P2

Bit 2: Multi Drive Status..

P3

Bit 3: Multi Drive Status..

P4

Bit 4: Multi Drive Status..

P5

Bit 5: Multi Drive Status..

P6

Bit 6: Multi Drive Status..

P7

Bit 7: Multi Drive Status..

P8

Bit 8: Multi Drive Status..

P9

Bit 9: Multi Drive Status..

P10

Bit 10: Multi Drive Status..

P11

Bit 11: Multi Drive Status..

P12

Bit 12: Multi Drive Status..

P13

Bit 13: Multi Drive Status..

P14

Bit 14: Multi Drive Status..

P15

Bit 15: Multi Drive Status..

P16

Bit 16: Multi Drive Status..

P17

Bit 17: Multi Drive Status..

P18

Bit 18: Multi Drive Status..

P19

Bit 19: Multi Drive Status..

P20

Bit 20: Multi Drive Status..

P21

Bit 21: Multi Drive Status..

P22

Bit 22: Multi Drive Status..

P23

Bit 23: Multi Drive Status..

P24

Bit 24: Multi Drive Status..

P25

Bit 25: Multi Drive Status..

P26

Bit 26: Multi Drive Status..

P27

Bit 27: Multi Drive Status..

P28

Bit 28: Multi Drive Status..

P29

Bit 29: Multi Drive Status..

P30

Bit 30: Multi Drive Status..

P31

Bit 31: Multi Drive Status..

PUDR

Pull-up Disable Register

Offset: 0x60, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Disable..

P1

Bit 1: Pull Up Disable..

P2

Bit 2: Pull Up Disable..

P3

Bit 3: Pull Up Disable..

P4

Bit 4: Pull Up Disable..

P5

Bit 5: Pull Up Disable..

P6

Bit 6: Pull Up Disable..

P7

Bit 7: Pull Up Disable..

P8

Bit 8: Pull Up Disable..

P9

Bit 9: Pull Up Disable..

P10

Bit 10: Pull Up Disable..

P11

Bit 11: Pull Up Disable..

P12

Bit 12: Pull Up Disable..

P13

Bit 13: Pull Up Disable..

P14

Bit 14: Pull Up Disable..

P15

Bit 15: Pull Up Disable..

P16

Bit 16: Pull Up Disable..

P17

Bit 17: Pull Up Disable..

P18

Bit 18: Pull Up Disable..

P19

Bit 19: Pull Up Disable..

P20

Bit 20: Pull Up Disable..

P21

Bit 21: Pull Up Disable..

P22

Bit 22: Pull Up Disable..

P23

Bit 23: Pull Up Disable..

P24

Bit 24: Pull Up Disable..

P25

Bit 25: Pull Up Disable..

P26

Bit 26: Pull Up Disable..

P27

Bit 27: Pull Up Disable..

P28

Bit 28: Pull Up Disable..

P29

Bit 29: Pull Up Disable..

P30

Bit 30: Pull Up Disable..

P31

Bit 31: Pull Up Disable..

PUER

Pull-up Enable Register

Offset: 0x64, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Enable..

P1

Bit 1: Pull Up Enable..

P2

Bit 2: Pull Up Enable..

P3

Bit 3: Pull Up Enable..

P4

Bit 4: Pull Up Enable..

P5

Bit 5: Pull Up Enable..

P6

Bit 6: Pull Up Enable..

P7

Bit 7: Pull Up Enable..

P8

Bit 8: Pull Up Enable..

P9

Bit 9: Pull Up Enable..

P10

Bit 10: Pull Up Enable..

P11

Bit 11: Pull Up Enable..

P12

Bit 12: Pull Up Enable..

P13

Bit 13: Pull Up Enable..

P14

Bit 14: Pull Up Enable..

P15

Bit 15: Pull Up Enable..

P16

Bit 16: Pull Up Enable..

P17

Bit 17: Pull Up Enable..

P18

Bit 18: Pull Up Enable..

P19

Bit 19: Pull Up Enable..

P20

Bit 20: Pull Up Enable..

P21

Bit 21: Pull Up Enable..

P22

Bit 22: Pull Up Enable..

P23

Bit 23: Pull Up Enable..

P24

Bit 24: Pull Up Enable..

P25

Bit 25: Pull Up Enable..

P26

Bit 26: Pull Up Enable..

P27

Bit 27: Pull Up Enable..

P28

Bit 28: Pull Up Enable..

P29

Bit 29: Pull Up Enable..

P30

Bit 30: Pull Up Enable..

P31

Bit 31: Pull Up Enable..

PUSR

Pad Pull-up Status Register

Offset: 0x68, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Pull Up Status..

P1

Bit 1: Pull Up Status..

P2

Bit 2: Pull Up Status..

P3

Bit 3: Pull Up Status..

P4

Bit 4: Pull Up Status..

P5

Bit 5: Pull Up Status..

P6

Bit 6: Pull Up Status..

P7

Bit 7: Pull Up Status..

P8

Bit 8: Pull Up Status..

P9

Bit 9: Pull Up Status..

P10

Bit 10: Pull Up Status..

P11

Bit 11: Pull Up Status..

P12

Bit 12: Pull Up Status..

P13

Bit 13: Pull Up Status..

P14

Bit 14: Pull Up Status..

P15

Bit 15: Pull Up Status..

P16

Bit 16: Pull Up Status..

P17

Bit 17: Pull Up Status..

P18

Bit 18: Pull Up Status..

P19

Bit 19: Pull Up Status..

P20

Bit 20: Pull Up Status..

P21

Bit 21: Pull Up Status..

P22

Bit 22: Pull Up Status..

P23

Bit 23: Pull Up Status..

P24

Bit 24: Pull Up Status..

P25

Bit 25: Pull Up Status..

P26

Bit 26: Pull Up Status..

P27

Bit 27: Pull Up Status..

P28

Bit 28: Pull Up Status..

P29

Bit 29: Pull Up Status..

P30

Bit 30: Pull Up Status..

P31

Bit 31: Pull Up Status..

ABSR

Peripheral AB Select Register

Offset: 0x70, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Peripheral A Select..

P1

Bit 1: Peripheral A Select..

P2

Bit 2: Peripheral A Select..

P3

Bit 3: Peripheral A Select..

P4

Bit 4: Peripheral A Select..

P5

Bit 5: Peripheral A Select..

P6

Bit 6: Peripheral A Select..

P7

Bit 7: Peripheral A Select..

P8

Bit 8: Peripheral A Select..

P9

Bit 9: Peripheral A Select..

P10

Bit 10: Peripheral A Select..

P11

Bit 11: Peripheral A Select..

P12

Bit 12: Peripheral A Select..

P13

Bit 13: Peripheral A Select..

P14

Bit 14: Peripheral A Select..

P15

Bit 15: Peripheral A Select..

P16

Bit 16: Peripheral A Select..

P17

Bit 17: Peripheral A Select..

P18

Bit 18: Peripheral A Select..

P19

Bit 19: Peripheral A Select..

P20

Bit 20: Peripheral A Select..

P21

Bit 21: Peripheral A Select..

P22

Bit 22: Peripheral A Select..

P23

Bit 23: Peripheral A Select..

P24

Bit 24: Peripheral A Select..

P25

Bit 25: Peripheral A Select..

P26

Bit 26: Peripheral A Select..

P27

Bit 27: Peripheral A Select..

P28

Bit 28: Peripheral A Select..

P29

Bit 29: Peripheral A Select..

P30

Bit 30: Peripheral A Select..

P31

Bit 31: Peripheral A Select..

SCIFSR

System Clock Glitch Input Filter Select Register

Offset: 0x80, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: System Clock Glitch Filtering Select..

P1

Bit 1: System Clock Glitch Filtering Select..

P2

Bit 2: System Clock Glitch Filtering Select..

P3

Bit 3: System Clock Glitch Filtering Select..

P4

Bit 4: System Clock Glitch Filtering Select..

P5

Bit 5: System Clock Glitch Filtering Select..

P6

Bit 6: System Clock Glitch Filtering Select..

P7

Bit 7: System Clock Glitch Filtering Select..

P8

Bit 8: System Clock Glitch Filtering Select..

P9

Bit 9: System Clock Glitch Filtering Select..

P10

Bit 10: System Clock Glitch Filtering Select..

P11

Bit 11: System Clock Glitch Filtering Select..

P12

Bit 12: System Clock Glitch Filtering Select..

P13

Bit 13: System Clock Glitch Filtering Select..

P14

Bit 14: System Clock Glitch Filtering Select..

P15

Bit 15: System Clock Glitch Filtering Select..

P16

Bit 16: System Clock Glitch Filtering Select..

P17

Bit 17: System Clock Glitch Filtering Select..

P18

Bit 18: System Clock Glitch Filtering Select..

P19

Bit 19: System Clock Glitch Filtering Select..

P20

Bit 20: System Clock Glitch Filtering Select..

P21

Bit 21: System Clock Glitch Filtering Select..

P22

Bit 22: System Clock Glitch Filtering Select..

P23

Bit 23: System Clock Glitch Filtering Select..

P24

Bit 24: System Clock Glitch Filtering Select..

P25

Bit 25: System Clock Glitch Filtering Select..

P26

Bit 26: System Clock Glitch Filtering Select..

P27

Bit 27: System Clock Glitch Filtering Select..

P28

Bit 28: System Clock Glitch Filtering Select..

P29

Bit 29: System Clock Glitch Filtering Select..

P30

Bit 30: System Clock Glitch Filtering Select..

P31

Bit 31: System Clock Glitch Filtering Select..

DIFSR

Debouncing Input Filter Select Register

Offset: 0x84, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Debouncing Filtering Select..

P1

Bit 1: Debouncing Filtering Select..

P2

Bit 2: Debouncing Filtering Select..

P3

Bit 3: Debouncing Filtering Select..

P4

Bit 4: Debouncing Filtering Select..

P5

Bit 5: Debouncing Filtering Select..

P6

Bit 6: Debouncing Filtering Select..

P7

Bit 7: Debouncing Filtering Select..

P8

Bit 8: Debouncing Filtering Select..

P9

Bit 9: Debouncing Filtering Select..

P10

Bit 10: Debouncing Filtering Select..

P11

Bit 11: Debouncing Filtering Select..

P12

Bit 12: Debouncing Filtering Select..

P13

Bit 13: Debouncing Filtering Select..

P14

Bit 14: Debouncing Filtering Select..

P15

Bit 15: Debouncing Filtering Select..

P16

Bit 16: Debouncing Filtering Select..

P17

Bit 17: Debouncing Filtering Select..

P18

Bit 18: Debouncing Filtering Select..

P19

Bit 19: Debouncing Filtering Select..

P20

Bit 20: Debouncing Filtering Select..

P21

Bit 21: Debouncing Filtering Select..

P22

Bit 22: Debouncing Filtering Select..

P23

Bit 23: Debouncing Filtering Select..

P24

Bit 24: Debouncing Filtering Select..

P25

Bit 25: Debouncing Filtering Select..

P26

Bit 26: Debouncing Filtering Select..

P27

Bit 27: Debouncing Filtering Select..

P28

Bit 28: Debouncing Filtering Select..

P29

Bit 29: Debouncing Filtering Select..

P30

Bit 30: Debouncing Filtering Select..

P31

Bit 31: Debouncing Filtering Select..

IFDGSR

Glitch or Debouncing Input Filter Clock Selection Status Register

Offset: 0x88, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Glitch or Debouncing Filter Selection Status.

P1

Bit 1: Glitch or Debouncing Filter Selection Status.

P2

Bit 2: Glitch or Debouncing Filter Selection Status.

P3

Bit 3: Glitch or Debouncing Filter Selection Status.

P4

Bit 4: Glitch or Debouncing Filter Selection Status.

P5

Bit 5: Glitch or Debouncing Filter Selection Status.

P6

Bit 6: Glitch or Debouncing Filter Selection Status.

P7

Bit 7: Glitch or Debouncing Filter Selection Status.

P8

Bit 8: Glitch or Debouncing Filter Selection Status.

P9

Bit 9: Glitch or Debouncing Filter Selection Status.

P10

Bit 10: Glitch or Debouncing Filter Selection Status.

P11

Bit 11: Glitch or Debouncing Filter Selection Status.

P12

Bit 12: Glitch or Debouncing Filter Selection Status.

P13

Bit 13: Glitch or Debouncing Filter Selection Status.

P14

Bit 14: Glitch or Debouncing Filter Selection Status.

P15

Bit 15: Glitch or Debouncing Filter Selection Status.

P16

Bit 16: Glitch or Debouncing Filter Selection Status.

P17

Bit 17: Glitch or Debouncing Filter Selection Status.

P18

Bit 18: Glitch or Debouncing Filter Selection Status.

P19

Bit 19: Glitch or Debouncing Filter Selection Status.

P20

Bit 20: Glitch or Debouncing Filter Selection Status.

P21

Bit 21: Glitch or Debouncing Filter Selection Status.

P22

Bit 22: Glitch or Debouncing Filter Selection Status.

P23

Bit 23: Glitch or Debouncing Filter Selection Status.

P24

Bit 24: Glitch or Debouncing Filter Selection Status.

P25

Bit 25: Glitch or Debouncing Filter Selection Status.

P26

Bit 26: Glitch or Debouncing Filter Selection Status.

P27

Bit 27: Glitch or Debouncing Filter Selection Status.

P28

Bit 28: Glitch or Debouncing Filter Selection Status.

P29

Bit 29: Glitch or Debouncing Filter Selection Status.

P30

Bit 30: Glitch or Debouncing Filter Selection Status.

P31

Bit 31: Glitch or Debouncing Filter Selection Status.

SCDR

Slow Clock Divider Debouncing Register

Offset: 0x8c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-13: Slow Clock Divider Selection for Debouncing.

OWER

Output Write Enable

Offset: 0xa0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Enable..

P1

Bit 1: Output Write Enable..

P2

Bit 2: Output Write Enable..

P3

Bit 3: Output Write Enable..

P4

Bit 4: Output Write Enable..

P5

Bit 5: Output Write Enable..

P6

Bit 6: Output Write Enable..

P7

Bit 7: Output Write Enable..

P8

Bit 8: Output Write Enable..

P9

Bit 9: Output Write Enable..

P10

Bit 10: Output Write Enable..

P11

Bit 11: Output Write Enable..

P12

Bit 12: Output Write Enable..

P13

Bit 13: Output Write Enable..

P14

Bit 14: Output Write Enable..

P15

Bit 15: Output Write Enable..

P16

Bit 16: Output Write Enable..

P17

Bit 17: Output Write Enable..

P18

Bit 18: Output Write Enable..

P19

Bit 19: Output Write Enable..

P20

Bit 20: Output Write Enable..

P21

Bit 21: Output Write Enable..

P22

Bit 22: Output Write Enable..

P23

Bit 23: Output Write Enable..

P24

Bit 24: Output Write Enable..

P25

Bit 25: Output Write Enable..

P26

Bit 26: Output Write Enable..

P27

Bit 27: Output Write Enable..

P28

Bit 28: Output Write Enable..

P29

Bit 29: Output Write Enable..

P30

Bit 30: Output Write Enable..

P31

Bit 31: Output Write Enable..

OWDR

Output Write Disable

Offset: 0xa4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Disable..

P1

Bit 1: Output Write Disable..

P2

Bit 2: Output Write Disable..

P3

Bit 3: Output Write Disable..

P4

Bit 4: Output Write Disable..

P5

Bit 5: Output Write Disable..

P6

Bit 6: Output Write Disable..

P7

Bit 7: Output Write Disable..

P8

Bit 8: Output Write Disable..

P9

Bit 9: Output Write Disable..

P10

Bit 10: Output Write Disable..

P11

Bit 11: Output Write Disable..

P12

Bit 12: Output Write Disable..

P13

Bit 13: Output Write Disable..

P14

Bit 14: Output Write Disable..

P15

Bit 15: Output Write Disable..

P16

Bit 16: Output Write Disable..

P17

Bit 17: Output Write Disable..

P18

Bit 18: Output Write Disable..

P19

Bit 19: Output Write Disable..

P20

Bit 20: Output Write Disable..

P21

Bit 21: Output Write Disable..

P22

Bit 22: Output Write Disable..

P23

Bit 23: Output Write Disable..

P24

Bit 24: Output Write Disable..

P25

Bit 25: Output Write Disable..

P26

Bit 26: Output Write Disable..

P27

Bit 27: Output Write Disable..

P28

Bit 28: Output Write Disable..

P29

Bit 29: Output Write Disable..

P30

Bit 30: Output Write Disable..

P31

Bit 31: Output Write Disable..

OWSR

Output Write Status Register

Offset: 0xa8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Write Status..

P1

Bit 1: Output Write Status..

P2

Bit 2: Output Write Status..

P3

Bit 3: Output Write Status..

P4

Bit 4: Output Write Status..

P5

Bit 5: Output Write Status..

P6

Bit 6: Output Write Status..

P7

Bit 7: Output Write Status..

P8

Bit 8: Output Write Status..

P9

Bit 9: Output Write Status..

P10

Bit 10: Output Write Status..

P11

Bit 11: Output Write Status..

P12

Bit 12: Output Write Status..

P13

Bit 13: Output Write Status..

P14

Bit 14: Output Write Status..

P15

Bit 15: Output Write Status..

P16

Bit 16: Output Write Status..

P17

Bit 17: Output Write Status..

P18

Bit 18: Output Write Status..

P19

Bit 19: Output Write Status..

P20

Bit 20: Output Write Status..

P21

Bit 21: Output Write Status..

P22

Bit 22: Output Write Status..

P23

Bit 23: Output Write Status..

P24

Bit 24: Output Write Status..

P25

Bit 25: Output Write Status..

P26

Bit 26: Output Write Status..

P27

Bit 27: Output Write Status..

P28

Bit 28: Output Write Status..

P29

Bit 29: Output Write Status..

P30

Bit 30: Output Write Status..

P31

Bit 31: Output Write Status..

AIMER

Additional Interrupt Modes Enable Register

Offset: 0xb0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Enable..

P1

Bit 1: Additional Interrupt Modes Enable..

P2

Bit 2: Additional Interrupt Modes Enable..

P3

Bit 3: Additional Interrupt Modes Enable..

P4

Bit 4: Additional Interrupt Modes Enable..

P5

Bit 5: Additional Interrupt Modes Enable..

P6

Bit 6: Additional Interrupt Modes Enable..

P7

Bit 7: Additional Interrupt Modes Enable..

P8

Bit 8: Additional Interrupt Modes Enable..

P9

Bit 9: Additional Interrupt Modes Enable..

P10

Bit 10: Additional Interrupt Modes Enable..

P11

Bit 11: Additional Interrupt Modes Enable..

P12

Bit 12: Additional Interrupt Modes Enable..

P13

Bit 13: Additional Interrupt Modes Enable..

P14

Bit 14: Additional Interrupt Modes Enable..

P15

Bit 15: Additional Interrupt Modes Enable..

P16

Bit 16: Additional Interrupt Modes Enable..

P17

Bit 17: Additional Interrupt Modes Enable..

P18

Bit 18: Additional Interrupt Modes Enable..

P19

Bit 19: Additional Interrupt Modes Enable..

P20

Bit 20: Additional Interrupt Modes Enable..

P21

Bit 21: Additional Interrupt Modes Enable..

P22

Bit 22: Additional Interrupt Modes Enable..

P23

Bit 23: Additional Interrupt Modes Enable..

P24

Bit 24: Additional Interrupt Modes Enable..

P25

Bit 25: Additional Interrupt Modes Enable..

P26

Bit 26: Additional Interrupt Modes Enable..

P27

Bit 27: Additional Interrupt Modes Enable..

P28

Bit 28: Additional Interrupt Modes Enable..

P29

Bit 29: Additional Interrupt Modes Enable..

P30

Bit 30: Additional Interrupt Modes Enable..

P31

Bit 31: Additional Interrupt Modes Enable..

AIMDR

Additional Interrupt Modes Disables Register

Offset: 0xb4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Disable..

P1

Bit 1: Additional Interrupt Modes Disable..

P2

Bit 2: Additional Interrupt Modes Disable..

P3

Bit 3: Additional Interrupt Modes Disable..

P4

Bit 4: Additional Interrupt Modes Disable..

P5

Bit 5: Additional Interrupt Modes Disable..

P6

Bit 6: Additional Interrupt Modes Disable..

P7

Bit 7: Additional Interrupt Modes Disable..

P8

Bit 8: Additional Interrupt Modes Disable..

P9

Bit 9: Additional Interrupt Modes Disable..

P10

Bit 10: Additional Interrupt Modes Disable..

P11

Bit 11: Additional Interrupt Modes Disable..

P12

Bit 12: Additional Interrupt Modes Disable..

P13

Bit 13: Additional Interrupt Modes Disable..

P14

Bit 14: Additional Interrupt Modes Disable..

P15

Bit 15: Additional Interrupt Modes Disable..

P16

Bit 16: Additional Interrupt Modes Disable..

P17

Bit 17: Additional Interrupt Modes Disable..

P18

Bit 18: Additional Interrupt Modes Disable..

P19

Bit 19: Additional Interrupt Modes Disable..

P20

Bit 20: Additional Interrupt Modes Disable..

P21

Bit 21: Additional Interrupt Modes Disable..

P22

Bit 22: Additional Interrupt Modes Disable..

P23

Bit 23: Additional Interrupt Modes Disable..

P24

Bit 24: Additional Interrupt Modes Disable..

P25

Bit 25: Additional Interrupt Modes Disable..

P26

Bit 26: Additional Interrupt Modes Disable..

P27

Bit 27: Additional Interrupt Modes Disable..

P28

Bit 28: Additional Interrupt Modes Disable..

P29

Bit 29: Additional Interrupt Modes Disable..

P30

Bit 30: Additional Interrupt Modes Disable..

P31

Bit 31: Additional Interrupt Modes Disable..

AIMMR

Additional Interrupt Modes Mask Register

Offset: 0xb8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Peripheral CD Status..

P1

Bit 1: Peripheral CD Status..

P2

Bit 2: Peripheral CD Status..

P3

Bit 3: Peripheral CD Status..

P4

Bit 4: Peripheral CD Status..

P5

Bit 5: Peripheral CD Status..

P6

Bit 6: Peripheral CD Status..

P7

Bit 7: Peripheral CD Status..

P8

Bit 8: Peripheral CD Status..

P9

Bit 9: Peripheral CD Status..

P10

Bit 10: Peripheral CD Status..

P11

Bit 11: Peripheral CD Status..

P12

Bit 12: Peripheral CD Status..

P13

Bit 13: Peripheral CD Status..

P14

Bit 14: Peripheral CD Status..

P15

Bit 15: Peripheral CD Status..

P16

Bit 16: Peripheral CD Status..

P17

Bit 17: Peripheral CD Status..

P18

Bit 18: Peripheral CD Status..

P19

Bit 19: Peripheral CD Status..

P20

Bit 20: Peripheral CD Status..

P21

Bit 21: Peripheral CD Status..

P22

Bit 22: Peripheral CD Status..

P23

Bit 23: Peripheral CD Status..

P24

Bit 24: Peripheral CD Status..

P25

Bit 25: Peripheral CD Status..

P26

Bit 26: Peripheral CD Status..

P27

Bit 27: Peripheral CD Status..

P28

Bit 28: Peripheral CD Status..

P29

Bit 29: Peripheral CD Status..

P30

Bit 30: Peripheral CD Status..

P31

Bit 31: Peripheral CD Status..

ESR

Edge Select Register

Offset: 0xc0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Edge Interrupt Selection..

P1

Bit 1: Edge Interrupt Selection..

P2

Bit 2: Edge Interrupt Selection..

P3

Bit 3: Edge Interrupt Selection..

P4

Bit 4: Edge Interrupt Selection..

P5

Bit 5: Edge Interrupt Selection..

P6

Bit 6: Edge Interrupt Selection..

P7

Bit 7: Edge Interrupt Selection..

P8

Bit 8: Edge Interrupt Selection..

P9

Bit 9: Edge Interrupt Selection..

P10

Bit 10: Edge Interrupt Selection..

P11

Bit 11: Edge Interrupt Selection..

P12

Bit 12: Edge Interrupt Selection..

P13

Bit 13: Edge Interrupt Selection..

P14

Bit 14: Edge Interrupt Selection..

P15

Bit 15: Edge Interrupt Selection..

P16

Bit 16: Edge Interrupt Selection..

P17

Bit 17: Edge Interrupt Selection..

P18

Bit 18: Edge Interrupt Selection..

P19

Bit 19: Edge Interrupt Selection..

P20

Bit 20: Edge Interrupt Selection..

P21

Bit 21: Edge Interrupt Selection..

P22

Bit 22: Edge Interrupt Selection..

P23

Bit 23: Edge Interrupt Selection..

P24

Bit 24: Edge Interrupt Selection..

P25

Bit 25: Edge Interrupt Selection..

P26

Bit 26: Edge Interrupt Selection..

P27

Bit 27: Edge Interrupt Selection..

P28

Bit 28: Edge Interrupt Selection..

P29

Bit 29: Edge Interrupt Selection..

P30

Bit 30: Edge Interrupt Selection..

P31

Bit 31: Edge Interrupt Selection..

LSR

Level Select Register

Offset: 0xc4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Level Interrupt Selection..

P1

Bit 1: Level Interrupt Selection..

P2

Bit 2: Level Interrupt Selection..

P3

Bit 3: Level Interrupt Selection..

P4

Bit 4: Level Interrupt Selection..

P5

Bit 5: Level Interrupt Selection..

P6

Bit 6: Level Interrupt Selection..

P7

Bit 7: Level Interrupt Selection..

P8

Bit 8: Level Interrupt Selection..

P9

Bit 9: Level Interrupt Selection..

P10

Bit 10: Level Interrupt Selection..

P11

Bit 11: Level Interrupt Selection..

P12

Bit 12: Level Interrupt Selection..

P13

Bit 13: Level Interrupt Selection..

P14

Bit 14: Level Interrupt Selection..

P15

Bit 15: Level Interrupt Selection..

P16

Bit 16: Level Interrupt Selection..

P17

Bit 17: Level Interrupt Selection..

P18

Bit 18: Level Interrupt Selection..

P19

Bit 19: Level Interrupt Selection..

P20

Bit 20: Level Interrupt Selection..

P21

Bit 21: Level Interrupt Selection..

P22

Bit 22: Level Interrupt Selection..

P23

Bit 23: Level Interrupt Selection..

P24

Bit 24: Level Interrupt Selection..

P25

Bit 25: Level Interrupt Selection..

P26

Bit 26: Level Interrupt Selection..

P27

Bit 27: Level Interrupt Selection..

P28

Bit 28: Level Interrupt Selection..

P29

Bit 29: Level Interrupt Selection..

P30

Bit 30: Level Interrupt Selection..

P31

Bit 31: Level Interrupt Selection..

ELSR

Edge/Level Status Register

Offset: 0xc8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge/Level Interrupt source selection..

P1

Bit 1: Edge/Level Interrupt source selection..

P2

Bit 2: Edge/Level Interrupt source selection..

P3

Bit 3: Edge/Level Interrupt source selection..

P4

Bit 4: Edge/Level Interrupt source selection..

P5

Bit 5: Edge/Level Interrupt source selection..

P6

Bit 6: Edge/Level Interrupt source selection..

P7

Bit 7: Edge/Level Interrupt source selection..

P8

Bit 8: Edge/Level Interrupt source selection..

P9

Bit 9: Edge/Level Interrupt source selection..

P10

Bit 10: Edge/Level Interrupt source selection..

P11

Bit 11: Edge/Level Interrupt source selection..

P12

Bit 12: Edge/Level Interrupt source selection..

P13

Bit 13: Edge/Level Interrupt source selection..

P14

Bit 14: Edge/Level Interrupt source selection..

P15

Bit 15: Edge/Level Interrupt source selection..

P16

Bit 16: Edge/Level Interrupt source selection..

P17

Bit 17: Edge/Level Interrupt source selection..

P18

Bit 18: Edge/Level Interrupt source selection..

P19

Bit 19: Edge/Level Interrupt source selection..

P20

Bit 20: Edge/Level Interrupt source selection..

P21

Bit 21: Edge/Level Interrupt source selection..

P22

Bit 22: Edge/Level Interrupt source selection..

P23

Bit 23: Edge/Level Interrupt source selection..

P24

Bit 24: Edge/Level Interrupt source selection..

P25

Bit 25: Edge/Level Interrupt source selection..

P26

Bit 26: Edge/Level Interrupt source selection..

P27

Bit 27: Edge/Level Interrupt source selection..

P28

Bit 28: Edge/Level Interrupt source selection..

P29

Bit 29: Edge/Level Interrupt source selection..

P30

Bit 30: Edge/Level Interrupt source selection..

P31

Bit 31: Edge/Level Interrupt source selection..

FELLSR

Falling Edge/Low Level Select Register

Offset: 0xd0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Falling Edge/Low Level Interrupt Selection..

P1

Bit 1: Falling Edge/Low Level Interrupt Selection..

P2

Bit 2: Falling Edge/Low Level Interrupt Selection..

P3

Bit 3: Falling Edge/Low Level Interrupt Selection..

P4

Bit 4: Falling Edge/Low Level Interrupt Selection..

P5

Bit 5: Falling Edge/Low Level Interrupt Selection..

P6

Bit 6: Falling Edge/Low Level Interrupt Selection..

P7

Bit 7: Falling Edge/Low Level Interrupt Selection..

P8

Bit 8: Falling Edge/Low Level Interrupt Selection..

P9

Bit 9: Falling Edge/Low Level Interrupt Selection..

P10

Bit 10: Falling Edge/Low Level Interrupt Selection..

P11

Bit 11: Falling Edge/Low Level Interrupt Selection..

P12

Bit 12: Falling Edge/Low Level Interrupt Selection..

P13

Bit 13: Falling Edge/Low Level Interrupt Selection..

P14

Bit 14: Falling Edge/Low Level Interrupt Selection..

P15

Bit 15: Falling Edge/Low Level Interrupt Selection..

P16

Bit 16: Falling Edge/Low Level Interrupt Selection..

P17

Bit 17: Falling Edge/Low Level Interrupt Selection..

P18

Bit 18: Falling Edge/Low Level Interrupt Selection..

P19

Bit 19: Falling Edge/Low Level Interrupt Selection..

P20

Bit 20: Falling Edge/Low Level Interrupt Selection..

P21

Bit 21: Falling Edge/Low Level Interrupt Selection..

P22

Bit 22: Falling Edge/Low Level Interrupt Selection..

P23

Bit 23: Falling Edge/Low Level Interrupt Selection..

P24

Bit 24: Falling Edge/Low Level Interrupt Selection..

P25

Bit 25: Falling Edge/Low Level Interrupt Selection..

P26

Bit 26: Falling Edge/Low Level Interrupt Selection..

P27

Bit 27: Falling Edge/Low Level Interrupt Selection..

P28

Bit 28: Falling Edge/Low Level Interrupt Selection..

P29

Bit 29: Falling Edge/Low Level Interrupt Selection..

P30

Bit 30: Falling Edge/Low Level Interrupt Selection..

P31

Bit 31: Falling Edge/Low Level Interrupt Selection..

REHLSR

Rising Edge/ High Level Select Register

Offset: 0xd4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Rising Edge /High Level Interrupt Selection..

P1

Bit 1: Rising Edge /High Level Interrupt Selection..

P2

Bit 2: Rising Edge /High Level Interrupt Selection..

P3

Bit 3: Rising Edge /High Level Interrupt Selection..

P4

Bit 4: Rising Edge /High Level Interrupt Selection..

P5

Bit 5: Rising Edge /High Level Interrupt Selection..

P6

Bit 6: Rising Edge /High Level Interrupt Selection..

P7

Bit 7: Rising Edge /High Level Interrupt Selection..

P8

Bit 8: Rising Edge /High Level Interrupt Selection..

P9

Bit 9: Rising Edge /High Level Interrupt Selection..

P10

Bit 10: Rising Edge /High Level Interrupt Selection..

P11

Bit 11: Rising Edge /High Level Interrupt Selection..

P12

Bit 12: Rising Edge /High Level Interrupt Selection..

P13

Bit 13: Rising Edge /High Level Interrupt Selection..

P14

Bit 14: Rising Edge /High Level Interrupt Selection..

P15

Bit 15: Rising Edge /High Level Interrupt Selection..

P16

Bit 16: Rising Edge /High Level Interrupt Selection..

P17

Bit 17: Rising Edge /High Level Interrupt Selection..

P18

Bit 18: Rising Edge /High Level Interrupt Selection..

P19

Bit 19: Rising Edge /High Level Interrupt Selection..

P20

Bit 20: Rising Edge /High Level Interrupt Selection..

P21

Bit 21: Rising Edge /High Level Interrupt Selection..

P22

Bit 22: Rising Edge /High Level Interrupt Selection..

P23

Bit 23: Rising Edge /High Level Interrupt Selection..

P24

Bit 24: Rising Edge /High Level Interrupt Selection..

P25

Bit 25: Rising Edge /High Level Interrupt Selection..

P26

Bit 26: Rising Edge /High Level Interrupt Selection..

P27

Bit 27: Rising Edge /High Level Interrupt Selection..

P28

Bit 28: Rising Edge /High Level Interrupt Selection..

P29

Bit 29: Rising Edge /High Level Interrupt Selection..

P30

Bit 30: Rising Edge /High Level Interrupt Selection..

P31

Bit 31: Rising Edge /High Level Interrupt Selection..

FRLHSR

Fall/Rise - Low/High Status Register

Offset: 0xd8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge /Level Interrupt Source Selection..

P1

Bit 1: Edge /Level Interrupt Source Selection..

P2

Bit 2: Edge /Level Interrupt Source Selection..

P3

Bit 3: Edge /Level Interrupt Source Selection..

P4

Bit 4: Edge /Level Interrupt Source Selection..

P5

Bit 5: Edge /Level Interrupt Source Selection..

P6

Bit 6: Edge /Level Interrupt Source Selection..

P7

Bit 7: Edge /Level Interrupt Source Selection..

P8

Bit 8: Edge /Level Interrupt Source Selection..

P9

Bit 9: Edge /Level Interrupt Source Selection..

P10

Bit 10: Edge /Level Interrupt Source Selection..

P11

Bit 11: Edge /Level Interrupt Source Selection..

P12

Bit 12: Edge /Level Interrupt Source Selection..

P13

Bit 13: Edge /Level Interrupt Source Selection..

P14

Bit 14: Edge /Level Interrupt Source Selection..

P15

Bit 15: Edge /Level Interrupt Source Selection..

P16

Bit 16: Edge /Level Interrupt Source Selection..

P17

Bit 17: Edge /Level Interrupt Source Selection..

P18

Bit 18: Edge /Level Interrupt Source Selection..

P19

Bit 19: Edge /Level Interrupt Source Selection..

P20

Bit 20: Edge /Level Interrupt Source Selection..

P21

Bit 21: Edge /Level Interrupt Source Selection..

P22

Bit 22: Edge /Level Interrupt Source Selection..

P23

Bit 23: Edge /Level Interrupt Source Selection..

P24

Bit 24: Edge /Level Interrupt Source Selection..

P25

Bit 25: Edge /Level Interrupt Source Selection..

P26

Bit 26: Edge /Level Interrupt Source Selection..

P27

Bit 27: Edge /Level Interrupt Source Selection..

P28

Bit 28: Edge /Level Interrupt Source Selection..

P29

Bit 29: Edge /Level Interrupt Source Selection..

P30

Bit 30: Edge /Level Interrupt Source Selection..

P31

Bit 31: Edge /Level Interrupt Source Selection..

LOCKSR

Lock Status

Offset: 0xe0, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Lock Status..

P1

Bit 1: Lock Status..

P2

Bit 2: Lock Status..

P3

Bit 3: Lock Status..

P4

Bit 4: Lock Status..

P5

Bit 5: Lock Status..

P6

Bit 6: Lock Status..

P7

Bit 7: Lock Status..

P8

Bit 8: Lock Status..

P9

Bit 9: Lock Status..

P10

Bit 10: Lock Status..

P11

Bit 11: Lock Status..

P12

Bit 12: Lock Status..

P13

Bit 13: Lock Status..

P14

Bit 14: Lock Status..

P15

Bit 15: Lock Status..

P16

Bit 16: Lock Status..

P17

Bit 17: Lock Status..

P18

Bit 18: Lock Status..

P19

Bit 19: Lock Status..

P20

Bit 20: Lock Status..

P21

Bit 21: Lock Status..

P22

Bit 22: Lock Status..

P23

Bit 23: Lock Status..

P24

Bit 24: Lock Status..

P25

Bit 25: Lock Status..

P26

Bit 26: Lock Status..

P27

Bit 27: Lock Status..

P28

Bit 28: Lock Status..

P29

Bit 29: Lock Status..

P30

Bit 30: Lock Status..

P31

Bit 31: Lock Status..

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

PIOD

0x400e1400: Parallel Input/Output Controller D

450/1285 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PER
0x4 PDR
0x8 PSR
0x10 OER
0x14 ODR
0x18 OSR
0x20 IFER
0x24 IFDR
0x28 IFSR
0x30 SODR
0x34 CODR
0x38 ODSR
0x3c PDSR
0x40 IER
0x44 IDR
0x48 IMR
0x4c ISR
0x50 MDER
0x54 MDDR
0x58 MDSR
0x60 PUDR
0x64 PUER
0x68 PUSR
0x70 ABSR
0x80 SCIFSR
0x84 DIFSR
0x88 IFDGSR
0x8c SCDR
0xa0 OWER
0xa4 OWDR
0xa8 OWSR
0xb0 AIMER
0xb4 AIMDR
0xb8 AIMMR
0xc0 ESR
0xc4 LSR
0xc8 ELSR
0xd0 FELLSR
0xd4 REHLSR
0xd8 FRLHSR
0xe0 LOCKSR
0xe4 WPMR
0xe8 WPSR

PER

PIO Enable Register

Offset: 0x0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Enable.

P1

Bit 1: PIO Enable.

P2

Bit 2: PIO Enable.

P3

Bit 3: PIO Enable.

P4

Bit 4: PIO Enable.

P5

Bit 5: PIO Enable.

P6

Bit 6: PIO Enable.

P7

Bit 7: PIO Enable.

P8

Bit 8: PIO Enable.

P9

Bit 9: PIO Enable.

P10

Bit 10: PIO Enable.

P11

Bit 11: PIO Enable.

P12

Bit 12: PIO Enable.

P13

Bit 13: PIO Enable.

P14

Bit 14: PIO Enable.

P15

Bit 15: PIO Enable.

P16

Bit 16: PIO Enable.

P17

Bit 17: PIO Enable.

P18

Bit 18: PIO Enable.

P19

Bit 19: PIO Enable.

P20

Bit 20: PIO Enable.

P21

Bit 21: PIO Enable.

P22

Bit 22: PIO Enable.

P23

Bit 23: PIO Enable.

P24

Bit 24: PIO Enable.

P25

Bit 25: PIO Enable.

P26

Bit 26: PIO Enable.

P27

Bit 27: PIO Enable.

P28

Bit 28: PIO Enable.

P29

Bit 29: PIO Enable.

P30

Bit 30: PIO Enable.

P31

Bit 31: PIO Enable.

PDR

PIO Disable Register

Offset: 0x4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: PIO Disable.

P1

Bit 1: PIO Disable.

P2

Bit 2: PIO Disable.

P3

Bit 3: PIO Disable.

P4

Bit 4: PIO Disable.

P5

Bit 5: PIO Disable.

P6

Bit 6: PIO Disable.

P7

Bit 7: PIO Disable.

P8

Bit 8: PIO Disable.

P9

Bit 9: PIO Disable.

P10

Bit 10: PIO Disable.

P11

Bit 11: PIO Disable.

P12

Bit 12: PIO Disable.

P13

Bit 13: PIO Disable.

P14

Bit 14: PIO Disable.

P15

Bit 15: PIO Disable.

P16

Bit 16: PIO Disable.

P17

Bit 17: PIO Disable.

P18

Bit 18: PIO Disable.

P19

Bit 19: PIO Disable.

P20

Bit 20: PIO Disable.

P21

Bit 21: PIO Disable.

P22

Bit 22: PIO Disable.

P23

Bit 23: PIO Disable.

P24

Bit 24: PIO Disable.

P25

Bit 25: PIO Disable.

P26

Bit 26: PIO Disable.

P27

Bit 27: PIO Disable.

P28

Bit 28: PIO Disable.

P29

Bit 29: PIO Disable.

P30

Bit 30: PIO Disable.

P31

Bit 31: PIO Disable.

PSR

PIO Status Register

Offset: 0x8, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: PIO Status.

P1

Bit 1: PIO Status.

P2

Bit 2: PIO Status.

P3

Bit 3: PIO Status.

P4

Bit 4: PIO Status.

P5

Bit 5: PIO Status.

P6

Bit 6: PIO Status.

P7

Bit 7: PIO Status.

P8

Bit 8: PIO Status.

P9

Bit 9: PIO Status.

P10

Bit 10: PIO Status.

P11

Bit 11: PIO Status.

P12

Bit 12: PIO Status.

P13

Bit 13: PIO Status.

P14

Bit 14: PIO Status.

P15

Bit 15: PIO Status.

P16

Bit 16: PIO Status.

P17

Bit 17: PIO Status.

P18

Bit 18: PIO Status.

P19

Bit 19: PIO Status.

P20

Bit 20: PIO Status.

P21

Bit 21: PIO Status.

P22

Bit 22: PIO Status.

P23

Bit 23: PIO Status.

P24

Bit 24: PIO Status.

P25

Bit 25: PIO Status.

P26

Bit 26: PIO Status.

P27

Bit 27: PIO Status.

P28

Bit 28: PIO Status.

P29

Bit 29: PIO Status.

P30

Bit 30: PIO Status.

P31

Bit 31: PIO Status.

OER

Output Enable Register

Offset: 0x10, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Enable.

P1

Bit 1: Output Enable.

P2

Bit 2: Output Enable.

P3

Bit 3: Output Enable.

P4

Bit 4: Output Enable.

P5

Bit 5: Output Enable.

P6

Bit 6: Output Enable.

P7

Bit 7: Output Enable.

P8

Bit 8: Output Enable.

P9

Bit 9: Output Enable.

P10

Bit 10: Output Enable.

P11

Bit 11: Output Enable.

P12

Bit 12: Output Enable.

P13

Bit 13: Output Enable.

P14

Bit 14: Output Enable.

P15

Bit 15: Output Enable.

P16

Bit 16: Output Enable.

P17

Bit 17: Output Enable.

P18

Bit 18: Output Enable.

P19

Bit 19: Output Enable.

P20

Bit 20: Output Enable.

P21

Bit 21: Output Enable.

P22

Bit 22: Output Enable.

P23

Bit 23: Output Enable.

P24

Bit 24: Output Enable.

P25

Bit 25: Output Enable.

P26

Bit 26: Output Enable.

P27

Bit 27: Output Enable.

P28

Bit 28: Output Enable.

P29

Bit 29: Output Enable.

P30

Bit 30: Output Enable.

P31

Bit 31: Output Enable.

ODR

Output Disable Register

Offset: 0x14, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Disable.

P1

Bit 1: Output Disable.

P2

Bit 2: Output Disable.

P3

Bit 3: Output Disable.

P4

Bit 4: Output Disable.

P5

Bit 5: Output Disable.

P6

Bit 6: Output Disable.

P7

Bit 7: Output Disable.

P8

Bit 8: Output Disable.

P9

Bit 9: Output Disable.

P10

Bit 10: Output Disable.

P11

Bit 11: Output Disable.

P12

Bit 12: Output Disable.

P13

Bit 13: Output Disable.

P14

Bit 14: Output Disable.

P15

Bit 15: Output Disable.

P16

Bit 16: Output Disable.

P17

Bit 17: Output Disable.

P18

Bit 18: Output Disable.

P19

Bit 19: Output Disable.

P20

Bit 20: Output Disable.

P21

Bit 21: Output Disable.

P22

Bit 22: Output Disable.

P23

Bit 23: Output Disable.

P24

Bit 24: Output Disable.

P25

Bit 25: Output Disable.

P26

Bit 26: Output Disable.

P27

Bit 27: Output Disable.

P28

Bit 28: Output Disable.

P29

Bit 29: Output Disable.

P30

Bit 30: Output Disable.

P31

Bit 31: Output Disable.

OSR

Output Status Register

Offset: 0x18, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Status.

P1

Bit 1: Output Status.

P2

Bit 2: Output Status.

P3

Bit 3: Output Status.

P4

Bit 4: Output Status.

P5

Bit 5: Output Status.

P6

Bit 6: Output Status.

P7

Bit 7: Output Status.

P8

Bit 8: Output Status.

P9

Bit 9: Output Status.

P10

Bit 10: Output Status.

P11

Bit 11: Output Status.

P12

Bit 12: Output Status.

P13

Bit 13: Output Status.

P14

Bit 14: Output Status.

P15

Bit 15: Output Status.

P16

Bit 16: Output Status.

P17

Bit 17: Output Status.

P18

Bit 18: Output Status.

P19

Bit 19: Output Status.

P20

Bit 20: Output Status.

P21

Bit 21: Output Status.

P22

Bit 22: Output Status.

P23

Bit 23: Output Status.

P24

Bit 24: Output Status.

P25

Bit 25: Output Status.

P26

Bit 26: Output Status.

P27

Bit 27: Output Status.

P28

Bit 28: Output Status.

P29

Bit 29: Output Status.

P30

Bit 30: Output Status.

P31

Bit 31: Output Status.

IFER

Glitch Input Filter Enable Register

Offset: 0x20, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Enable.

P1

Bit 1: Input Filter Enable.

P2

Bit 2: Input Filter Enable.

P3

Bit 3: Input Filter Enable.

P4

Bit 4: Input Filter Enable.

P5

Bit 5: Input Filter Enable.

P6

Bit 6: Input Filter Enable.

P7

Bit 7: Input Filter Enable.

P8

Bit 8: Input Filter Enable.

P9

Bit 9: Input Filter Enable.

P10

Bit 10: Input Filter Enable.

P11

Bit 11: Input Filter Enable.

P12

Bit 12: Input Filter Enable.

P13

Bit 13: Input Filter Enable.

P14

Bit 14: Input Filter Enable.

P15

Bit 15: Input Filter Enable.

P16

Bit 16: Input Filter Enable.

P17

Bit 17: Input Filter Enable.

P18

Bit 18: Input Filter Enable.

P19

Bit 19: Input Filter Enable.

P20

Bit 20: Input Filter Enable.

P21

Bit 21: Input Filter Enable.

P22

Bit 22: Input Filter Enable.

P23

Bit 23: Input Filter Enable.

P24

Bit 24: Input Filter Enable.

P25

Bit 25: Input Filter Enable.

P26

Bit 26: Input Filter Enable.

P27

Bit 27: Input Filter Enable.

P28

Bit 28: Input Filter Enable.

P29

Bit 29: Input Filter Enable.

P30

Bit 30: Input Filter Enable.

P31

Bit 31: Input Filter Enable.

IFDR

Glitch Input Filter Disable Register

Offset: 0x24, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Filter Disable.

P1

Bit 1: Input Filter Disable.

P2

Bit 2: Input Filter Disable.

P3

Bit 3: Input Filter Disable.

P4

Bit 4: Input Filter Disable.

P5

Bit 5: Input Filter Disable.

P6

Bit 6: Input Filter Disable.

P7

Bit 7: Input Filter Disable.

P8

Bit 8: Input Filter Disable.

P9

Bit 9: Input Filter Disable.

P10

Bit 10: Input Filter Disable.

P11

Bit 11: Input Filter Disable.

P12

Bit 12: Input Filter Disable.

P13

Bit 13: Input Filter Disable.

P14

Bit 14: Input Filter Disable.

P15

Bit 15: Input Filter Disable.

P16

Bit 16: Input Filter Disable.

P17

Bit 17: Input Filter Disable.

P18

Bit 18: Input Filter Disable.

P19

Bit 19: Input Filter Disable.

P20

Bit 20: Input Filter Disable.

P21

Bit 21: Input Filter Disable.

P22

Bit 22: Input Filter Disable.

P23

Bit 23: Input Filter Disable.

P24

Bit 24: Input Filter Disable.

P25

Bit 25: Input Filter Disable.

P26

Bit 26: Input Filter Disable.

P27

Bit 27: Input Filter Disable.

P28

Bit 28: Input Filter Disable.

P29

Bit 29: Input Filter Disable.

P30

Bit 30: Input Filter Disable.

P31

Bit 31: Input Filter Disable.

IFSR

Glitch Input Filter Status Register

Offset: 0x28, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Filer Status.

P1

Bit 1: Input Filer Status.

P2

Bit 2: Input Filer Status.

P3

Bit 3: Input Filer Status.

P4

Bit 4: Input Filer Status.

P5

Bit 5: Input Filer Status.

P6

Bit 6: Input Filer Status.

P7

Bit 7: Input Filer Status.

P8

Bit 8: Input Filer Status.

P9

Bit 9: Input Filer Status.

P10

Bit 10: Input Filer Status.

P11

Bit 11: Input Filer Status.

P12

Bit 12: Input Filer Status.

P13

Bit 13: Input Filer Status.

P14

Bit 14: Input Filer Status.

P15

Bit 15: Input Filer Status.

P16

Bit 16: Input Filer Status.

P17

Bit 17: Input Filer Status.

P18

Bit 18: Input Filer Status.

P19

Bit 19: Input Filer Status.

P20

Bit 20: Input Filer Status.

P21

Bit 21: Input Filer Status.

P22

Bit 22: Input Filer Status.

P23

Bit 23: Input Filer Status.

P24

Bit 24: Input Filer Status.

P25

Bit 25: Input Filer Status.

P26

Bit 26: Input Filer Status.

P27

Bit 27: Input Filer Status.

P28

Bit 28: Input Filer Status.

P29

Bit 29: Input Filer Status.

P30

Bit 30: Input Filer Status.

P31

Bit 31: Input Filer Status.

SODR

Set Output Data Register

Offset: 0x30, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Set Output Data.

P1

Bit 1: Set Output Data.

P2

Bit 2: Set Output Data.

P3

Bit 3: Set Output Data.

P4

Bit 4: Set Output Data.

P5

Bit 5: Set Output Data.

P6

Bit 6: Set Output Data.

P7

Bit 7: Set Output Data.

P8

Bit 8: Set Output Data.

P9

Bit 9: Set Output Data.

P10

Bit 10: Set Output Data.

P11

Bit 11: Set Output Data.

P12

Bit 12: Set Output Data.

P13

Bit 13: Set Output Data.

P14

Bit 14: Set Output Data.

P15

Bit 15: Set Output Data.

P16

Bit 16: Set Output Data.

P17

Bit 17: Set Output Data.

P18

Bit 18: Set Output Data.

P19

Bit 19: Set Output Data.

P20

Bit 20: Set Output Data.

P21

Bit 21: Set Output Data.

P22

Bit 22: Set Output Data.

P23

Bit 23: Set Output Data.

P24

Bit 24: Set Output Data.

P25

Bit 25: Set Output Data.

P26

Bit 26: Set Output Data.

P27

Bit 27: Set Output Data.

P28

Bit 28: Set Output Data.

P29

Bit 29: Set Output Data.

P30

Bit 30: Set Output Data.

P31

Bit 31: Set Output Data.

CODR

Clear Output Data Register

Offset: 0x34, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Clear Output Data.

P1

Bit 1: Clear Output Data.

P2

Bit 2: Clear Output Data.

P3

Bit 3: Clear Output Data.

P4

Bit 4: Clear Output Data.

P5

Bit 5: Clear Output Data.

P6

Bit 6: Clear Output Data.

P7

Bit 7: Clear Output Data.

P8

Bit 8: Clear Output Data.

P9

Bit 9: Clear Output Data.

P10

Bit 10: Clear Output Data.

P11

Bit 11: Clear Output Data.

P12

Bit 12: Clear Output Data.

P13

Bit 13: Clear Output Data.

P14

Bit 14: Clear Output Data.

P15

Bit 15: Clear Output Data.

P16

Bit 16: Clear Output Data.

P17

Bit 17: Clear Output Data.

P18

Bit 18: Clear Output Data.

P19

Bit 19: Clear Output Data.

P20

Bit 20: Clear Output Data.

P21

Bit 21: Clear Output Data.

P22

Bit 22: Clear Output Data.

P23

Bit 23: Clear Output Data.

P24

Bit 24: Clear Output Data.

P25

Bit 25: Clear Output Data.

P26

Bit 26: Clear Output Data.

P27

Bit 27: Clear Output Data.

P28

Bit 28: Clear Output Data.

P29

Bit 29: Clear Output Data.

P30

Bit 30: Clear Output Data.

P31

Bit 31: Clear Output Data.

ODSR

Output Data Status Register

Offset: 0x38, reset: None, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

PDSR

Pin Data Status Register

Offset: 0x3c, reset: None, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Data Status.

P1

Bit 1: Output Data Status.

P2

Bit 2: Output Data Status.

P3

Bit 3: Output Data Status.

P4

Bit 4: Output Data Status.

P5

Bit 5: Output Data Status.

P6

Bit 6: Output Data Status.

P7

Bit 7: Output Data Status.

P8

Bit 8: Output Data Status.

P9

Bit 9: Output Data Status.

P10

Bit 10: Output Data Status.

P11

Bit 11: Output Data Status.

P12

Bit 12: Output Data Status.

P13

Bit 13: Output Data Status.

P14

Bit 14: Output Data Status.

P15

Bit 15: Output Data Status.

P16

Bit 16: Output Data Status.

P17

Bit 17: Output Data Status.

P18

Bit 18: Output Data Status.

P19

Bit 19: Output Data Status.

P20

Bit 20: Output Data Status.

P21

Bit 21: Output Data Status.

P22

Bit 22: Output Data Status.

P23

Bit 23: Output Data Status.

P24

Bit 24: Output Data Status.

P25

Bit 25: Output Data Status.

P26

Bit 26: Output Data Status.

P27

Bit 27: Output Data Status.

P28

Bit 28: Output Data Status.

P29

Bit 29: Output Data Status.

P30

Bit 30: Output Data Status.

P31

Bit 31: Output Data Status.

IER

Interrupt Enable Register

Offset: 0x40, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Enable.

P1

Bit 1: Input Change Interrupt Enable.

P2

Bit 2: Input Change Interrupt Enable.

P3

Bit 3: Input Change Interrupt Enable.

P4

Bit 4: Input Change Interrupt Enable.

P5

Bit 5: Input Change Interrupt Enable.

P6

Bit 6: Input Change Interrupt Enable.

P7

Bit 7: Input Change Interrupt Enable.

P8

Bit 8: Input Change Interrupt Enable.

P9

Bit 9: Input Change Interrupt Enable.

P10

Bit 10: Input Change Interrupt Enable.

P11

Bit 11: Input Change Interrupt Enable.

P12

Bit 12: Input Change Interrupt Enable.

P13

Bit 13: Input Change Interrupt Enable.

P14

Bit 14: Input Change Interrupt Enable.

P15

Bit 15: Input Change Interrupt Enable.

P16

Bit 16: Input Change Interrupt Enable.

P17

Bit 17: Input Change Interrupt Enable.

P18

Bit 18: Input Change Interrupt Enable.

P19

Bit 19: Input Change Interrupt Enable.

P20

Bit 20: Input Change Interrupt Enable.

P21

Bit 21: Input Change Interrupt Enable.

P22

Bit 22: Input Change Interrupt Enable.

P23

Bit 23: Input Change Interrupt Enable.

P24

Bit 24: Input Change Interrupt Enable.

P25

Bit 25: Input Change Interrupt Enable.

P26

Bit 26: Input Change Interrupt Enable.

P27

Bit 27: Input Change Interrupt Enable.

P28

Bit 28: Input Change Interrupt Enable.

P29

Bit 29: Input Change Interrupt Enable.

P30

Bit 30: Input Change Interrupt Enable.

P31

Bit 31: Input Change Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x44, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Input Change Interrupt Disable.

P1

Bit 1: Input Change Interrupt Disable.

P2

Bit 2: Input Change Interrupt Disable.

P3

Bit 3: Input Change Interrupt Disable.

P4

Bit 4: Input Change Interrupt Disable.

P5

Bit 5: Input Change Interrupt Disable.

P6

Bit 6: Input Change Interrupt Disable.

P7

Bit 7: Input Change Interrupt Disable.

P8

Bit 8: Input Change Interrupt Disable.

P9

Bit 9: Input Change Interrupt Disable.

P10

Bit 10: Input Change Interrupt Disable.

P11

Bit 11: Input Change Interrupt Disable.

P12

Bit 12: Input Change Interrupt Disable.

P13

Bit 13: Input Change Interrupt Disable.

P14

Bit 14: Input Change Interrupt Disable.

P15

Bit 15: Input Change Interrupt Disable.

P16

Bit 16: Input Change Interrupt Disable.

P17

Bit 17: Input Change Interrupt Disable.

P18

Bit 18: Input Change Interrupt Disable.

P19

Bit 19: Input Change Interrupt Disable.

P20

Bit 20: Input Change Interrupt Disable.

P21

Bit 21: Input Change Interrupt Disable.

P22

Bit 22: Input Change Interrupt Disable.

P23

Bit 23: Input Change Interrupt Disable.

P24

Bit 24: Input Change Interrupt Disable.

P25

Bit 25: Input Change Interrupt Disable.

P26

Bit 26: Input Change Interrupt Disable.

P27

Bit 27: Input Change Interrupt Disable.

P28

Bit 28: Input Change Interrupt Disable.

P29

Bit 29: Input Change Interrupt Disable.

P30

Bit 30: Input Change Interrupt Disable.

P31

Bit 31: Input Change Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x48, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Mask.

P1

Bit 1: Input Change Interrupt Mask.

P2

Bit 2: Input Change Interrupt Mask.

P3

Bit 3: Input Change Interrupt Mask.

P4

Bit 4: Input Change Interrupt Mask.

P5

Bit 5: Input Change Interrupt Mask.

P6

Bit 6: Input Change Interrupt Mask.

P7

Bit 7: Input Change Interrupt Mask.

P8

Bit 8: Input Change Interrupt Mask.

P9

Bit 9: Input Change Interrupt Mask.

P10

Bit 10: Input Change Interrupt Mask.

P11

Bit 11: Input Change Interrupt Mask.

P12

Bit 12: Input Change Interrupt Mask.

P13

Bit 13: Input Change Interrupt Mask.

P14

Bit 14: Input Change Interrupt Mask.

P15

Bit 15: Input Change Interrupt Mask.

P16

Bit 16: Input Change Interrupt Mask.

P17

Bit 17: Input Change Interrupt Mask.

P18

Bit 18: Input Change Interrupt Mask.

P19

Bit 19: Input Change Interrupt Mask.

P20

Bit 20: Input Change Interrupt Mask.

P21

Bit 21: Input Change Interrupt Mask.

P22

Bit 22: Input Change Interrupt Mask.

P23

Bit 23: Input Change Interrupt Mask.

P24

Bit 24: Input Change Interrupt Mask.

P25

Bit 25: Input Change Interrupt Mask.

P26

Bit 26: Input Change Interrupt Mask.

P27

Bit 27: Input Change Interrupt Mask.

P28

Bit 28: Input Change Interrupt Mask.

P29

Bit 29: Input Change Interrupt Mask.

P30

Bit 30: Input Change Interrupt Mask.

P31

Bit 31: Input Change Interrupt Mask.

ISR

Interrupt Status Register

Offset: 0x4c, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Input Change Interrupt Status.

P1

Bit 1: Input Change Interrupt Status.

P2

Bit 2: Input Change Interrupt Status.

P3

Bit 3: Input Change Interrupt Status.

P4

Bit 4: Input Change Interrupt Status.

P5

Bit 5: Input Change Interrupt Status.

P6

Bit 6: Input Change Interrupt Status.

P7

Bit 7: Input Change Interrupt Status.

P8

Bit 8: Input Change Interrupt Status.

P9

Bit 9: Input Change Interrupt Status.

P10

Bit 10: Input Change Interrupt Status.

P11

Bit 11: Input Change Interrupt Status.

P12

Bit 12: Input Change Interrupt Status.

P13

Bit 13: Input Change Interrupt Status.

P14

Bit 14: Input Change Interrupt Status.

P15

Bit 15: Input Change Interrupt Status.

P16

Bit 16: Input Change Interrupt Status.

P17

Bit 17: Input Change Interrupt Status.

P18

Bit 18: Input Change Interrupt Status.

P19

Bit 19: Input Change Interrupt Status.

P20

Bit 20: Input Change Interrupt Status.

P21

Bit 21: Input Change Interrupt Status.

P22

Bit 22: Input Change Interrupt Status.

P23

Bit 23: Input Change Interrupt Status.

P24

Bit 24: Input Change Interrupt Status.

P25

Bit 25: Input Change Interrupt Status.

P26

Bit 26: Input Change Interrupt Status.

P27

Bit 27: Input Change Interrupt Status.

P28

Bit 28: Input Change Interrupt Status.

P29

Bit 29: Input Change Interrupt Status.

P30

Bit 30: Input Change Interrupt Status.

P31

Bit 31: Input Change Interrupt Status.

MDER

Multi-driver Enable Register

Offset: 0x50, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Enable..

P1

Bit 1: Multi Drive Enable..

P2

Bit 2: Multi Drive Enable..

P3

Bit 3: Multi Drive Enable..

P4

Bit 4: Multi Drive Enable..

P5

Bit 5: Multi Drive Enable..

P6

Bit 6: Multi Drive Enable..

P7

Bit 7: Multi Drive Enable..

P8

Bit 8: Multi Drive Enable..

P9

Bit 9: Multi Drive Enable..

P10

Bit 10: Multi Drive Enable..

P11

Bit 11: Multi Drive Enable..

P12

Bit 12: Multi Drive Enable..

P13

Bit 13: Multi Drive Enable..

P14

Bit 14: Multi Drive Enable..

P15

Bit 15: Multi Drive Enable..

P16

Bit 16: Multi Drive Enable..

P17

Bit 17: Multi Drive Enable..

P18

Bit 18: Multi Drive Enable..

P19

Bit 19: Multi Drive Enable..

P20

Bit 20: Multi Drive Enable..

P21

Bit 21: Multi Drive Enable..

P22

Bit 22: Multi Drive Enable..

P23

Bit 23: Multi Drive Enable..

P24

Bit 24: Multi Drive Enable..

P25

Bit 25: Multi Drive Enable..

P26

Bit 26: Multi Drive Enable..

P27

Bit 27: Multi Drive Enable..

P28

Bit 28: Multi Drive Enable..

P29

Bit 29: Multi Drive Enable..

P30

Bit 30: Multi Drive Enable..

P31

Bit 31: Multi Drive Enable..

MDDR

Multi-driver Disable Register

Offset: 0x54, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Multi Drive Disable..

P1

Bit 1: Multi Drive Disable..

P2

Bit 2: Multi Drive Disable..

P3

Bit 3: Multi Drive Disable..

P4

Bit 4: Multi Drive Disable..

P5

Bit 5: Multi Drive Disable..

P6

Bit 6: Multi Drive Disable..

P7

Bit 7: Multi Drive Disable..

P8

Bit 8: Multi Drive Disable..

P9

Bit 9: Multi Drive Disable..

P10

Bit 10: Multi Drive Disable..

P11

Bit 11: Multi Drive Disable..

P12

Bit 12: Multi Drive Disable..

P13

Bit 13: Multi Drive Disable..

P14

Bit 14: Multi Drive Disable..

P15

Bit 15: Multi Drive Disable..

P16

Bit 16: Multi Drive Disable..

P17

Bit 17: Multi Drive Disable..

P18

Bit 18: Multi Drive Disable..

P19

Bit 19: Multi Drive Disable..

P20

Bit 20: Multi Drive Disable..

P21

Bit 21: Multi Drive Disable..

P22

Bit 22: Multi Drive Disable..

P23

Bit 23: Multi Drive Disable..

P24

Bit 24: Multi Drive Disable..

P25

Bit 25: Multi Drive Disable..

P26

Bit 26: Multi Drive Disable..

P27

Bit 27: Multi Drive Disable..

P28

Bit 28: Multi Drive Disable..

P29

Bit 29: Multi Drive Disable..

P30

Bit 30: Multi Drive Disable..

P31

Bit 31: Multi Drive Disable..

MDSR

Multi-driver Status Register

Offset: 0x58, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Multi Drive Status..

P1

Bit 1: Multi Drive Status..

P2

Bit 2: Multi Drive Status..

P3

Bit 3: Multi Drive Status..

P4

Bit 4: Multi Drive Status..

P5

Bit 5: Multi Drive Status..

P6

Bit 6: Multi Drive Status..

P7

Bit 7: Multi Drive Status..

P8

Bit 8: Multi Drive Status..

P9

Bit 9: Multi Drive Status..

P10

Bit 10: Multi Drive Status..

P11

Bit 11: Multi Drive Status..

P12

Bit 12: Multi Drive Status..

P13

Bit 13: Multi Drive Status..

P14

Bit 14: Multi Drive Status..

P15

Bit 15: Multi Drive Status..

P16

Bit 16: Multi Drive Status..

P17

Bit 17: Multi Drive Status..

P18

Bit 18: Multi Drive Status..

P19

Bit 19: Multi Drive Status..

P20

Bit 20: Multi Drive Status..

P21

Bit 21: Multi Drive Status..

P22

Bit 22: Multi Drive Status..

P23

Bit 23: Multi Drive Status..

P24

Bit 24: Multi Drive Status..

P25

Bit 25: Multi Drive Status..

P26

Bit 26: Multi Drive Status..

P27

Bit 27: Multi Drive Status..

P28

Bit 28: Multi Drive Status..

P29

Bit 29: Multi Drive Status..

P30

Bit 30: Multi Drive Status..

P31

Bit 31: Multi Drive Status..

PUDR

Pull-up Disable Register

Offset: 0x60, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Disable..

P1

Bit 1: Pull Up Disable..

P2

Bit 2: Pull Up Disable..

P3

Bit 3: Pull Up Disable..

P4

Bit 4: Pull Up Disable..

P5

Bit 5: Pull Up Disable..

P6

Bit 6: Pull Up Disable..

P7

Bit 7: Pull Up Disable..

P8

Bit 8: Pull Up Disable..

P9

Bit 9: Pull Up Disable..

P10

Bit 10: Pull Up Disable..

P11

Bit 11: Pull Up Disable..

P12

Bit 12: Pull Up Disable..

P13

Bit 13: Pull Up Disable..

P14

Bit 14: Pull Up Disable..

P15

Bit 15: Pull Up Disable..

P16

Bit 16: Pull Up Disable..

P17

Bit 17: Pull Up Disable..

P18

Bit 18: Pull Up Disable..

P19

Bit 19: Pull Up Disable..

P20

Bit 20: Pull Up Disable..

P21

Bit 21: Pull Up Disable..

P22

Bit 22: Pull Up Disable..

P23

Bit 23: Pull Up Disable..

P24

Bit 24: Pull Up Disable..

P25

Bit 25: Pull Up Disable..

P26

Bit 26: Pull Up Disable..

P27

Bit 27: Pull Up Disable..

P28

Bit 28: Pull Up Disable..

P29

Bit 29: Pull Up Disable..

P30

Bit 30: Pull Up Disable..

P31

Bit 31: Pull Up Disable..

PUER

Pull-up Enable Register

Offset: 0x64, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Pull Up Enable..

P1

Bit 1: Pull Up Enable..

P2

Bit 2: Pull Up Enable..

P3

Bit 3: Pull Up Enable..

P4

Bit 4: Pull Up Enable..

P5

Bit 5: Pull Up Enable..

P6

Bit 6: Pull Up Enable..

P7

Bit 7: Pull Up Enable..

P8

Bit 8: Pull Up Enable..

P9

Bit 9: Pull Up Enable..

P10

Bit 10: Pull Up Enable..

P11

Bit 11: Pull Up Enable..

P12

Bit 12: Pull Up Enable..

P13

Bit 13: Pull Up Enable..

P14

Bit 14: Pull Up Enable..

P15

Bit 15: Pull Up Enable..

P16

Bit 16: Pull Up Enable..

P17

Bit 17: Pull Up Enable..

P18

Bit 18: Pull Up Enable..

P19

Bit 19: Pull Up Enable..

P20

Bit 20: Pull Up Enable..

P21

Bit 21: Pull Up Enable..

P22

Bit 22: Pull Up Enable..

P23

Bit 23: Pull Up Enable..

P24

Bit 24: Pull Up Enable..

P25

Bit 25: Pull Up Enable..

P26

Bit 26: Pull Up Enable..

P27

Bit 27: Pull Up Enable..

P28

Bit 28: Pull Up Enable..

P29

Bit 29: Pull Up Enable..

P30

Bit 30: Pull Up Enable..

P31

Bit 31: Pull Up Enable..

PUSR

Pad Pull-up Status Register

Offset: 0x68, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Pull Up Status..

P1

Bit 1: Pull Up Status..

P2

Bit 2: Pull Up Status..

P3

Bit 3: Pull Up Status..

P4

Bit 4: Pull Up Status..

P5

Bit 5: Pull Up Status..

P6

Bit 6: Pull Up Status..

P7

Bit 7: Pull Up Status..

P8

Bit 8: Pull Up Status..

P9

Bit 9: Pull Up Status..

P10

Bit 10: Pull Up Status..

P11

Bit 11: Pull Up Status..

P12

Bit 12: Pull Up Status..

P13

Bit 13: Pull Up Status..

P14

Bit 14: Pull Up Status..

P15

Bit 15: Pull Up Status..

P16

Bit 16: Pull Up Status..

P17

Bit 17: Pull Up Status..

P18

Bit 18: Pull Up Status..

P19

Bit 19: Pull Up Status..

P20

Bit 20: Pull Up Status..

P21

Bit 21: Pull Up Status..

P22

Bit 22: Pull Up Status..

P23

Bit 23: Pull Up Status..

P24

Bit 24: Pull Up Status..

P25

Bit 25: Pull Up Status..

P26

Bit 26: Pull Up Status..

P27

Bit 27: Pull Up Status..

P28

Bit 28: Pull Up Status..

P29

Bit 29: Pull Up Status..

P30

Bit 30: Pull Up Status..

P31

Bit 31: Pull Up Status..

ABSR

Peripheral AB Select Register

Offset: 0x70, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
rw 		P30
rw 		P29
rw 		P28
rw 		P27
rw 		P26
rw 		P25
rw 		P24
rw 		P23
rw 		P22
rw 		P21
rw 		P20
rw 		P19
rw 		P18
rw 		P17
rw 		P16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
rw 		P14
rw 		P13
rw 		P12
rw 		P11
rw 		P10
rw 		P9
rw 		P8
rw 		P7
rw 		P6
rw 		P5
rw 		P4
rw 		P3
rw 		P2
rw 		P1
rw 		P0
rw
Toggle Fields

P0

Bit 0: Peripheral A Select..

P1

Bit 1: Peripheral A Select..

P2

Bit 2: Peripheral A Select..

P3

Bit 3: Peripheral A Select..

P4

Bit 4: Peripheral A Select..

P5

Bit 5: Peripheral A Select..

P6

Bit 6: Peripheral A Select..

P7

Bit 7: Peripheral A Select..

P8

Bit 8: Peripheral A Select..

P9

Bit 9: Peripheral A Select..

P10

Bit 10: Peripheral A Select..

P11

Bit 11: Peripheral A Select..

P12

Bit 12: Peripheral A Select..

P13

Bit 13: Peripheral A Select..

P14

Bit 14: Peripheral A Select..

P15

Bit 15: Peripheral A Select..

P16

Bit 16: Peripheral A Select..

P17

Bit 17: Peripheral A Select..

P18

Bit 18: Peripheral A Select..

P19

Bit 19: Peripheral A Select..

P20

Bit 20: Peripheral A Select..

P21

Bit 21: Peripheral A Select..

P22

Bit 22: Peripheral A Select..

P23

Bit 23: Peripheral A Select..

P24

Bit 24: Peripheral A Select..

P25

Bit 25: Peripheral A Select..

P26

Bit 26: Peripheral A Select..

P27

Bit 27: Peripheral A Select..

P28

Bit 28: Peripheral A Select..

P29

Bit 29: Peripheral A Select..

P30

Bit 30: Peripheral A Select..

P31

Bit 31: Peripheral A Select..

SCIFSR

System Clock Glitch Input Filter Select Register

Offset: 0x80, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: System Clock Glitch Filtering Select..

P1

Bit 1: System Clock Glitch Filtering Select..

P2

Bit 2: System Clock Glitch Filtering Select..

P3

Bit 3: System Clock Glitch Filtering Select..

P4

Bit 4: System Clock Glitch Filtering Select..

P5

Bit 5: System Clock Glitch Filtering Select..

P6

Bit 6: System Clock Glitch Filtering Select..

P7

Bit 7: System Clock Glitch Filtering Select..

P8

Bit 8: System Clock Glitch Filtering Select..

P9

Bit 9: System Clock Glitch Filtering Select..

P10

Bit 10: System Clock Glitch Filtering Select..

P11

Bit 11: System Clock Glitch Filtering Select..

P12

Bit 12: System Clock Glitch Filtering Select..

P13

Bit 13: System Clock Glitch Filtering Select..

P14

Bit 14: System Clock Glitch Filtering Select..

P15

Bit 15: System Clock Glitch Filtering Select..

P16

Bit 16: System Clock Glitch Filtering Select..

P17

Bit 17: System Clock Glitch Filtering Select..

P18

Bit 18: System Clock Glitch Filtering Select..

P19

Bit 19: System Clock Glitch Filtering Select..

P20

Bit 20: System Clock Glitch Filtering Select..

P21

Bit 21: System Clock Glitch Filtering Select..

P22

Bit 22: System Clock Glitch Filtering Select..

P23

Bit 23: System Clock Glitch Filtering Select..

P24

Bit 24: System Clock Glitch Filtering Select..

P25

Bit 25: System Clock Glitch Filtering Select..

P26

Bit 26: System Clock Glitch Filtering Select..

P27

Bit 27: System Clock Glitch Filtering Select..

P28

Bit 28: System Clock Glitch Filtering Select..

P29

Bit 29: System Clock Glitch Filtering Select..

P30

Bit 30: System Clock Glitch Filtering Select..

P31

Bit 31: System Clock Glitch Filtering Select..

DIFSR

Debouncing Input Filter Select Register

Offset: 0x84, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Debouncing Filtering Select..

P1

Bit 1: Debouncing Filtering Select..

P2

Bit 2: Debouncing Filtering Select..

P3

Bit 3: Debouncing Filtering Select..

P4

Bit 4: Debouncing Filtering Select..

P5

Bit 5: Debouncing Filtering Select..

P6

Bit 6: Debouncing Filtering Select..

P7

Bit 7: Debouncing Filtering Select..

P8

Bit 8: Debouncing Filtering Select..

P9

Bit 9: Debouncing Filtering Select..

P10

Bit 10: Debouncing Filtering Select..

P11

Bit 11: Debouncing Filtering Select..

P12

Bit 12: Debouncing Filtering Select..

P13

Bit 13: Debouncing Filtering Select..

P14

Bit 14: Debouncing Filtering Select..

P15

Bit 15: Debouncing Filtering Select..

P16

Bit 16: Debouncing Filtering Select..

P17

Bit 17: Debouncing Filtering Select..

P18

Bit 18: Debouncing Filtering Select..

P19

Bit 19: Debouncing Filtering Select..

P20

Bit 20: Debouncing Filtering Select..

P21

Bit 21: Debouncing Filtering Select..

P22

Bit 22: Debouncing Filtering Select..

P23

Bit 23: Debouncing Filtering Select..

P24

Bit 24: Debouncing Filtering Select..

P25

Bit 25: Debouncing Filtering Select..

P26

Bit 26: Debouncing Filtering Select..

P27

Bit 27: Debouncing Filtering Select..

P28

Bit 28: Debouncing Filtering Select..

P29

Bit 29: Debouncing Filtering Select..

P30

Bit 30: Debouncing Filtering Select..

P31

Bit 31: Debouncing Filtering Select..

IFDGSR

Glitch or Debouncing Input Filter Clock Selection Status Register

Offset: 0x88, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Glitch or Debouncing Filter Selection Status.

P1

Bit 1: Glitch or Debouncing Filter Selection Status.

P2

Bit 2: Glitch or Debouncing Filter Selection Status.

P3

Bit 3: Glitch or Debouncing Filter Selection Status.

P4

Bit 4: Glitch or Debouncing Filter Selection Status.

P5

Bit 5: Glitch or Debouncing Filter Selection Status.

P6

Bit 6: Glitch or Debouncing Filter Selection Status.

P7

Bit 7: Glitch or Debouncing Filter Selection Status.

P8

Bit 8: Glitch or Debouncing Filter Selection Status.

P9

Bit 9: Glitch or Debouncing Filter Selection Status.

P10

Bit 10: Glitch or Debouncing Filter Selection Status.

P11

Bit 11: Glitch or Debouncing Filter Selection Status.

P12

Bit 12: Glitch or Debouncing Filter Selection Status.

P13

Bit 13: Glitch or Debouncing Filter Selection Status.

P14

Bit 14: Glitch or Debouncing Filter Selection Status.

P15

Bit 15: Glitch or Debouncing Filter Selection Status.

P16

Bit 16: Glitch or Debouncing Filter Selection Status.

P17

Bit 17: Glitch or Debouncing Filter Selection Status.

P18

Bit 18: Glitch or Debouncing Filter Selection Status.

P19

Bit 19: Glitch or Debouncing Filter Selection Status.

P20

Bit 20: Glitch or Debouncing Filter Selection Status.

P21

Bit 21: Glitch or Debouncing Filter Selection Status.

P22

Bit 22: Glitch or Debouncing Filter Selection Status.

P23

Bit 23: Glitch or Debouncing Filter Selection Status.

P24

Bit 24: Glitch or Debouncing Filter Selection Status.

P25

Bit 25: Glitch or Debouncing Filter Selection Status.

P26

Bit 26: Glitch or Debouncing Filter Selection Status.

P27

Bit 27: Glitch or Debouncing Filter Selection Status.

P28

Bit 28: Glitch or Debouncing Filter Selection Status.

P29

Bit 29: Glitch or Debouncing Filter Selection Status.

P30

Bit 30: Glitch or Debouncing Filter Selection Status.

P31

Bit 31: Glitch or Debouncing Filter Selection Status.

SCDR

Slow Clock Divider Debouncing Register

Offset: 0x8c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-13: Slow Clock Divider Selection for Debouncing.

OWER

Output Write Enable

Offset: 0xa0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Enable..

P1

Bit 1: Output Write Enable..

P2

Bit 2: Output Write Enable..

P3

Bit 3: Output Write Enable..

P4

Bit 4: Output Write Enable..

P5

Bit 5: Output Write Enable..

P6

Bit 6: Output Write Enable..

P7

Bit 7: Output Write Enable..

P8

Bit 8: Output Write Enable..

P9

Bit 9: Output Write Enable..

P10

Bit 10: Output Write Enable..

P11

Bit 11: Output Write Enable..

P12

Bit 12: Output Write Enable..

P13

Bit 13: Output Write Enable..

P14

Bit 14: Output Write Enable..

P15

Bit 15: Output Write Enable..

P16

Bit 16: Output Write Enable..

P17

Bit 17: Output Write Enable..

P18

Bit 18: Output Write Enable..

P19

Bit 19: Output Write Enable..

P20

Bit 20: Output Write Enable..

P21

Bit 21: Output Write Enable..

P22

Bit 22: Output Write Enable..

P23

Bit 23: Output Write Enable..

P24

Bit 24: Output Write Enable..

P25

Bit 25: Output Write Enable..

P26

Bit 26: Output Write Enable..

P27

Bit 27: Output Write Enable..

P28

Bit 28: Output Write Enable..

P29

Bit 29: Output Write Enable..

P30

Bit 30: Output Write Enable..

P31

Bit 31: Output Write Enable..

OWDR

Output Write Disable

Offset: 0xa4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Output Write Disable..

P1

Bit 1: Output Write Disable..

P2

Bit 2: Output Write Disable..

P3

Bit 3: Output Write Disable..

P4

Bit 4: Output Write Disable..

P5

Bit 5: Output Write Disable..

P6

Bit 6: Output Write Disable..

P7

Bit 7: Output Write Disable..

P8

Bit 8: Output Write Disable..

P9

Bit 9: Output Write Disable..

P10

Bit 10: Output Write Disable..

P11

Bit 11: Output Write Disable..

P12

Bit 12: Output Write Disable..

P13

Bit 13: Output Write Disable..

P14

Bit 14: Output Write Disable..

P15

Bit 15: Output Write Disable..

P16

Bit 16: Output Write Disable..

P17

Bit 17: Output Write Disable..

P18

Bit 18: Output Write Disable..

P19

Bit 19: Output Write Disable..

P20

Bit 20: Output Write Disable..

P21

Bit 21: Output Write Disable..

P22

Bit 22: Output Write Disable..

P23

Bit 23: Output Write Disable..

P24

Bit 24: Output Write Disable..

P25

Bit 25: Output Write Disable..

P26

Bit 26: Output Write Disable..

P27

Bit 27: Output Write Disable..

P28

Bit 28: Output Write Disable..

P29

Bit 29: Output Write Disable..

P30

Bit 30: Output Write Disable..

P31

Bit 31: Output Write Disable..

OWSR

Output Write Status Register

Offset: 0xa8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Output Write Status..

P1

Bit 1: Output Write Status..

P2

Bit 2: Output Write Status..

P3

Bit 3: Output Write Status..

P4

Bit 4: Output Write Status..

P5

Bit 5: Output Write Status..

P6

Bit 6: Output Write Status..

P7

Bit 7: Output Write Status..

P8

Bit 8: Output Write Status..

P9

Bit 9: Output Write Status..

P10

Bit 10: Output Write Status..

P11

Bit 11: Output Write Status..

P12

Bit 12: Output Write Status..

P13

Bit 13: Output Write Status..

P14

Bit 14: Output Write Status..

P15

Bit 15: Output Write Status..

P16

Bit 16: Output Write Status..

P17

Bit 17: Output Write Status..

P18

Bit 18: Output Write Status..

P19

Bit 19: Output Write Status..

P20

Bit 20: Output Write Status..

P21

Bit 21: Output Write Status..

P22

Bit 22: Output Write Status..

P23

Bit 23: Output Write Status..

P24

Bit 24: Output Write Status..

P25

Bit 25: Output Write Status..

P26

Bit 26: Output Write Status..

P27

Bit 27: Output Write Status..

P28

Bit 28: Output Write Status..

P29

Bit 29: Output Write Status..

P30

Bit 30: Output Write Status..

P31

Bit 31: Output Write Status..

AIMER

Additional Interrupt Modes Enable Register

Offset: 0xb0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Enable..

P1

Bit 1: Additional Interrupt Modes Enable..

P2

Bit 2: Additional Interrupt Modes Enable..

P3

Bit 3: Additional Interrupt Modes Enable..

P4

Bit 4: Additional Interrupt Modes Enable..

P5

Bit 5: Additional Interrupt Modes Enable..

P6

Bit 6: Additional Interrupt Modes Enable..

P7

Bit 7: Additional Interrupt Modes Enable..

P8

Bit 8: Additional Interrupt Modes Enable..

P9

Bit 9: Additional Interrupt Modes Enable..

P10

Bit 10: Additional Interrupt Modes Enable..

P11

Bit 11: Additional Interrupt Modes Enable..

P12

Bit 12: Additional Interrupt Modes Enable..

P13

Bit 13: Additional Interrupt Modes Enable..

P14

Bit 14: Additional Interrupt Modes Enable..

P15

Bit 15: Additional Interrupt Modes Enable..

P16

Bit 16: Additional Interrupt Modes Enable..

P17

Bit 17: Additional Interrupt Modes Enable..

P18

Bit 18: Additional Interrupt Modes Enable..

P19

Bit 19: Additional Interrupt Modes Enable..

P20

Bit 20: Additional Interrupt Modes Enable..

P21

Bit 21: Additional Interrupt Modes Enable..

P22

Bit 22: Additional Interrupt Modes Enable..

P23

Bit 23: Additional Interrupt Modes Enable..

P24

Bit 24: Additional Interrupt Modes Enable..

P25

Bit 25: Additional Interrupt Modes Enable..

P26

Bit 26: Additional Interrupt Modes Enable..

P27

Bit 27: Additional Interrupt Modes Enable..

P28

Bit 28: Additional Interrupt Modes Enable..

P29

Bit 29: Additional Interrupt Modes Enable..

P30

Bit 30: Additional Interrupt Modes Enable..

P31

Bit 31: Additional Interrupt Modes Enable..

AIMDR

Additional Interrupt Modes Disables Register

Offset: 0xb4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Additional Interrupt Modes Disable..

P1

Bit 1: Additional Interrupt Modes Disable..

P2

Bit 2: Additional Interrupt Modes Disable..

P3

Bit 3: Additional Interrupt Modes Disable..

P4

Bit 4: Additional Interrupt Modes Disable..

P5

Bit 5: Additional Interrupt Modes Disable..

P6

Bit 6: Additional Interrupt Modes Disable..

P7

Bit 7: Additional Interrupt Modes Disable..

P8

Bit 8: Additional Interrupt Modes Disable..

P9

Bit 9: Additional Interrupt Modes Disable..

P10

Bit 10: Additional Interrupt Modes Disable..

P11

Bit 11: Additional Interrupt Modes Disable..

P12

Bit 12: Additional Interrupt Modes Disable..

P13

Bit 13: Additional Interrupt Modes Disable..

P14

Bit 14: Additional Interrupt Modes Disable..

P15

Bit 15: Additional Interrupt Modes Disable..

P16

Bit 16: Additional Interrupt Modes Disable..

P17

Bit 17: Additional Interrupt Modes Disable..

P18

Bit 18: Additional Interrupt Modes Disable..

P19

Bit 19: Additional Interrupt Modes Disable..

P20

Bit 20: Additional Interrupt Modes Disable..

P21

Bit 21: Additional Interrupt Modes Disable..

P22

Bit 22: Additional Interrupt Modes Disable..

P23

Bit 23: Additional Interrupt Modes Disable..

P24

Bit 24: Additional Interrupt Modes Disable..

P25

Bit 25: Additional Interrupt Modes Disable..

P26

Bit 26: Additional Interrupt Modes Disable..

P27

Bit 27: Additional Interrupt Modes Disable..

P28

Bit 28: Additional Interrupt Modes Disable..

P29

Bit 29: Additional Interrupt Modes Disable..

P30

Bit 30: Additional Interrupt Modes Disable..

P31

Bit 31: Additional Interrupt Modes Disable..

AIMMR

Additional Interrupt Modes Mask Register

Offset: 0xb8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Peripheral CD Status..

P1

Bit 1: Peripheral CD Status..

P2

Bit 2: Peripheral CD Status..

P3

Bit 3: Peripheral CD Status..

P4

Bit 4: Peripheral CD Status..

P5

Bit 5: Peripheral CD Status..

P6

Bit 6: Peripheral CD Status..

P7

Bit 7: Peripheral CD Status..

P8

Bit 8: Peripheral CD Status..

P9

Bit 9: Peripheral CD Status..

P10

Bit 10: Peripheral CD Status..

P11

Bit 11: Peripheral CD Status..

P12

Bit 12: Peripheral CD Status..

P13

Bit 13: Peripheral CD Status..

P14

Bit 14: Peripheral CD Status..

P15

Bit 15: Peripheral CD Status..

P16

Bit 16: Peripheral CD Status..

P17

Bit 17: Peripheral CD Status..

P18

Bit 18: Peripheral CD Status..

P19

Bit 19: Peripheral CD Status..

P20

Bit 20: Peripheral CD Status..

P21

Bit 21: Peripheral CD Status..

P22

Bit 22: Peripheral CD Status..

P23

Bit 23: Peripheral CD Status..

P24

Bit 24: Peripheral CD Status..

P25

Bit 25: Peripheral CD Status..

P26

Bit 26: Peripheral CD Status..

P27

Bit 27: Peripheral CD Status..

P28

Bit 28: Peripheral CD Status..

P29

Bit 29: Peripheral CD Status..

P30

Bit 30: Peripheral CD Status..

P31

Bit 31: Peripheral CD Status..

ESR

Edge Select Register

Offset: 0xc0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Edge Interrupt Selection..

P1

Bit 1: Edge Interrupt Selection..

P2

Bit 2: Edge Interrupt Selection..

P3

Bit 3: Edge Interrupt Selection..

P4

Bit 4: Edge Interrupt Selection..

P5

Bit 5: Edge Interrupt Selection..

P6

Bit 6: Edge Interrupt Selection..

P7

Bit 7: Edge Interrupt Selection..

P8

Bit 8: Edge Interrupt Selection..

P9

Bit 9: Edge Interrupt Selection..

P10

Bit 10: Edge Interrupt Selection..

P11

Bit 11: Edge Interrupt Selection..

P12

Bit 12: Edge Interrupt Selection..

P13

Bit 13: Edge Interrupt Selection..

P14

Bit 14: Edge Interrupt Selection..

P15

Bit 15: Edge Interrupt Selection..

P16

Bit 16: Edge Interrupt Selection..

P17

Bit 17: Edge Interrupt Selection..

P18

Bit 18: Edge Interrupt Selection..

P19

Bit 19: Edge Interrupt Selection..

P20

Bit 20: Edge Interrupt Selection..

P21

Bit 21: Edge Interrupt Selection..

P22

Bit 22: Edge Interrupt Selection..

P23

Bit 23: Edge Interrupt Selection..

P24

Bit 24: Edge Interrupt Selection..

P25

Bit 25: Edge Interrupt Selection..

P26

Bit 26: Edge Interrupt Selection..

P27

Bit 27: Edge Interrupt Selection..

P28

Bit 28: Edge Interrupt Selection..

P29

Bit 29: Edge Interrupt Selection..

P30

Bit 30: Edge Interrupt Selection..

P31

Bit 31: Edge Interrupt Selection..

LSR

Level Select Register

Offset: 0xc4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Level Interrupt Selection..

P1

Bit 1: Level Interrupt Selection..

P2

Bit 2: Level Interrupt Selection..

P3

Bit 3: Level Interrupt Selection..

P4

Bit 4: Level Interrupt Selection..

P5

Bit 5: Level Interrupt Selection..

P6

Bit 6: Level Interrupt Selection..

P7

Bit 7: Level Interrupt Selection..

P8

Bit 8: Level Interrupt Selection..

P9

Bit 9: Level Interrupt Selection..

P10

Bit 10: Level Interrupt Selection..

P11

Bit 11: Level Interrupt Selection..

P12

Bit 12: Level Interrupt Selection..

P13

Bit 13: Level Interrupt Selection..

P14

Bit 14: Level Interrupt Selection..

P15

Bit 15: Level Interrupt Selection..

P16

Bit 16: Level Interrupt Selection..

P17

Bit 17: Level Interrupt Selection..

P18

Bit 18: Level Interrupt Selection..

P19

Bit 19: Level Interrupt Selection..

P20

Bit 20: Level Interrupt Selection..

P21

Bit 21: Level Interrupt Selection..

P22

Bit 22: Level Interrupt Selection..

P23

Bit 23: Level Interrupt Selection..

P24

Bit 24: Level Interrupt Selection..

P25

Bit 25: Level Interrupt Selection..

P26

Bit 26: Level Interrupt Selection..

P27

Bit 27: Level Interrupt Selection..

P28

Bit 28: Level Interrupt Selection..

P29

Bit 29: Level Interrupt Selection..

P30

Bit 30: Level Interrupt Selection..

P31

Bit 31: Level Interrupt Selection..

ELSR

Edge/Level Status Register

Offset: 0xc8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge/Level Interrupt source selection..

P1

Bit 1: Edge/Level Interrupt source selection..

P2

Bit 2: Edge/Level Interrupt source selection..

P3

Bit 3: Edge/Level Interrupt source selection..

P4

Bit 4: Edge/Level Interrupt source selection..

P5

Bit 5: Edge/Level Interrupt source selection..

P6

Bit 6: Edge/Level Interrupt source selection..

P7

Bit 7: Edge/Level Interrupt source selection..

P8

Bit 8: Edge/Level Interrupt source selection..

P9

Bit 9: Edge/Level Interrupt source selection..

P10

Bit 10: Edge/Level Interrupt source selection..

P11

Bit 11: Edge/Level Interrupt source selection..

P12

Bit 12: Edge/Level Interrupt source selection..

P13

Bit 13: Edge/Level Interrupt source selection..

P14

Bit 14: Edge/Level Interrupt source selection..

P15

Bit 15: Edge/Level Interrupt source selection..

P16

Bit 16: Edge/Level Interrupt source selection..

P17

Bit 17: Edge/Level Interrupt source selection..

P18

Bit 18: Edge/Level Interrupt source selection..

P19

Bit 19: Edge/Level Interrupt source selection..

P20

Bit 20: Edge/Level Interrupt source selection..

P21

Bit 21: Edge/Level Interrupt source selection..

P22

Bit 22: Edge/Level Interrupt source selection..

P23

Bit 23: Edge/Level Interrupt source selection..

P24

Bit 24: Edge/Level Interrupt source selection..

P25

Bit 25: Edge/Level Interrupt source selection..

P26

Bit 26: Edge/Level Interrupt source selection..

P27

Bit 27: Edge/Level Interrupt source selection..

P28

Bit 28: Edge/Level Interrupt source selection..

P29

Bit 29: Edge/Level Interrupt source selection..

P30

Bit 30: Edge/Level Interrupt source selection..

P31

Bit 31: Edge/Level Interrupt source selection..

FELLSR

Falling Edge/Low Level Select Register

Offset: 0xd0, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Falling Edge/Low Level Interrupt Selection..

P1

Bit 1: Falling Edge/Low Level Interrupt Selection..

P2

Bit 2: Falling Edge/Low Level Interrupt Selection..

P3

Bit 3: Falling Edge/Low Level Interrupt Selection..

P4

Bit 4: Falling Edge/Low Level Interrupt Selection..

P5

Bit 5: Falling Edge/Low Level Interrupt Selection..

P6

Bit 6: Falling Edge/Low Level Interrupt Selection..

P7

Bit 7: Falling Edge/Low Level Interrupt Selection..

P8

Bit 8: Falling Edge/Low Level Interrupt Selection..

P9

Bit 9: Falling Edge/Low Level Interrupt Selection..

P10

Bit 10: Falling Edge/Low Level Interrupt Selection..

P11

Bit 11: Falling Edge/Low Level Interrupt Selection..

P12

Bit 12: Falling Edge/Low Level Interrupt Selection..

P13

Bit 13: Falling Edge/Low Level Interrupt Selection..

P14

Bit 14: Falling Edge/Low Level Interrupt Selection..

P15

Bit 15: Falling Edge/Low Level Interrupt Selection..

P16

Bit 16: Falling Edge/Low Level Interrupt Selection..

P17

Bit 17: Falling Edge/Low Level Interrupt Selection..

P18

Bit 18: Falling Edge/Low Level Interrupt Selection..

P19

Bit 19: Falling Edge/Low Level Interrupt Selection..

P20

Bit 20: Falling Edge/Low Level Interrupt Selection..

P21

Bit 21: Falling Edge/Low Level Interrupt Selection..

P22

Bit 22: Falling Edge/Low Level Interrupt Selection..

P23

Bit 23: Falling Edge/Low Level Interrupt Selection..

P24

Bit 24: Falling Edge/Low Level Interrupt Selection..

P25

Bit 25: Falling Edge/Low Level Interrupt Selection..

P26

Bit 26: Falling Edge/Low Level Interrupt Selection..

P27

Bit 27: Falling Edge/Low Level Interrupt Selection..

P28

Bit 28: Falling Edge/Low Level Interrupt Selection..

P29

Bit 29: Falling Edge/Low Level Interrupt Selection..

P30

Bit 30: Falling Edge/Low Level Interrupt Selection..

P31

Bit 31: Falling Edge/Low Level Interrupt Selection..

REHLSR

Rising Edge/ High Level Select Register

Offset: 0xd4, reset: None, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
w 		P30
w 		P29
w 		P28
w 		P27
w 		P26
w 		P25
w 		P24
w 		P23
w 		P22
w 		P21
w 		P20
w 		P19
w 		P18
w 		P17
w 		P16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
w 		P14
w 		P13
w 		P12
w 		P11
w 		P10
w 		P9
w 		P8
w 		P7
w 		P6
w 		P5
w 		P4
w 		P3
w 		P2
w 		P1
w 		P0
w
Toggle Fields

P0

Bit 0: Rising Edge /High Level Interrupt Selection..

P1

Bit 1: Rising Edge /High Level Interrupt Selection..

P2

Bit 2: Rising Edge /High Level Interrupt Selection..

P3

Bit 3: Rising Edge /High Level Interrupt Selection..

P4

Bit 4: Rising Edge /High Level Interrupt Selection..

P5

Bit 5: Rising Edge /High Level Interrupt Selection..

P6

Bit 6: Rising Edge /High Level Interrupt Selection..

P7

Bit 7: Rising Edge /High Level Interrupt Selection..

P8

Bit 8: Rising Edge /High Level Interrupt Selection..

P9

Bit 9: Rising Edge /High Level Interrupt Selection..

P10

Bit 10: Rising Edge /High Level Interrupt Selection..

P11

Bit 11: Rising Edge /High Level Interrupt Selection..

P12

Bit 12: Rising Edge /High Level Interrupt Selection..

P13

Bit 13: Rising Edge /High Level Interrupt Selection..

P14

Bit 14: Rising Edge /High Level Interrupt Selection..

P15

Bit 15: Rising Edge /High Level Interrupt Selection..

P16

Bit 16: Rising Edge /High Level Interrupt Selection..

P17

Bit 17: Rising Edge /High Level Interrupt Selection..

P18

Bit 18: Rising Edge /High Level Interrupt Selection..

P19

Bit 19: Rising Edge /High Level Interrupt Selection..

P20

Bit 20: Rising Edge /High Level Interrupt Selection..

P21

Bit 21: Rising Edge /High Level Interrupt Selection..

P22

Bit 22: Rising Edge /High Level Interrupt Selection..

P23

Bit 23: Rising Edge /High Level Interrupt Selection..

P24

Bit 24: Rising Edge /High Level Interrupt Selection..

P25

Bit 25: Rising Edge /High Level Interrupt Selection..

P26

Bit 26: Rising Edge /High Level Interrupt Selection..

P27

Bit 27: Rising Edge /High Level Interrupt Selection..

P28

Bit 28: Rising Edge /High Level Interrupt Selection..

P29

Bit 29: Rising Edge /High Level Interrupt Selection..

P30

Bit 30: Rising Edge /High Level Interrupt Selection..

P31

Bit 31: Rising Edge /High Level Interrupt Selection..

FRLHSR

Fall/Rise - Low/High Status Register

Offset: 0xd8, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Edge /Level Interrupt Source Selection..

P1

Bit 1: Edge /Level Interrupt Source Selection..

P2

Bit 2: Edge /Level Interrupt Source Selection..

P3

Bit 3: Edge /Level Interrupt Source Selection..

P4

Bit 4: Edge /Level Interrupt Source Selection..

P5

Bit 5: Edge /Level Interrupt Source Selection..

P6

Bit 6: Edge /Level Interrupt Source Selection..

P7

Bit 7: Edge /Level Interrupt Source Selection..

P8

Bit 8: Edge /Level Interrupt Source Selection..

P9

Bit 9: Edge /Level Interrupt Source Selection..

P10

Bit 10: Edge /Level Interrupt Source Selection..

P11

Bit 11: Edge /Level Interrupt Source Selection..

P12

Bit 12: Edge /Level Interrupt Source Selection..

P13

Bit 13: Edge /Level Interrupt Source Selection..

P14

Bit 14: Edge /Level Interrupt Source Selection..

P15

Bit 15: Edge /Level Interrupt Source Selection..

P16

Bit 16: Edge /Level Interrupt Source Selection..

P17

Bit 17: Edge /Level Interrupt Source Selection..

P18

Bit 18: Edge /Level Interrupt Source Selection..

P19

Bit 19: Edge /Level Interrupt Source Selection..

P20

Bit 20: Edge /Level Interrupt Source Selection..

P21

Bit 21: Edge /Level Interrupt Source Selection..

P22

Bit 22: Edge /Level Interrupt Source Selection..

P23

Bit 23: Edge /Level Interrupt Source Selection..

P24

Bit 24: Edge /Level Interrupt Source Selection..

P25

Bit 25: Edge /Level Interrupt Source Selection..

P26

Bit 26: Edge /Level Interrupt Source Selection..

P27

Bit 27: Edge /Level Interrupt Source Selection..

P28

Bit 28: Edge /Level Interrupt Source Selection..

P29

Bit 29: Edge /Level Interrupt Source Selection..

P30

Bit 30: Edge /Level Interrupt Source Selection..

P31

Bit 31: Edge /Level Interrupt Source Selection..

LOCKSR

Lock Status

Offset: 0xe0, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31
r 		P30
r 		P29
r 		P28
r 		P27
r 		P26
r 		P25
r 		P24
r 		P23
r 		P22
r 		P21
r 		P20
r 		P19
r 		P18
r 		P17
r 		P16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15
r 		P14
r 		P13
r 		P12
r 		P11
r 		P10
r 		P9
r 		P8
r 		P7
r 		P6
r 		P5
r 		P4
r 		P3
r 		P2
r 		P1
r 		P0
r
Toggle Fields

P0

Bit 0: Lock Status..

P1

Bit 1: Lock Status..

P2

Bit 2: Lock Status..

P3

Bit 3: Lock Status..

P4

Bit 4: Lock Status..

P5

Bit 5: Lock Status..

P6

Bit 6: Lock Status..

P7

Bit 7: Lock Status..

P8

Bit 8: Lock Status..

P9

Bit 9: Lock Status..

P10

Bit 10: Lock Status..

P11

Bit 11: Lock Status..

P12

Bit 12: Lock Status..

P13

Bit 13: Lock Status..

P14

Bit 14: Lock Status..

P15

Bit 15: Lock Status..

P16

Bit 16: Lock Status..

P17

Bit 17: Lock Status..

P18

Bit 18: Lock Status..

P19

Bit 19: Lock Status..

P20

Bit 20: Lock Status..

P21

Bit 21: Lock Status..

P22

Bit 22: Lock Status..

P23

Bit 23: Lock Status..

P24

Bit 24: Lock Status..

P25

Bit 25: Lock Status..

P26

Bit 26: Lock Status..

P27

Bit 27: Lock Status..

P28

Bit 28: Lock Status..

P29

Bit 29: Lock Status..

P30

Bit 30: Lock Status..

P31

Bit 31: Lock Status..

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

PMC

0x400e0600: Power Management Controller

80/239 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PMC_SCER
0x4 PMC_SCDR
0x8 PMC_SCSR
0x10 PMC_PCER0
0x14 PMC_PCDR0
0x18 PMC_PCSR0
0x1c CKGR_UCKR
0x20 CKGR_MOR
0x24 CKGR_MCFR
0x28 CKGR_PLLAR
0x30 PMC_MCKR
0x38 PMC_USB
0x40 PMC_PCK[[0]]
0x44 PMC_PCK[[1]]
0x48 PMC_PCK[[2]]
0x60 PMC_IER
0x64 PMC_IDR
0x68 PMC_SR
0x6c PMC_IMR
0x70 PMC_FSMR
0x74 PMC_FSPR
0x78 PMC_FOCR
0xe4 PMC_WPMR
0xe8 PMC_WPSR
0x100 PMC_PCER1
0x104 PMC_PCDR1
0x108 PMC_PCSR1
0x10c PMC_PCR

PMC_SCER

System Clock Enable Register

Offset: 0x0, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCK2
w 		PCK1
w 		PCK0
w 		UOTGCLK
w
Toggle Fields

UOTGCLK

Bit 5: Enable USB OTG Clock (48 MHz, USB_48M) for UTMI.

PCK0

Bit 8: Programmable Clock 0 Output Enable.

PCK1

Bit 9: Programmable Clock 1 Output Enable.

PCK2

Bit 10: Programmable Clock 2 Output Enable.

PMC_SCDR

System Clock Disable Register

Offset: 0x4, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCK2
w 		PCK1
w 		PCK0
w 		UOTGCLK
w
Toggle Fields

UOTGCLK

Bit 5: Disable USB OTG Clock (48 MHz, USB_48M) for UTMI.

PCK0

Bit 8: Programmable Clock 0 Output Disable.

PCK1

Bit 9: Programmable Clock 1 Output Disable.

PCK2

Bit 10: Programmable Clock 2 Output Disable.

PMC_SCSR

System Clock Status Register

Offset: 0x8, reset: 0x00000001, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCK2
r 		PCK1
r 		PCK0
r 		UOTGCLK
r
Toggle Fields

UOTGCLK

Bit 5: USB OTG Clock (48 MHz, USB_48M) Clock Status.

PCK0

Bit 8: Programmable Clock 0 Output Status.

PCK1

Bit 9: Programmable Clock 1 Output Status.

PCK2

Bit 10: Programmable Clock 2 Output Status.

PMC_PCER0

Peripheral Clock Enable Register 0

Offset: 0x10, reset: None, access: write-only

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID31
w 		PID30
w 		PID29
w 		PID28
w 		PID27
w 		PID26
w 		PID25
w 		PID24
w 		PID23
w 		PID22
w 		PID21
w 		PID20
w 		PID19
w 		PID18
w 		PID17
w 		PID16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID15
w 		PID14
w 		PID13
w 		PID12
w 		PID11
w 		PID10
w 		PID9
w 		PID8
w
Toggle Fields

PID8

Bit 8: Peripheral Clock 8 Enable.

PID9

Bit 9: Peripheral Clock 9 Enable.

PID10

Bit 10: Peripheral Clock 10 Enable.

PID11

Bit 11: Peripheral Clock 11 Enable.

PID12

Bit 12: Peripheral Clock 12 Enable.

PID13

Bit 13: Peripheral Clock 13 Enable.

PID14

Bit 14: Peripheral Clock 14 Enable.

PID15

Bit 15: Peripheral Clock 15 Enable.

PID16

Bit 16: Peripheral Clock 16 Enable.

PID17

Bit 17: Peripheral Clock 17 Enable.

PID18

Bit 18: Peripheral Clock 18 Enable.

PID19

Bit 19: Peripheral Clock 19 Enable.

PID20

Bit 20: Peripheral Clock 20 Enable.

PID21

Bit 21: Peripheral Clock 21 Enable.

PID22

Bit 22: Peripheral Clock 22 Enable.

PID23

Bit 23: Peripheral Clock 23 Enable.

PID24

Bit 24: Peripheral Clock 24 Enable.

PID25

Bit 25: Peripheral Clock 25 Enable.

PID26

Bit 26: Peripheral Clock 26 Enable.

PID27

Bit 27: Peripheral Clock 27 Enable.

PID28

Bit 28: Peripheral Clock 28 Enable.

PID29

Bit 29: Peripheral Clock 29 Enable.

PID30

Bit 30: Peripheral Clock 30 Enable.

PID31

Bit 31: Peripheral Clock 31 Enable.

PMC_PCDR0

Peripheral Clock Disable Register 0

Offset: 0x14, reset: None, access: write-only

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID31
w 		PID30
w 		PID29
w 		PID28
w 		PID27
w 		PID26
w 		PID25
w 		PID24
w 		PID23
w 		PID22
w 		PID21
w 		PID20
w 		PID19
w 		PID18
w 		PID17
w 		PID16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID15
w 		PID14
w 		PID13
w 		PID12
w 		PID11
w 		PID10
w 		PID9
w 		PID8
w
Toggle Fields

PID8

Bit 8: Peripheral Clock 8 Disable.

PID9

Bit 9: Peripheral Clock 9 Disable.

PID10

Bit 10: Peripheral Clock 10 Disable.

PID11

Bit 11: Peripheral Clock 11 Disable.

PID12

Bit 12: Peripheral Clock 12 Disable.

PID13

Bit 13: Peripheral Clock 13 Disable.

PID14

Bit 14: Peripheral Clock 14 Disable.

PID15

Bit 15: Peripheral Clock 15 Disable.

PID16

Bit 16: Peripheral Clock 16 Disable.

PID17

Bit 17: Peripheral Clock 17 Disable.

PID18

Bit 18: Peripheral Clock 18 Disable.

PID19

Bit 19: Peripheral Clock 19 Disable.

PID20

Bit 20: Peripheral Clock 20 Disable.

PID21

Bit 21: Peripheral Clock 21 Disable.

PID22

Bit 22: Peripheral Clock 22 Disable.

PID23

Bit 23: Peripheral Clock 23 Disable.

PID24

Bit 24: Peripheral Clock 24 Disable.

PID25

Bit 25: Peripheral Clock 25 Disable.

PID26

Bit 26: Peripheral Clock 26 Disable.

PID27

Bit 27: Peripheral Clock 27 Disable.

PID28

Bit 28: Peripheral Clock 28 Disable.

PID29

Bit 29: Peripheral Clock 29 Disable.

PID30

Bit 30: Peripheral Clock 30 Disable.

PID31

Bit 31: Peripheral Clock 31 Disable.

PMC_PCSR0

Peripheral Clock Status Register 0

Offset: 0x18, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID31
r 		PID30
r 		PID29
r 		PID28
r 		PID27
r 		PID26
r 		PID25
r 		PID24
r 		PID23
r 		PID22
r 		PID21
r 		PID20
r 		PID19
r 		PID18
r 		PID17
r 		PID16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID15
r 		PID14
r 		PID13
r 		PID12
r 		PID11
r 		PID10
r 		PID9
r 		PID8
r
Toggle Fields

PID8

Bit 8: Peripheral Clock 8 Status.

PID9

Bit 9: Peripheral Clock 9 Status.

PID10

Bit 10: Peripheral Clock 10 Status.

PID11

Bit 11: Peripheral Clock 11 Status.

PID12

Bit 12: Peripheral Clock 12 Status.

PID13

Bit 13: Peripheral Clock 13 Status.

PID14

Bit 14: Peripheral Clock 14 Status.

PID15

Bit 15: Peripheral Clock 15 Status.

PID16

Bit 16: Peripheral Clock 16 Status.

PID17

Bit 17: Peripheral Clock 17 Status.

PID18

Bit 18: Peripheral Clock 18 Status.

PID19

Bit 19: Peripheral Clock 19 Status.

PID20

Bit 20: Peripheral Clock 20 Status.

PID21

Bit 21: Peripheral Clock 21 Status.

PID22

Bit 22: Peripheral Clock 22 Status.

PID23

Bit 23: Peripheral Clock 23 Status.

PID24

Bit 24: Peripheral Clock 24 Status.

PID25

Bit 25: Peripheral Clock 25 Status.

PID26

Bit 26: Peripheral Clock 26 Status.

PID27

Bit 27: Peripheral Clock 27 Status.

PID28

Bit 28: Peripheral Clock 28 Status.

PID29

Bit 29: Peripheral Clock 29 Status.

PID30

Bit 30: Peripheral Clock 30 Status.

PID31

Bit 31: Peripheral Clock 31 Status.

CKGR_UCKR

UTMI Clock Register

Offset: 0x1c, reset: 0x10200800, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPLLCOUNT
rw 		UPLLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

UPLLEN

Bit 16: UTMI PLL Enable.

UPLLCOUNT

Bits 20-23: UTMI PLL Start-up Time.

CKGR_MOR

Main Oscillator Register

Offset: 0x20, reset: 0x00000008, access: read-write

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFDEN
rw 		MOSCSEL
rw 		KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOSCXTST
rw 		MOSCRCF
rw 		MOSCRCEN
rw 		MOSCXTBY
rw 		MOSCXTEN
rw
Toggle Fields

MOSCXTEN

Bit 0: Main Crystal Oscillator Enable.

MOSCXTBY

Bit 1: Main Crystal Oscillator Bypass.

MOSCRCEN

Bit 3: Main On-Chip RC Oscillator Enable.

MOSCRCF

Bits 4-6: Main On-Chip RC Oscillator Frequency Selection.

Allowed values:
0x0: 4_MHz: The Fast RC Oscillator Frequency is at 4 MHz (default)
0x1: 8_MHz: The Fast RC Oscillator Frequency is at 8 MHz
0x2: 12_MHz: The Fast RC Oscillator Frequency is at 12 MHz

MOSCXTST

Bits 8-15: Main Crystal Oscillator Start-up Time.

KEY

Bits 16-23: Write Access Password.

Allowed values:
0x37: PASSWD: Writing any other value in this field aborts the write operation.Always reads as 0.

MOSCSEL

Bit 24: Main Oscillator Selection.

CFDEN

Bit 25: Clock Failure Detector Enable.

CKGR_MCFR

Main Clock Frequency Register

Offset: 0x24, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAINFRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAINF
r
Toggle Fields

MAINF

Bits 0-15: Main Clock Frequency.

MAINFRDY

Bit 16: Main Clock Ready.

CKGR_PLLAR

PLLA Register

Offset: 0x28, reset: 0x00003F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ONE
rw 		MULA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLACOUNT
rw 		DIVA
rw
Toggle Fields

DIVA

Bits 0-7: Divider.

PLLACOUNT

Bits 8-13: PLLA Counter.

MULA

Bits 16-26: PLLA Multiplier.

ONE

Bit 29: Must Be Set to 1.

PMC_MCKR

Master Clock Register

Offset: 0x30, reset: 0x00000001, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPLLDIV2
rw 		PLLADIV2
rw 		PRES
rw 		CSS
rw
Toggle Fields

CSS

Bits 0-1: Master Clock Source Selection.

Allowed values:
0x0: SLOW_CLK: Slow Clock is selected
0x1: MAIN_CLK: Main Clock is selected
0x2: PLLA_CLK: PLLA Clock is selected
0x3: UPLL_CLK: UPLL Clock is selected

PRES

Bits 4-6: Processor Clock Prescaler.

Allowed values:
0x0: CLK_1: Selected clock
0x1: CLK_2: Selected clock divided by 2
0x2: CLK_4: Selected clock divided by 4
0x3: CLK_8: Selected clock divided by 8
0x4: CLK_16: Selected clock divided by 16
0x5: CLK_32: Selected clock divided by 32
0x6: CLK_64: Selected clock divided by 64
0x7: CLK_3: Selected clock divided by 3

PLLADIV2

Bit 12: PLLA Divisor by 2.

UPLLDIV2

Bit 13: None.

PMC_USB

USB Clock Register

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBDIV
rw 		USBS
rw
Toggle Fields

USBS

Bit 0: USB Input Clock Selection.

USBDIV

Bits 8-11: Divider for USB Clock..

PMC_PCK[[0]]

Programmable Clock 0 Register

Offset: 0x40, reset: None, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRES
rw 		CSS
rw
Toggle Fields

CSS

Bits 0-2: Master Clock Source Selection.

Allowed values:
0x0: SLOW_CLK: Slow Clock is selected
0x1: MAIN_CLK: Main Clock is selected
0x2: PLLA_CLK: PLLA Clock is selected
0x3: UPLL_CLK: UPLL Clock is selected
0x4: MCK: Master Clock is selected

PRES

Bits 4-6: Programmable Clock Prescaler.

Allowed values:
0x0: CLK_1: Selected clock
0x1: CLK_2: Selected clock divided by 2
0x2: CLK_4: Selected clock divided by 4
0x3: CLK_8: Selected clock divided by 8
0x4: CLK_16: Selected clock divided by 16
0x5: CLK_32: Selected clock divided by 32
0x6: CLK_64: Selected clock divided by 64

PMC_PCK[[1]]

Programmable Clock 0 Register

Offset: 0x44, reset: None, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRES
rw 		CSS
rw
Toggle Fields

CSS

Bits 0-2: Master Clock Source Selection.

Allowed values:
0x0: SLOW_CLK: Slow Clock is selected
0x1: MAIN_CLK: Main Clock is selected
0x2: PLLA_CLK: PLLA Clock is selected
0x3: UPLL_CLK: UPLL Clock is selected
0x4: MCK: Master Clock is selected

PRES

Bits 4-6: Programmable Clock Prescaler.

Allowed values:
0x0: CLK_1: Selected clock
0x1: CLK_2: Selected clock divided by 2
0x2: CLK_4: Selected clock divided by 4
0x3: CLK_8: Selected clock divided by 8
0x4: CLK_16: Selected clock divided by 16
0x5: CLK_32: Selected clock divided by 32
0x6: CLK_64: Selected clock divided by 64

PMC_PCK[[2]]

Programmable Clock 0 Register

Offset: 0x48, reset: None, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRES
rw 		CSS
rw
Toggle Fields

CSS

Bits 0-2: Master Clock Source Selection.

Allowed values:
0x0: SLOW_CLK: Slow Clock is selected
0x1: MAIN_CLK: Main Clock is selected
0x2: PLLA_CLK: PLLA Clock is selected
0x3: UPLL_CLK: UPLL Clock is selected
0x4: MCK: Master Clock is selected

PRES

Bits 4-6: Programmable Clock Prescaler.

Allowed values:
0x0: CLK_1: Selected clock
0x1: CLK_2: Selected clock divided by 2
0x2: CLK_4: Selected clock divided by 4
0x3: CLK_8: Selected clock divided by 8
0x4: CLK_16: Selected clock divided by 16
0x5: CLK_32: Selected clock divided by 32
0x6: CLK_64: Selected clock divided by 64

PMC_IER

Interrupt Enable Register

Offset: 0x60, reset: None, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFDEV
w 		MOSCRCS
w 		MOSCSELS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCKRDY2
w 		PCKRDY1
w 		PCKRDY0
w 		LOCKU
w 		MCKRDY
w 		LOCKA
w 		MOSCXTS
w
Toggle Fields

MOSCXTS

Bit 0: Main Crystal Oscillator Status Interrupt Enable.

LOCKA

Bit 1: PLLA Lock Interrupt Enable.

MCKRDY

Bit 3: Master Clock Ready Interrupt Enable.

LOCKU

Bit 6: UTMI PLL Lock Interrupt Enable.

PCKRDY0

Bit 8: Programmable Clock Ready 0 Interrupt Enable.

PCKRDY1

Bit 9: Programmable Clock Ready 1 Interrupt Enable.

PCKRDY2

Bit 10: Programmable Clock Ready 2 Interrupt Enable.

MOSCSELS

Bit 16: Main Oscillator Selection Status Interrupt Enable.

MOSCRCS

Bit 17: Main On-Chip RC Status Interrupt Enable.

CFDEV

Bit 18: Clock Failure Detector Event Interrupt Enable.

PMC_IDR

Interrupt Disable Register

Offset: 0x64, reset: None, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFDEV
w 		MOSCRCS
w 		MOSCSELS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCKRDY2
w 		PCKRDY1
w 		PCKRDY0
w 		LOCKU
w 		MCKRDY
w 		LOCKA
w 		MOSCXTS
w
Toggle Fields

MOSCXTS

Bit 0: Main Crystal Oscillator Status Interrupt Disable.

LOCKA

Bit 1: PLLA Lock Interrupt Disable.

MCKRDY

Bit 3: Master Clock Ready Interrupt Disable.

LOCKU

Bit 6: UTMI PLL Lock Interrupt Disable.

PCKRDY0

Bit 8: Programmable Clock Ready 0 Interrupt Disable.

PCKRDY1

Bit 9: Programmable Clock Ready 1 Interrupt Disable.

PCKRDY2

Bit 10: Programmable Clock Ready 2 Interrupt Disable.

MOSCSELS

Bit 16: Main Oscillator Selection Status Interrupt Disable.

MOSCRCS

Bit 17: Main On-Chip RC Status Interrupt Disable.

CFDEV

Bit 18: Clock Failure Detector Event Interrupt Disable.

PMC_SR

Status Register

Offset: 0x68, reset: 0x00010008, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FOS
r 		CFDS
r 		CFDEV
r 		MOSCRCS
r 		MOSCSELS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCKRDY2
r 		PCKRDY1
r 		PCKRDY0
r 		OSCSELS
r 		LOCKU
r 		MCKRDY
r 		LOCKA
r 		MOSCXTS
r
Toggle Fields

MOSCXTS

Bit 0: Main XTAL Oscillator Status.

LOCKA

Bit 1: PLLA Lock Status.

MCKRDY

Bit 3: Master Clock Status.

LOCKU

Bit 6: UTMI PLL Lock Status.

OSCSELS

Bit 7: Slow Clock Oscillator Selection.

PCKRDY0

Bit 8: Programmable Clock Ready Status.

PCKRDY1

Bit 9: Programmable Clock Ready Status.

PCKRDY2

Bit 10: Programmable Clock Ready Status.

MOSCSELS

Bit 16: Main Oscillator Selection Status.

MOSCRCS

Bit 17: Main On-Chip RC Oscillator Status.

CFDEV

Bit 18: Clock Failure Detector Event.

CFDS

Bit 19: Clock Failure Detector Status.

FOS

Bit 20: Clock Failure Detector Fault Output Status.

PMC_IMR

Interrupt Mask Register

Offset: 0x6c, reset: 0x00000000, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFDEV
r 		MOSCRCS
r 		MOSCSELS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCKRDY2
r 		PCKRDY1
r 		PCKRDY0
r 		LOCKU
r 		MCKRDY
r 		LOCKA
r 		MOSCXTS
r
Toggle Fields

MOSCXTS

Bit 0: Main Crystal Oscillator Status Interrupt Mask.

LOCKA

Bit 1: PLLA Lock Interrupt Mask.

MCKRDY

Bit 3: Master Clock Ready Interrupt Mask.

LOCKU

Bit 6: UTMI PLL Lock Interrupt Mask.

PCKRDY0

Bit 8: Programmable Clock Ready 0 Interrupt Mask.

PCKRDY1

Bit 9: Programmable Clock Ready 1 Interrupt Mask.

PCKRDY2

Bit 10: Programmable Clock Ready 2 Interrupt Mask.

MOSCSELS

Bit 16: Main Oscillator Selection Status Interrupt Mask.

MOSCRCS

Bit 17: Main On-Chip RC Status Interrupt Mask.

CFDEV

Bit 18: Clock Failure Detector Event Interrupt Mask.

PMC_FSMR

Fast Start-up Mode Register

Offset: 0x70, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPM
rw 		USBAL
rw 		RTCAL
rw 		RTTAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSTT15
rw 		FSTT14
rw 		FSTT13
rw 		FSTT12
rw 		FSTT11
rw 		FSTT10
rw 		FSTT9
rw 		FSTT8
rw 		FSTT7
rw 		FSTT6
rw 		FSTT5
rw 		FSTT4
rw 		FSTT3
rw 		FSTT2
rw 		FSTT1
rw 		FSTT0
rw
Toggle Fields

FSTT0

Bit 0: Fast Start-up Input Enable 0.

FSTT1

Bit 1: Fast Start-up Input Enable 1.

FSTT2

Bit 2: Fast Start-up Input Enable 2.

FSTT3

Bit 3: Fast Start-up Input Enable 3.

FSTT4

Bit 4: Fast Start-up Input Enable 4.

FSTT5

Bit 5: Fast Start-up Input Enable 5.

FSTT6

Bit 6: Fast Start-up Input Enable 6.

FSTT7

Bit 7: Fast Start-up Input Enable 7.

FSTT8

Bit 8: Fast Start-up Input Enable 8.

FSTT9

Bit 9: Fast Start-up Input Enable 9.

FSTT10

Bit 10: Fast Start-up Input Enable 10.

FSTT11

Bit 11: Fast Start-up Input Enable 11.

FSTT12

Bit 12: Fast Start-up Input Enable 12.

FSTT13

Bit 13: Fast Start-up Input Enable 13.

FSTT14

Bit 14: Fast Start-up Input Enable 14.

FSTT15

Bit 15: Fast Start-up Input Enable 15.

RTTAL

Bit 16: RTT Alarm Enable.

RTCAL

Bit 17: RTC Alarm Enable.

USBAL

Bit 18: USB Alarm Enable.

LPM

Bit 20: Low Power Mode.

PMC_FSPR

Fast Start-up Polarity Register

Offset: 0x74, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSTP15
rw 		FSTP14
rw 		FSTP13
rw 		FSTP12
rw 		FSTP11
rw 		FSTP10
rw 		FSTP9
rw 		FSTP8
rw 		FSTP7
rw 		FSTP6
rw 		FSTP5
rw 		FSTP4
rw 		FSTP3
rw 		FSTP2
rw 		FSTP1
rw 		FSTP0
rw
Toggle Fields

FSTP0

Bit 0: Fast Start-up Input Polarityx.

FSTP1

Bit 1: Fast Start-up Input Polarityx.

FSTP2

Bit 2: Fast Start-up Input Polarityx.

FSTP3

Bit 3: Fast Start-up Input Polarityx.

FSTP4

Bit 4: Fast Start-up Input Polarityx.

FSTP5

Bit 5: Fast Start-up Input Polarityx.

FSTP6

Bit 6: Fast Start-up Input Polarityx.

FSTP7

Bit 7: Fast Start-up Input Polarityx.

FSTP8

Bit 8: Fast Start-up Input Polarityx.

FSTP9

Bit 9: Fast Start-up Input Polarityx.

FSTP10

Bit 10: Fast Start-up Input Polarityx.

FSTP11

Bit 11: Fast Start-up Input Polarityx.

FSTP12

Bit 12: Fast Start-up Input Polarityx.

FSTP13

Bit 13: Fast Start-up Input Polarityx.

FSTP14

Bit 14: Fast Start-up Input Polarityx.

FSTP15

Bit 15: Fast Start-up Input Polarityx.

PMC_FOCR

Fault Output Clear Register

Offset: 0x78, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FOCLR
w
Toggle Fields

FOCLR

Bit 0: Fault Output Clear.

PMC_WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x504D43: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

PMC_WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protect Violation Status.

WPVSRC

Bits 8-23: Write Protect Violation Source.

PMC_PCER1

Peripheral Clock Enable Register 1

Offset: 0x100, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID44
w 		PID43
w 		PID42
w 		PID41
w 		PID40
w 		PID39
w 		PID38
w 		PID37
w 		PID36
w 		PID35
w 		PID34
w 		PID33
w 		PID32
w
Toggle Fields

PID32

Bit 0: Peripheral Clock 32 Enable.

PID33

Bit 1: Peripheral Clock 33 Enable.

PID34

Bit 2: Peripheral Clock 34 Enable.

PID35

Bit 3: Peripheral Clock 35 Enable.

PID36

Bit 4: Peripheral Clock 36 Enable.

PID37

Bit 5: Peripheral Clock 37 Enable.

PID38

Bit 6: Peripheral Clock 38 Enable.

PID39

Bit 7: Peripheral Clock 39 Enable.

PID40

Bit 8: Peripheral Clock 40 Enable.

PID41

Bit 9: Peripheral Clock 41 Enable.

PID42

Bit 10: Peripheral Clock 42 Enable.

PID43

Bit 11: Peripheral Clock 43 Enable.

PID44

Bit 12: Peripheral Clock 44 Enable.

PMC_PCDR1

Peripheral Clock Disable Register 1

Offset: 0x104, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID44
w 		PID43
w 		PID42
w 		PID41
w 		PID40
w 		PID39
w 		PID38
w 		PID37
w 		PID36
w 		PID35
w 		PID34
w 		PID33
w 		PID32
w
Toggle Fields

PID32

Bit 0: Peripheral Clock 32 Disable.

PID33

Bit 1: Peripheral Clock 33 Disable.

PID34

Bit 2: Peripheral Clock 34 Disable.

PID35

Bit 3: Peripheral Clock 35 Disable.

PID36

Bit 4: Peripheral Clock 36 Disable.

PID37

Bit 5: Peripheral Clock 37 Disable.

PID38

Bit 6: Peripheral Clock 38 Disable.

PID39

Bit 7: Peripheral Clock 39 Disable.

PID40

Bit 8: Peripheral Clock 40 Disable.

PID41

Bit 9: Peripheral Clock 41 Disable.

PID42

Bit 10: Peripheral Clock 42 Disable.

PID43

Bit 11: Peripheral Clock 43 Disable.

PID44

Bit 12: Peripheral Clock 44 Disable.

PMC_PCSR1

Peripheral Clock Status Register 1

Offset: 0x108, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID44
r 		PID43
r 		PID42
r 		PID41
r 		PID40
r 		PID39
r 		PID38
r 		PID37
r 		PID36
r 		PID35
r 		PID34
r 		PID33
r 		PID32
r
Toggle Fields

PID32

Bit 0: Peripheral Clock 32 Status.

PID33

Bit 1: Peripheral Clock 33 Status.

PID34

Bit 2: Peripheral Clock 34 Status.

PID35

Bit 3: Peripheral Clock 35 Status.

PID36

Bit 4: Peripheral Clock 36 Status.

PID37

Bit 5: Peripheral Clock 37 Status.

PID38

Bit 6: Peripheral Clock 38 Status.

PID39

Bit 7: Peripheral Clock 39 Status.

PID40

Bit 8: Peripheral Clock 40 Status.

PID41

Bit 9: Peripheral Clock 41 Status.

PID42

Bit 10: Peripheral Clock 42 Status.

PID43

Bit 11: Peripheral Clock 43 Status.

PID44

Bit 12: Peripheral Clock 44 Status.

PMC_PCR

Peripheral Control Register

Offset: 0x10c, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN
rw 		DIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD
rw 		PID
rw
Toggle Fields

PID

Bits 0-5: Peripheral ID.

CMD

Bit 12: Command.

DIV

Bits 16-17: Divisor Value.

Allowed values:
0x0: PERIPH_DIV_MCK: Peripheral clock is MCK
0x1: PERIPH_DIV2_MCK: Peripheral clock is MCK/2
0x2: PERIPH_DIV4_MCK: Peripheral clock is MCK/4

EN

Bit 28: Enable.

PWM

0x40094000: Pulse Width Modulation Controller

115/609 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CLK
0x4 ENA
0x8 DIS
0xc SR
0x10 IER1
0x14 IDR1
0x18 IMR1
0x1c ISR1
0x20 SCM
0x28 SCUC
0x2c SCUP
0x30 SCUPUPD
0x34 IER2
0x38 IDR2
0x3c IMR2
0x40 ISR2
0x44 OOV
0x48 OS
0x4c OSS
0x50 OSC
0x54 OSSUPD
0x58 OSCUPD
0x5c FMR
0x60 FSR
0x64 FCR
0x68 FPV
0x6c FPE1
0x70 FPE2
0x7c ELMR[[0]]
0x80 ELMR[[1]]
0xb0 SMMR
0xe4 WPCR
0xe8 WPSR
0x108 TPR
0x10c TCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR
0x130 CMPV0
0x134 CMPVUPD0
0x138 CMPM0
0x13c CMPMUPD0
0x140 CMPV1
0x144 CMPVUPD1
0x148 CMPM1
0x14c CMPMUPD1
0x150 CMPV2
0x154 CMPVUPD2
0x158 CMPM2
0x15c CMPMUPD2
0x160 CMPV3
0x164 CMPVUPD3
0x168 CMPM3
0x16c CMPMUPD3
0x170 CMPV4
0x174 CMPVUPD4
0x178 CMPM4
0x17c CMPMUPD4
0x180 CMPV5
0x184 CMPVUPD5
0x188 CMPM5
0x18c CMPMUPD5
0x190 CMPV6
0x194 CMPVUPD6
0x198 CMPM6
0x19c CMPMUPD6
0x1a0 CMPV7
0x1a4 CMPVUPD7
0x1a8 CMPM7
0x1ac CMPMUPD7
0x200 CMR0
0x204 CDTY0
0x208 CDTYUPD0
0x20c CPRD0
0x210 CPRDUPD0
0x214 CCNT0
0x218 DT0
0x21c DTUPD0
0x220 CMR1
0x224 CDTY1
0x228 CDTYUPD1
0x22c CPRD1
0x230 CPRDUPD1
0x234 CCNT1
0x238 DT1
0x23c DTUPD1
0x240 CMR2
0x244 CDTY2
0x248 CDTYUPD2
0x24c CPRD2
0x250 CPRDUPD2
0x254 CCNT2
0x258 DT2
0x25c DTUPD2
0x260 CMR3
0x264 CDTY3
0x268 CDTYUPD3
0x26c CPRD3
0x270 CPRDUPD3
0x274 CCNT3
0x278 DT3
0x27c DTUPD3
0x280 CMR4
0x284 CDTY4
0x288 CDTYUPD4
0x28c CPRD4
0x290 CPRDUPD4
0x294 CCNT4
0x298 DT4
0x29c DTUPD4
0x2a0 CMR5
0x2a4 CDTY5
0x2a8 CDTYUPD5
0x2ac CPRD5
0x2b0 CPRDUPD5
0x2b4 CCNT5
0x2b8 DT5
0x2bc DTUPD5
0x2c0 CMR6
0x2c4 CDTY6
0x2c8 CDTYUPD6
0x2cc CPRD6
0x2d0 CPRDUPD6
0x2d4 CCNT6
0x2d8 DT6
0x2dc DTUPD6
0x2e0 CMR7
0x2e4 CDTY7
0x2e8 CDTYUPD7
0x2ec CPRD7
0x2f0 CPRDUPD7
0x2f4 CCNT7
0x2f8 DT7
0x2fc DTUPD7

CLK

PWM Clock Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREB
rw 		DIVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREA
rw 		DIVA
rw
Toggle Fields

DIVA

Bits 0-7: CLKA, CLKB Divide Factor.

PREA

Bits 8-11: CLKA, CLKB Source Clock Selection.

DIVB

Bits 16-23: CLKA, CLKB Divide Factor.

PREB

Bits 24-27: CLKA, CLKB Source Clock Selection.

ENA

PWM Enable Register

Offset: 0x4, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHID7
w 		CHID6
w 		CHID5
w 		CHID4
w 		CHID3
w 		CHID2
w 		CHID1
w 		CHID0
w
Toggle Fields

CHID0

Bit 0: Channel ID.

CHID1

Bit 1: Channel ID.

CHID2

Bit 2: Channel ID.

CHID3

Bit 3: Channel ID.

CHID4

Bit 4: Channel ID.

CHID5

Bit 5: Channel ID.

CHID6

Bit 6: Channel ID.

CHID7

Bit 7: Channel ID.

DIS

PWM Disable Register

Offset: 0x8, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHID7
w 		CHID6
w 		CHID5
w 		CHID4
w 		CHID3
w 		CHID2
w 		CHID1
w 		CHID0
w
Toggle Fields

CHID0

Bit 0: Channel ID.

CHID1

Bit 1: Channel ID.

CHID2

Bit 2: Channel ID.

CHID3

Bit 3: Channel ID.

CHID4

Bit 4: Channel ID.

CHID5

Bit 5: Channel ID.

CHID6

Bit 6: Channel ID.

CHID7

Bit 7: Channel ID.

SR

PWM Status Register

Offset: 0xc, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHID7
r 		CHID6
r 		CHID5
r 		CHID4
r 		CHID3
r 		CHID2
r 		CHID1
r 		CHID0
r
Toggle Fields

CHID0

Bit 0: Channel ID.

CHID1

Bit 1: Channel ID.

CHID2

Bit 2: Channel ID.

CHID3

Bit 3: Channel ID.

CHID4

Bit 4: Channel ID.

CHID5

Bit 5: Channel ID.

CHID6

Bit 6: Channel ID.

CHID7

Bit 7: Channel ID.

IER1

PWM Interrupt Enable Register 1

Offset: 0x10, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FCHID7
w 		FCHID6
w 		FCHID5
w 		FCHID4
w 		FCHID3
w 		FCHID2
w 		FCHID1
w 		FCHID0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHID7
w 		CHID6
w 		CHID5
w 		CHID4
w 		CHID3
w 		CHID2
w 		CHID1
w 		CHID0
w
Toggle Fields

CHID0

Bit 0: Counter Event on Channel 0 Interrupt Enable.

CHID1

Bit 1: Counter Event on Channel 1 Interrupt Enable.

CHID2

Bit 2: Counter Event on Channel 2 Interrupt Enable.

CHID3

Bit 3: Counter Event on Channel 3 Interrupt Enable.

CHID4

Bit 4: Counter Event on Channel 4 Interrupt Enable.

CHID5

Bit 5: Counter Event on Channel 5 Interrupt Enable.

CHID6

Bit 6: Counter Event on Channel 6 Interrupt Enable.

CHID7

Bit 7: Counter Event on Channel 7 Interrupt Enable.

FCHID0

Bit 16: Fault Protection Trigger on Channel 0 Interrupt Enable.

FCHID1

Bit 17: Fault Protection Trigger on Channel 1 Interrupt Enable.

FCHID2

Bit 18: Fault Protection Trigger on Channel 2 Interrupt Enable.

FCHID3

Bit 19: Fault Protection Trigger on Channel 3 Interrupt Enable.

FCHID4

Bit 20: Fault Protection Trigger on Channel 4 Interrupt Enable.

FCHID5

Bit 21: Fault Protection Trigger on Channel 5 Interrupt Enable.

FCHID6

Bit 22: Fault Protection Trigger on Channel 6 Interrupt Enable.

FCHID7

Bit 23: Fault Protection Trigger on Channel 7 Interrupt Enable.

IDR1

PWM Interrupt Disable Register 1

Offset: 0x14, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FCHID7
w 		FCHID6
w 		FCHID5
w 		FCHID4
w 		FCHID3
w 		FCHID2
w 		FCHID1
w 		FCHID0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHID7
w 		CHID6
w 		CHID5
w 		CHID4
w 		CHID3
w 		CHID2
w 		CHID1
w 		CHID0
w
Toggle Fields

CHID0

Bit 0: Counter Event on Channel 0 Interrupt Disable.

CHID1

Bit 1: Counter Event on Channel 1 Interrupt Disable.

CHID2

Bit 2: Counter Event on Channel 2 Interrupt Disable.

CHID3

Bit 3: Counter Event on Channel 3 Interrupt Disable.

CHID4

Bit 4: Counter Event on Channel 4 Interrupt Disable.

CHID5

Bit 5: Counter Event on Channel 5 Interrupt Disable.

CHID6

Bit 6: Counter Event on Channel 6 Interrupt Disable.

CHID7

Bit 7: Counter Event on Channel 7 Interrupt Disable.

FCHID0

Bit 16: Fault Protection Trigger on Channel 0 Interrupt Disable.

FCHID1

Bit 17: Fault Protection Trigger on Channel 1 Interrupt Disable.

FCHID2

Bit 18: Fault Protection Trigger on Channel 2 Interrupt Disable.

FCHID3

Bit 19: Fault Protection Trigger on Channel 3 Interrupt Disable.

FCHID4

Bit 20: Fault Protection Trigger on Channel 4 Interrupt Disable.

FCHID5

Bit 21: Fault Protection Trigger on Channel 5 Interrupt Disable.

FCHID6

Bit 22: Fault Protection Trigger on Channel 6 Interrupt Disable.

FCHID7

Bit 23: Fault Protection Trigger on Channel 7 Interrupt Disable.

IMR1

PWM Interrupt Mask Register 1

Offset: 0x18, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FCHID7
r 		FCHID6
r 		FCHID5
r 		FCHID4
r 		FCHID3
r 		FCHID2
r 		FCHID1
r 		FCHID0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHID7
r 		CHID6
r 		CHID5
r 		CHID4
r 		CHID3
r 		CHID2
r 		CHID1
r 		CHID0
r
Toggle Fields

CHID0

Bit 0: Counter Event on Channel 0 Interrupt Mask.

CHID1

Bit 1: Counter Event on Channel 1 Interrupt Mask.

CHID2

Bit 2: Counter Event on Channel 2 Interrupt Mask.

CHID3

Bit 3: Counter Event on Channel 3 Interrupt Mask.

CHID4

Bit 4: Counter Event on Channel 4 Interrupt Mask.

CHID5

Bit 5: Counter Event on Channel 5 Interrupt Mask.

CHID6

Bit 6: Counter Event on Channel 6 Interrupt Mask.

CHID7

Bit 7: Counter Event on Channel 7 Interrupt Mask.

FCHID0

Bit 16: Fault Protection Trigger on Channel 0 Interrupt Mask.

FCHID1

Bit 17: Fault Protection Trigger on Channel 1 Interrupt Mask.

FCHID2

Bit 18: Fault Protection Trigger on Channel 2 Interrupt Mask.

FCHID3

Bit 19: Fault Protection Trigger on Channel 3 Interrupt Mask.

FCHID4

Bit 20: Fault Protection Trigger on Channel 4 Interrupt Mask.

FCHID5

Bit 21: Fault Protection Trigger on Channel 5 Interrupt Mask.

FCHID6

Bit 22: Fault Protection Trigger on Channel 6 Interrupt Mask.

FCHID7

Bit 23: Fault Protection Trigger on Channel 7 Interrupt Mask.

ISR1

PWM Interrupt Status Register 1

Offset: 0x1c, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FCHID7
r 		FCHID6
r 		FCHID5
r 		FCHID4
r 		FCHID3
r 		FCHID2
r 		FCHID1
r 		FCHID0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHID7
r 		CHID6
r 		CHID5
r 		CHID4
r 		CHID3
r 		CHID2
r 		CHID1
r 		CHID0
r
Toggle Fields

CHID0

Bit 0: Counter Event on Channel 0.

CHID1

Bit 1: Counter Event on Channel 1.

CHID2

Bit 2: Counter Event on Channel 2.

CHID3

Bit 3: Counter Event on Channel 3.

CHID4

Bit 4: Counter Event on Channel 4.

CHID5

Bit 5: Counter Event on Channel 5.

CHID6

Bit 6: Counter Event on Channel 6.

CHID7

Bit 7: Counter Event on Channel 7.

FCHID0

Bit 16: Fault Protection Trigger on Channel 0.

FCHID1

Bit 17: Fault Protection Trigger on Channel 1.

FCHID2

Bit 18: Fault Protection Trigger on Channel 2.

FCHID3

Bit 19: Fault Protection Trigger on Channel 3.

FCHID4

Bit 20: Fault Protection Trigger on Channel 4.

FCHID5

Bit 21: Fault Protection Trigger on Channel 5.

FCHID6

Bit 22: Fault Protection Trigger on Channel 6.

FCHID7

Bit 23: Fault Protection Trigger on Channel 7.

SCM

PWM Sync Channels Mode Register

Offset: 0x20, reset: 0x00000000, access: read-write

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTRCS
rw 		PTRM
rw 		UPDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC7
rw 		SYNC6
rw 		SYNC5
rw 		SYNC4
rw 		SYNC3
rw 		SYNC2
rw 		SYNC1
rw 		SYNC0
rw
Toggle Fields

SYNC0

Bit 0: Synchronous Channel 0.

SYNC1

Bit 1: Synchronous Channel 1.

SYNC2

Bit 2: Synchronous Channel 2.

SYNC3

Bit 3: Synchronous Channel 3.

SYNC4

Bit 4: Synchronous Channel 4.

SYNC5

Bit 5: Synchronous Channel 5.

SYNC6

Bit 6: Synchronous Channel 6.

SYNC7

Bit 7: Synchronous Channel 7.

UPDM

Bits 16-17: Synchronous Channels Update Mode.

Allowed values:
0x0: MODE0: Manual write of double buffer registers and manual update of synchronous channels
0x1: MODE1: Manual write of double buffer registers and automatic update of synchronous channels
0x2: MODE2: Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels

PTRM

Bit 20: PDC Transfer Request Mode.

PTRCS

Bits 21-23: PDC Transfer Request Comparison Selection.

SCUC

PWM Sync Channels Update Control Register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDULOCK
rw
Toggle Fields

UPDULOCK

Bit 0: Synchronous Channels Update Unlock.

SCUP

PWM Sync Channels Update Period Register

Offset: 0x2c, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPRCNT
rw 		UPR
rw
Toggle Fields

UPR

Bits 0-3: Update Period.

UPRCNT

Bits 4-7: Update Period Counter.

SCUPUPD

PWM Sync Channels Update Period Update Register

Offset: 0x30, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPRUPD
w
Toggle Fields

UPRUPD

Bits 0-3: Update Period Update.

IER2

PWM Interrupt Enable Register 2

Offset: 0x34, reset: None, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMPU7
w 		CMPU6
w 		CMPU5
w 		CMPU4
w 		CMPU3
w 		CMPU2
w 		CMPU1
w 		CMPU0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPM7
w 		CMPM6
w 		CMPM5
w 		CMPM4
w 		CMPM3
w 		CMPM2
w 		CMPM1
w 		CMPM0
w 		UNRE
w 		TXBUFE
w 		ENDTX
w 		WRDY
w
Toggle Fields

WRDY

Bit 0: Write Ready for Synchronous Channels Update Interrupt Enable.

ENDTX

Bit 1: PDC End of TX Buffer Interrupt Enable.

TXBUFE

Bit 2: PDC TX Buffer Empty Interrupt Enable.

UNRE

Bit 3: Synchronous Channels Update Underrun Error Interrupt Enable.

CMPM0

Bit 8: Comparison 0 Match Interrupt Enable.

CMPM1

Bit 9: Comparison 1 Match Interrupt Enable.

CMPM2

Bit 10: Comparison 2 Match Interrupt Enable.

CMPM3

Bit 11: Comparison 3 Match Interrupt Enable.

CMPM4

Bit 12: Comparison 4 Match Interrupt Enable.

CMPM5

Bit 13: Comparison 5 Match Interrupt Enable.

CMPM6

Bit 14: Comparison 6 Match Interrupt Enable.

CMPM7

Bit 15: Comparison 7 Match Interrupt Enable.

CMPU0

Bit 16: Comparison 0 Update Interrupt Enable.

CMPU1

Bit 17: Comparison 1 Update Interrupt Enable.

CMPU2

Bit 18: Comparison 2 Update Interrupt Enable.

CMPU3

Bit 19: Comparison 3 Update Interrupt Enable.

CMPU4

Bit 20: Comparison 4 Update Interrupt Enable.

CMPU5

Bit 21: Comparison 5 Update Interrupt Enable.

CMPU6

Bit 22: Comparison 6 Update Interrupt Enable.

CMPU7

Bit 23: Comparison 7 Update Interrupt Enable.

IDR2

PWM Interrupt Disable Register 2

Offset: 0x38, reset: None, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMPU7
w 		CMPU6
w 		CMPU5
w 		CMPU4
w 		CMPU3
w 		CMPU2
w 		CMPU1
w 		CMPU0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPM7
w 		CMPM6
w 		CMPM5
w 		CMPM4
w 		CMPM3
w 		CMPM2
w 		CMPM1
w 		CMPM0
w 		UNRE
w 		TXBUFE
w 		ENDTX
w 		WRDY
w
Toggle Fields

WRDY

Bit 0: Write Ready for Synchronous Channels Update Interrupt Disable.

ENDTX

Bit 1: PDC End of TX Buffer Interrupt Disable.

TXBUFE

Bit 2: PDC TX Buffer Empty Interrupt Disable.

UNRE

Bit 3: Synchronous Channels Update Underrun Error Interrupt Disable.

CMPM0

Bit 8: Comparison 0 Match Interrupt Disable.

CMPM1

Bit 9: Comparison 1 Match Interrupt Disable.

CMPM2

Bit 10: Comparison 2 Match Interrupt Disable.

CMPM3

Bit 11: Comparison 3 Match Interrupt Disable.

CMPM4

Bit 12: Comparison 4 Match Interrupt Disable.

CMPM5

Bit 13: Comparison 5 Match Interrupt Disable.

CMPM6

Bit 14: Comparison 6 Match Interrupt Disable.

CMPM7

Bit 15: Comparison 7 Match Interrupt Disable.

CMPU0

Bit 16: Comparison 0 Update Interrupt Disable.

CMPU1

Bit 17: Comparison 1 Update Interrupt Disable.

CMPU2

Bit 18: Comparison 2 Update Interrupt Disable.

CMPU3

Bit 19: Comparison 3 Update Interrupt Disable.

CMPU4

Bit 20: Comparison 4 Update Interrupt Disable.

CMPU5

Bit 21: Comparison 5 Update Interrupt Disable.

CMPU6

Bit 22: Comparison 6 Update Interrupt Disable.

CMPU7

Bit 23: Comparison 7 Update Interrupt Disable.

IMR2

PWM Interrupt Mask Register 2

Offset: 0x3c, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMPU7
r 		CMPU6
r 		CMPU5
r 		CMPU4
r 		CMPU3
r 		CMPU2
r 		CMPU1
r 		CMPU0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPM7
r 		CMPM6
r 		CMPM5
r 		CMPM4
r 		CMPM3
r 		CMPM2
r 		CMPM1
r 		CMPM0
r 		UNRE
r 		TXBUFE
r 		ENDTX
r 		WRDY
r
Toggle Fields

WRDY

Bit 0: Write Ready for Synchronous Channels Update Interrupt Mask.

ENDTX

Bit 1: PDC End of TX Buffer Interrupt Mask.

TXBUFE

Bit 2: PDC TX Buffer Empty Interrupt Mask.

UNRE

Bit 3: Synchronous Channels Update Underrun Error Interrupt Mask.

CMPM0

Bit 8: Comparison 0 Match Interrupt Mask.

CMPM1

Bit 9: Comparison 1 Match Interrupt Mask.

CMPM2

Bit 10: Comparison 2 Match Interrupt Mask.

CMPM3

Bit 11: Comparison 3 Match Interrupt Mask.

CMPM4

Bit 12: Comparison 4 Match Interrupt Mask.

CMPM5

Bit 13: Comparison 5 Match Interrupt Mask.

CMPM6

Bit 14: Comparison 6 Match Interrupt Mask.

CMPM7

Bit 15: Comparison 7 Match Interrupt Mask.

CMPU0

Bit 16: Comparison 0 Update Interrupt Mask.

CMPU1

Bit 17: Comparison 1 Update Interrupt Mask.

CMPU2

Bit 18: Comparison 2 Update Interrupt Mask.

CMPU3

Bit 19: Comparison 3 Update Interrupt Mask.

CMPU4

Bit 20: Comparison 4 Update Interrupt Mask.

CMPU5

Bit 21: Comparison 5 Update Interrupt Mask.

CMPU6

Bit 22: Comparison 6 Update Interrupt Mask.

CMPU7

Bit 23: Comparison 7 Update Interrupt Mask.

ISR2

PWM Interrupt Status Register 2

Offset: 0x40, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMPU7
r 		CMPU6
r 		CMPU5
r 		CMPU4
r 		CMPU3
r 		CMPU2
r 		CMPU1
r 		CMPU0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPM7
r 		CMPM6
r 		CMPM5
r 		CMPM4
r 		CMPM3
r 		CMPM2
r 		CMPM1
r 		CMPM0
r 		UNRE
r 		TXBUFE
r 		ENDTX
r 		WRDY
r
Toggle Fields

WRDY

Bit 0: Write Ready for Synchronous Channels Update.

ENDTX

Bit 1: PDC End of TX Buffer.

TXBUFE

Bit 2: PDC TX Buffer Empty.

UNRE

Bit 3: Synchronous Channels Update Underrun Error.

CMPM0

Bit 8: Comparison 0 Match.

CMPM1

Bit 9: Comparison 1 Match.

CMPM2

Bit 10: Comparison 2 Match.

CMPM3

Bit 11: Comparison 3 Match.

CMPM4

Bit 12: Comparison 4 Match.

CMPM5

Bit 13: Comparison 5 Match.

CMPM6

Bit 14: Comparison 6 Match.

CMPM7

Bit 15: Comparison 7 Match.

CMPU0

Bit 16: Comparison 0 Update.

CMPU1

Bit 17: Comparison 1 Update.

CMPU2

Bit 18: Comparison 2 Update.

CMPU3

Bit 19: Comparison 3 Update.

CMPU4

Bit 20: Comparison 4 Update.

CMPU5

Bit 21: Comparison 5 Update.

CMPU6

Bit 22: Comparison 6 Update.

CMPU7

Bit 23: Comparison 7 Update.

OOV

PWM Output Override Value Register

Offset: 0x44, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OOVL7
rw 		OOVL6
rw 		OOVL5
rw 		OOVL4
rw 		OOVL3
rw 		OOVL2
rw 		OOVL1
rw 		OOVL0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OOVH7
rw 		OOVH6
rw 		OOVH5
rw 		OOVH4
rw 		OOVH3
rw 		OOVH2
rw 		OOVH1
rw 		OOVH0
rw
Toggle Fields

OOVH0

Bit 0: Output Override Value for PWMH output of the channel 0.

OOVH1

Bit 1: Output Override Value for PWMH output of the channel 1.

OOVH2

Bit 2: Output Override Value for PWMH output of the channel 2.

OOVH3

Bit 3: Output Override Value for PWMH output of the channel 3.

OOVH4

Bit 4: Output Override Value for PWMH output of the channel 4.

OOVH5

Bit 5: Output Override Value for PWMH output of the channel 5.

OOVH6

Bit 6: Output Override Value for PWMH output of the channel 6.

OOVH7

Bit 7: Output Override Value for PWMH output of the channel 7.

OOVL0

Bit 16: Output Override Value for PWML output of the channel 0.

OOVL1

Bit 17: Output Override Value for PWML output of the channel 1.

OOVL2

Bit 18: Output Override Value for PWML output of the channel 2.

OOVL3

Bit 19: Output Override Value for PWML output of the channel 3.

OOVL4

Bit 20: Output Override Value for PWML output of the channel 4.

OOVL5

Bit 21: Output Override Value for PWML output of the channel 5.

OOVL6

Bit 22: Output Override Value for PWML output of the channel 6.

OOVL7

Bit 23: Output Override Value for PWML output of the channel 7.

OS

PWM Output Selection Register

Offset: 0x48, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSL7
rw 		OSL6
rw 		OSL5
rw 		OSL4
rw 		OSL3
rw 		OSL2
rw 		OSL1
rw 		OSL0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSH7
rw 		OSH6
rw 		OSH5
rw 		OSH4
rw 		OSH3
rw 		OSH2
rw 		OSH1
rw 		OSH0
rw
Toggle Fields

OSH0

Bit 0: Output Selection for PWMH output of the channel 0.

OSH1

Bit 1: Output Selection for PWMH output of the channel 1.

OSH2

Bit 2: Output Selection for PWMH output of the channel 2.

OSH3

Bit 3: Output Selection for PWMH output of the channel 3.

OSH4

Bit 4: Output Selection for PWMH output of the channel 4.

OSH5

Bit 5: Output Selection for PWMH output of the channel 5.

OSH6

Bit 6: Output Selection for PWMH output of the channel 6.

OSH7

Bit 7: Output Selection for PWMH output of the channel 7.

OSL0

Bit 16: Output Selection for PWML output of the channel 0.

OSL1

Bit 17: Output Selection for PWML output of the channel 1.

OSL2

Bit 18: Output Selection for PWML output of the channel 2.

OSL3

Bit 19: Output Selection for PWML output of the channel 3.

OSL4

Bit 20: Output Selection for PWML output of the channel 4.

OSL5

Bit 21: Output Selection for PWML output of the channel 5.

OSL6

Bit 22: Output Selection for PWML output of the channel 6.

OSL7

Bit 23: Output Selection for PWML output of the channel 7.

OSS

PWM Output Selection Set Register

Offset: 0x4c, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSSL7
w 		OSSL6
w 		OSSL5
w 		OSSL4
w 		OSSL3
w 		OSSL2
w 		OSSL1
w 		OSSL0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSSH7
w 		OSSH6
w 		OSSH5
w 		OSSH4
w 		OSSH3
w 		OSSH2
w 		OSSH1
w 		OSSH0
w
Toggle Fields

OSSH0

Bit 0: Output Selection Set for PWMH output of the channel 0.

OSSH1

Bit 1: Output Selection Set for PWMH output of the channel 1.

OSSH2

Bit 2: Output Selection Set for PWMH output of the channel 2.

OSSH3

Bit 3: Output Selection Set for PWMH output of the channel 3.

OSSH4

Bit 4: Output Selection Set for PWMH output of the channel 4.

OSSH5

Bit 5: Output Selection Set for PWMH output of the channel 5.

OSSH6

Bit 6: Output Selection Set for PWMH output of the channel 6.

OSSH7

Bit 7: Output Selection Set for PWMH output of the channel 7.

OSSL0

Bit 16: Output Selection Set for PWML output of the channel 0.

OSSL1

Bit 17: Output Selection Set for PWML output of the channel 1.

OSSL2

Bit 18: Output Selection Set for PWML output of the channel 2.

OSSL3

Bit 19: Output Selection Set for PWML output of the channel 3.

OSSL4

Bit 20: Output Selection Set for PWML output of the channel 4.

OSSL5

Bit 21: Output Selection Set for PWML output of the channel 5.

OSSL6

Bit 22: Output Selection Set for PWML output of the channel 6.

OSSL7

Bit 23: Output Selection Set for PWML output of the channel 7.

OSC

PWM Output Selection Clear Register

Offset: 0x50, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSCL7
w 		OSCL6
w 		OSCL5
w 		OSCL4
w 		OSCL3
w 		OSCL2
w 		OSCL1
w 		OSCL0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSCH7
w 		OSCH6
w 		OSCH5
w 		OSCH4
w 		OSCH3
w 		OSCH2
w 		OSCH1
w 		OSCH0
w
Toggle Fields

OSCH0

Bit 0: Output Selection Clear for PWMH output of the channel 0.

OSCH1

Bit 1: Output Selection Clear for PWMH output of the channel 1.

OSCH2

Bit 2: Output Selection Clear for PWMH output of the channel 2.

OSCH3

Bit 3: Output Selection Clear for PWMH output of the channel 3.

OSCH4

Bit 4: Output Selection Clear for PWMH output of the channel 4.

OSCH5

Bit 5: Output Selection Clear for PWMH output of the channel 5.

OSCH6

Bit 6: Output Selection Clear for PWMH output of the channel 6.

OSCH7

Bit 7: Output Selection Clear for PWMH output of the channel 7.

OSCL0

Bit 16: Output Selection Clear for PWML output of the channel 0.

OSCL1

Bit 17: Output Selection Clear for PWML output of the channel 1.

OSCL2

Bit 18: Output Selection Clear for PWML output of the channel 2.

OSCL3

Bit 19: Output Selection Clear for PWML output of the channel 3.

OSCL4

Bit 20: Output Selection Clear for PWML output of the channel 4.

OSCL5

Bit 21: Output Selection Clear for PWML output of the channel 5.

OSCL6

Bit 22: Output Selection Clear for PWML output of the channel 6.

OSCL7

Bit 23: Output Selection Clear for PWML output of the channel 7.

OSSUPD

PWM Output Selection Set Update Register

Offset: 0x54, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSSUPL7
w 		OSSUPL6
w 		OSSUPL5
w 		OSSUPL4
w 		OSSUPL3
w 		OSSUPL2
w 		OSSUPL1
w 		OSSUPL0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSSUPH7
w 		OSSUPH6
w 		OSSUPH5
w 		OSSUPH4
w 		OSSUPH3
w 		OSSUPH2
w 		OSSUPH1
w 		OSSUPH0
w
Toggle Fields

OSSUPH0

Bit 0: Output Selection Set for PWMH output of the channel 0.

OSSUPH1

Bit 1: Output Selection Set for PWMH output of the channel 1.

OSSUPH2

Bit 2: Output Selection Set for PWMH output of the channel 2.

OSSUPH3

Bit 3: Output Selection Set for PWMH output of the channel 3.

OSSUPH4

Bit 4: Output Selection Set for PWMH output of the channel 4.

OSSUPH5

Bit 5: Output Selection Set for PWMH output of the channel 5.

OSSUPH6

Bit 6: Output Selection Set for PWMH output of the channel 6.

OSSUPH7

Bit 7: Output Selection Set for PWMH output of the channel 7.

OSSUPL0

Bit 16: Output Selection Set for PWML output of the channel 0.

OSSUPL1

Bit 17: Output Selection Set for PWML output of the channel 1.

OSSUPL2

Bit 18: Output Selection Set for PWML output of the channel 2.

OSSUPL3

Bit 19: Output Selection Set for PWML output of the channel 3.

OSSUPL4

Bit 20: Output Selection Set for PWML output of the channel 4.

OSSUPL5

Bit 21: Output Selection Set for PWML output of the channel 5.

OSSUPL6

Bit 22: Output Selection Set for PWML output of the channel 6.

OSSUPL7

Bit 23: Output Selection Set for PWML output of the channel 7.

OSCUPD

PWM Output Selection Clear Update Register

Offset: 0x58, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSCUPL7
w 		OSCUPL6
w 		OSCUPL5
w 		OSCUPL4
w 		OSCUPL3
w 		OSCUPL2
w 		OSCUPL1
w 		OSCUPL0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSCUPH7
w 		OSCUPH6
w 		OSCUPH5
w 		OSCUPH4
w 		OSCUPH3
w 		OSCUPH2
w 		OSCUPH1
w 		OSCUPH0
w
Toggle Fields

OSCUPH0

Bit 0: Output Selection Clear for PWMH output of the channel 0.

OSCUPH1

Bit 1: Output Selection Clear for PWMH output of the channel 1.

OSCUPH2

Bit 2: Output Selection Clear for PWMH output of the channel 2.

OSCUPH3

Bit 3: Output Selection Clear for PWMH output of the channel 3.

OSCUPH4

Bit 4: Output Selection Clear for PWMH output of the channel 4.

OSCUPH5

Bit 5: Output Selection Clear for PWMH output of the channel 5.

OSCUPH6

Bit 6: Output Selection Clear for PWMH output of the channel 6.

OSCUPH7

Bit 7: Output Selection Clear for PWMH output of the channel 7.

OSCUPL0

Bit 16: Output Selection Clear for PWML output of the channel 0.

OSCUPL1

Bit 17: Output Selection Clear for PWML output of the channel 1.

OSCUPL2

Bit 18: Output Selection Clear for PWML output of the channel 2.

OSCUPL3

Bit 19: Output Selection Clear for PWML output of the channel 3.

OSCUPL4

Bit 20: Output Selection Clear for PWML output of the channel 4.

OSCUPL5

Bit 21: Output Selection Clear for PWML output of the channel 5.

OSCUPL6

Bit 22: Output Selection Clear for PWML output of the channel 6.

OSCUPL7

Bit 23: Output Selection Clear for PWML output of the channel 7.

FMR

PWM Fault Mode Register

Offset: 0x5c, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FFIL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMOD
rw 		FPOL
rw
Toggle Fields

FPOL

Bits 0-7: Fault Polarity (fault input bit varies from 0 to 5).

FMOD

Bits 8-15: Fault Activation Mode (fault input bit varies from 0 to 5).

FFIL

Bits 16-23: Fault Filtering (fault input bit varies from 0 to 5).

FSR

PWM Fault Status Register

Offset: 0x60, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS
r 		FIV
r
Toggle Fields

FIV

Bits 0-7: Fault Input Value (fault input bit varies from 0 to 5).

FS

Bits 8-15: Fault Status (fault input bit varies from 0 to 5).

FCR

PWM Fault Clear Register

Offset: 0x64, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCLR
w
Toggle Fields

FCLR

Bits 0-7: Fault Clear (fault input bit varies from 0 to 5).

FPV

PWM Fault Protection Value Register

Offset: 0x68, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPVL7
rw 		FPVL6
rw 		FPVL5
rw 		FPVL4
rw 		FPVL3
rw 		FPVL2
rw 		FPVL1
rw 		FPVL0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPVH7
rw 		FPVH6
rw 		FPVH5
rw 		FPVH4
rw 		FPVH3
rw 		FPVH2
rw 		FPVH1
rw 		FPVH0
rw
Toggle Fields

FPVH0

Bit 0: Fault Protection Value for PWMH output on channel 0.

FPVH1

Bit 1: Fault Protection Value for PWMH output on channel 1.

FPVH2

Bit 2: Fault Protection Value for PWMH output on channel 2.

FPVH3

Bit 3: Fault Protection Value for PWMH output on channel 3.

FPVH4

Bit 4: Fault Protection Value for PWMH output on channel 4.

FPVH5

Bit 5: Fault Protection Value for PWMH output on channel 5.

FPVH6

Bit 6: Fault Protection Value for PWMH output on channel 6.

FPVH7

Bit 7: Fault Protection Value for PWMH output on channel 7.

FPVL0

Bit 16: Fault Protection Value for PWML output on channel 0.

FPVL1

Bit 17: Fault Protection Value for PWML output on channel 1.

FPVL2

Bit 18: Fault Protection Value for PWML output on channel 2.

FPVL3

Bit 19: Fault Protection Value for PWML output on channel 3.

FPVL4

Bit 20: Fault Protection Value for PWML output on channel 4.

FPVL5

Bit 21: Fault Protection Value for PWML output on channel 5.

FPVL6

Bit 22: Fault Protection Value for PWML output on channel 6.

FPVL7

Bit 23: Fault Protection Value for PWML output on channel 7.

FPE1

PWM Fault Protection Enable Register 1

Offset: 0x6c, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPE3
rw 		FPE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPE1
rw 		FPE0
rw
Toggle Fields

FPE0

Bits 0-7: Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5).

FPE1

Bits 8-15: Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5).

FPE2

Bits 16-23: Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5).

FPE3

Bits 24-31: Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5).

FPE2

PWM Fault Protection Enable Register 2

Offset: 0x70, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPE7
rw 		FPE6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPE5
rw 		FPE4
rw
Toggle Fields

FPE4

Bits 0-7: Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5).

FPE5

Bits 8-15: Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5).

FPE6

Bits 16-23: Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5).

FPE7

Bits 24-31: Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5).

ELMR[[0]]

PWM Event Line 0 Mode Register

Offset: 0x7c, reset: None, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSEL7
rw 		CSEL6
rw 		CSEL5
rw 		CSEL4
rw 		CSEL3
rw 		CSEL2
rw 		CSEL1
rw 		CSEL0
rw
Toggle Fields

CSEL0

Bit 0: Comparison 0 Selection.

CSEL1

Bit 1: Comparison 1 Selection.

CSEL2

Bit 2: Comparison 2 Selection.

CSEL3

Bit 3: Comparison 3 Selection.

CSEL4

Bit 4: Comparison 4 Selection.

CSEL5

Bit 5: Comparison 5 Selection.

CSEL6

Bit 6: Comparison 6 Selection.

CSEL7

Bit 7: Comparison 7 Selection.

ELMR[[1]]

PWM Event Line 0 Mode Register

Offset: 0x80, reset: None, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSEL7
rw 		CSEL6
rw 		CSEL5
rw 		CSEL4
rw 		CSEL3
rw 		CSEL2
rw 		CSEL1
rw 		CSEL0
rw
Toggle Fields

CSEL0

Bit 0: Comparison 0 Selection.

CSEL1

Bit 1: Comparison 1 Selection.

CSEL2

Bit 2: Comparison 2 Selection.

CSEL3

Bit 3: Comparison 3 Selection.

CSEL4

Bit 4: Comparison 4 Selection.

CSEL5

Bit 5: Comparison 5 Selection.

CSEL6

Bit 6: Comparison 6 Selection.

CSEL7

Bit 7: Comparison 7 Selection.

SMMR

PWM Stepper Motor Mode Register

Offset: 0xb0, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOWN3
rw 		DOWN2
rw 		DOWN1
rw 		DOWN0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GCEN3
rw 		GCEN2
rw 		GCEN1
rw 		GCEN0
rw
Toggle Fields

GCEN0

Bit 0: Gray Count ENable.

GCEN1

Bit 1: Gray Count ENable.

GCEN2

Bit 2: Gray Count ENable.

GCEN3

Bit 3: Gray Count ENable.

DOWN0

Bit 16: DOWN Count.

DOWN1

Bit 17: DOWN Count.

DOWN2

Bit 18: DOWN Count.

DOWN3

Bit 19: DOWN Count.

WPCR

PWM Write Protect Control Register

Offset: 0xe4, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
w 		WPRG5
w 		WPRG4
w 		WPRG3
w 		WPRG2
w 		WPRG1
w 		WPRG0
w 		WPCMD
w
Toggle Fields

WPCMD

Bits 0-1: Write Protect Command.

WPRG0

Bit 2: Write Protect Register Group 0.

WPRG1

Bit 3: Write Protect Register Group 1.

WPRG2

Bit 4: Write Protect Register Group 2.

WPRG3

Bit 5: Write Protect Register Group 3.

WPRG4

Bit 6: Write Protect Register Group 4.

WPRG5

Bit 7: Write Protect Register Group 5.

WPKEY

Bits 8-31: Write Protect Key.

WPSR

PWM Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPHWS5
r 		WPHWS4
r 		WPHWS3
r 		WPHWS2
r 		WPHWS1
r 		WPHWS0
r 		WPVS
r 		WPSWS5
r 		WPSWS4
r 		WPSWS3
r 		WPSWS2
r 		WPSWS1
r 		WPSWS0
r
Toggle Fields

WPSWS0

Bit 0: Write Protect SW Status.

WPSWS1

Bit 1: Write Protect SW Status.

WPSWS2

Bit 2: Write Protect SW Status.

WPSWS3

Bit 3: Write Protect SW Status.

WPSWS4

Bit 4: Write Protect SW Status.

WPSWS5

Bit 5: Write Protect SW Status.

WPVS

Bit 7: Write Protect Violation Status.

WPHWS0

Bit 8: Write Protect HW Status.

WPHWS1

Bit 9: Write Protect HW Status.

WPHWS2

Bit 10: Write Protect HW Status.

WPHWS3

Bit 11: Write Protect HW Status.

WPHWS4

Bit 12: Write Protect HW Status.

WPHWS5

Bit 13: Write Protect HW Status.

WPVSRC

Bits 16-31: Write Protect Violation Source.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

CMPV0

PWM Comparison 0 Value Register

Offset: 0x130, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD0

PWM Comparison 0 Value Update Register

Offset: 0x134, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM0

PWM Comparison 0 Mode Register

Offset: 0x138, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD0

PWM Comparison 0 Mode Update Register

Offset: 0x13c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMPV1

PWM Comparison 1 Value Register

Offset: 0x140, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD1

PWM Comparison 1 Value Update Register

Offset: 0x144, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM1

PWM Comparison 1 Mode Register

Offset: 0x148, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD1

PWM Comparison 1 Mode Update Register

Offset: 0x14c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMPV2

PWM Comparison 2 Value Register

Offset: 0x150, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD2

PWM Comparison 2 Value Update Register

Offset: 0x154, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM2

PWM Comparison 2 Mode Register

Offset: 0x158, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD2

PWM Comparison 2 Mode Update Register

Offset: 0x15c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMPV3

PWM Comparison 3 Value Register

Offset: 0x160, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD3

PWM Comparison 3 Value Update Register

Offset: 0x164, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM3

PWM Comparison 3 Mode Register

Offset: 0x168, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD3

PWM Comparison 3 Mode Update Register

Offset: 0x16c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMPV4

PWM Comparison 4 Value Register

Offset: 0x170, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD4

PWM Comparison 4 Value Update Register

Offset: 0x174, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM4

PWM Comparison 4 Mode Register

Offset: 0x178, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD4

PWM Comparison 4 Mode Update Register

Offset: 0x17c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMPV5

PWM Comparison 5 Value Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD5

PWM Comparison 5 Value Update Register

Offset: 0x184, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM5

PWM Comparison 5 Mode Register

Offset: 0x188, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD5

PWM Comparison 5 Mode Update Register

Offset: 0x18c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMPV6

PWM Comparison 6 Value Register

Offset: 0x190, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD6

PWM Comparison 6 Value Update Register

Offset: 0x194, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM6

PWM Comparison 6 Mode Register

Offset: 0x198, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD6

PWM Comparison 6 Mode Update Register

Offset: 0x19c, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMPV7

PWM Comparison 7 Value Register

Offset: 0x1a0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVM
rw 		CV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
rw
Toggle Fields

CV

Bits 0-23: Comparison x Value.

CVM

Bit 24: Comparison x Value Mode.

CMPVUPD7

PWM Comparison 7 Value Update Register

Offset: 0x1a4, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CVMUPD
w 		CVUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CVUPD
w
Toggle Fields

CVUPD

Bits 0-23: Comparison x Value Update.

CVMUPD

Bit 24: Comparison x Value Mode Update.

CMPM7

PWM Comparison 7 Mode Register

Offset: 0x1a8, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRCNT
rw 		CUPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRCNT
rw 		CPR
rw 		CTR
rw 		CEN
rw
Toggle Fields

CEN

Bit 0: Comparison x Enable.

CTR

Bits 4-7: Comparison x Trigger.

CPR

Bits 8-11: Comparison x Period.

CPRCNT

Bits 12-15: Comparison x Period Counter.

CUPR

Bits 16-19: Comparison x Update Period.

CUPRCNT

Bits 20-23: Comparison x Update Period Counter.

CMPMUPD7

PWM Comparison 7 Mode Update Register

Offset: 0x1ac, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CUPRUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRUPD
w 		CTRUPD
w 		CENUPD
w
Toggle Fields

CENUPD

Bit 0: Comparison x Enable Update.

CTRUPD

Bits 4-7: Comparison x Trigger Update.

CPRUPD

Bits 8-11: Comparison x Period Update.

CUPRUPD

Bits 16-19: Comparison x Update Period Update.

CMR0

PWM Channel Mode Register (ch_num = 0)

Offset: 0x200, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY0

PWM Channel Duty Cycle Register (ch_num = 0)

Offset: 0x204, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD0

PWM Channel Duty Cycle Update Register (ch_num = 0)

Offset: 0x208, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD0

PWM Channel Period Register (ch_num = 0)

Offset: 0x20c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD0

PWM Channel Period Update Register (ch_num = 0)

Offset: 0x210, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT0

PWM Channel Counter Register (ch_num = 0)

Offset: 0x214, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT0

PWM Channel Dead Time Register (ch_num = 0)

Offset: 0x218, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD0

PWM Channel Dead Time Update Register (ch_num = 0)

Offset: 0x21c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

CMR1

PWM Channel Mode Register (ch_num = 1)

Offset: 0x220, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY1

PWM Channel Duty Cycle Register (ch_num = 1)

Offset: 0x224, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD1

PWM Channel Duty Cycle Update Register (ch_num = 1)

Offset: 0x228, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD1

PWM Channel Period Register (ch_num = 1)

Offset: 0x22c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD1

PWM Channel Period Update Register (ch_num = 1)

Offset: 0x230, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT1

PWM Channel Counter Register (ch_num = 1)

Offset: 0x234, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT1

PWM Channel Dead Time Register (ch_num = 1)

Offset: 0x238, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD1

PWM Channel Dead Time Update Register (ch_num = 1)

Offset: 0x23c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

CMR2

PWM Channel Mode Register (ch_num = 2)

Offset: 0x240, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY2

PWM Channel Duty Cycle Register (ch_num = 2)

Offset: 0x244, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD2

PWM Channel Duty Cycle Update Register (ch_num = 2)

Offset: 0x248, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD2

PWM Channel Period Register (ch_num = 2)

Offset: 0x24c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD2

PWM Channel Period Update Register (ch_num = 2)

Offset: 0x250, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT2

PWM Channel Counter Register (ch_num = 2)

Offset: 0x254, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT2

PWM Channel Dead Time Register (ch_num = 2)

Offset: 0x258, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD2

PWM Channel Dead Time Update Register (ch_num = 2)

Offset: 0x25c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

CMR3

PWM Channel Mode Register (ch_num = 3)

Offset: 0x260, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY3

PWM Channel Duty Cycle Register (ch_num = 3)

Offset: 0x264, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD3

PWM Channel Duty Cycle Update Register (ch_num = 3)

Offset: 0x268, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD3

PWM Channel Period Register (ch_num = 3)

Offset: 0x26c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD3

PWM Channel Period Update Register (ch_num = 3)

Offset: 0x270, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT3

PWM Channel Counter Register (ch_num = 3)

Offset: 0x274, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT3

PWM Channel Dead Time Register (ch_num = 3)

Offset: 0x278, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD3

PWM Channel Dead Time Update Register (ch_num = 3)

Offset: 0x27c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

CMR4

PWM Channel Mode Register (ch_num = 4)

Offset: 0x280, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY4

PWM Channel Duty Cycle Register (ch_num = 4)

Offset: 0x284, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD4

PWM Channel Duty Cycle Update Register (ch_num = 4)

Offset: 0x288, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD4

PWM Channel Period Register (ch_num = 4)

Offset: 0x28c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD4

PWM Channel Period Update Register (ch_num = 4)

Offset: 0x290, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT4

PWM Channel Counter Register (ch_num = 4)

Offset: 0x294, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT4

PWM Channel Dead Time Register (ch_num = 4)

Offset: 0x298, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD4

PWM Channel Dead Time Update Register (ch_num = 4)

Offset: 0x29c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

CMR5

PWM Channel Mode Register (ch_num = 5)

Offset: 0x2a0, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY5

PWM Channel Duty Cycle Register (ch_num = 5)

Offset: 0x2a4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD5

PWM Channel Duty Cycle Update Register (ch_num = 5)

Offset: 0x2a8, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD5

PWM Channel Period Register (ch_num = 5)

Offset: 0x2ac, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD5

PWM Channel Period Update Register (ch_num = 5)

Offset: 0x2b0, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT5

PWM Channel Counter Register (ch_num = 5)

Offset: 0x2b4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT5

PWM Channel Dead Time Register (ch_num = 5)

Offset: 0x2b8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD5

PWM Channel Dead Time Update Register (ch_num = 5)

Offset: 0x2bc, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

CMR6

PWM Channel Mode Register (ch_num = 6)

Offset: 0x2c0, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY6

PWM Channel Duty Cycle Register (ch_num = 6)

Offset: 0x2c4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD6

PWM Channel Duty Cycle Update Register (ch_num = 6)

Offset: 0x2c8, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD6

PWM Channel Period Register (ch_num = 6)

Offset: 0x2cc, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD6

PWM Channel Period Update Register (ch_num = 6)

Offset: 0x2d0, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT6

PWM Channel Counter Register (ch_num = 6)

Offset: 0x2d4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT6

PWM Channel Dead Time Register (ch_num = 6)

Offset: 0x2d8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD6

PWM Channel Dead Time Update Register (ch_num = 6)

Offset: 0x2dc, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

CMR7

PWM Channel Mode Register (ch_num = 7)

Offset: 0x2e0, reset: 0x00000000, access: read-write

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLI
rw 		DTHI
rw 		DTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CES
rw 		CPOL
rw 		CALG
rw 		CPRE
rw
Toggle Fields

CPRE

Bits 0-3: Channel Pre-scaler.

Allowed values:
0x0: MCK: Master clock
0x1: MCK_DIV_2: Master clock/2
0x2: MCK_DIV_4: Master clock/4
0x3: MCK_DIV_8: Master clock/8
0x4: MCK_DIV_16: Master clock/16
0x5: MCK_DIV_32: Master clock/32
0x6: MCK_DIV_64: Master clock/64
0x7: MCK_DIV_128: Master clock/128
0x8: MCK_DIV_256: Master clock/256
0x9: MCK_DIV_512: Master clock/512
0xA: MCK_DIV_1024: Master clock/1024
0xB: CLKA: Clock A
0xC: CLKB: Clock B

CALG

Bit 8: Channel Alignment.

CPOL

Bit 9: Channel Polarity.

CES

Bit 10: Counter Event Selection.

DTE

Bit 16: Dead-Time Generator Enable.

DTHI

Bit 17: Dead-Time PWMHx Output Inverted.

DTLI

Bit 18: Dead-Time PWMLx Output Inverted.

CDTY7

PWM Channel Duty Cycle Register (ch_num = 7)

Offset: 0x2e4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTY
rw
Toggle Fields

CDTY

Bits 0-23: Channel Duty-Cycle.

CDTYUPD7

PWM Channel Duty Cycle Update Register (ch_num = 7)

Offset: 0x2e8, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDTYUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDTYUPD
w
Toggle Fields

CDTYUPD

Bits 0-23: Channel Duty-Cycle Update.

CPRD7

PWM Channel Period Register (ch_num = 7)

Offset: 0x2ec, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRD
rw
Toggle Fields

CPRD

Bits 0-23: Channel Period.

CPRDUPD7

PWM Channel Period Update Register (ch_num = 7)

Offset: 0x2f0, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPRDUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPRDUPD
w
Toggle Fields

CPRDUPD

Bits 0-23: Channel Period Update.

CCNT7

PWM Channel Counter Register (ch_num = 7)

Offset: 0x2f4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields

CNT

Bits 0-23: Channel Counter Register.

DT7

PWM Channel Dead Time Register (ch_num = 7)

Offset: 0x2f8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH
rw
Toggle Fields

DTH

Bits 0-15: Dead-Time Value for PWMHx Output.

DTL

Bits 16-31: Dead-Time Value for PWMLx Output.

DTUPD7

PWM Channel Dead Time Update Register (ch_num = 7)

Offset: 0x2fc, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTLUPD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTHUPD
w
Toggle Fields

DTHUPD

Bits 0-15: Dead-Time Value Update for PWMHx Output.

DTLUPD

Bits 16-31: Dead-Time Value Update for PWMLx Output.

RSTC

0x400e1a00: Reset Controller

6/12 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 MR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTRST
w 		PERRST
w 		PROCRST
w
Toggle Fields

PROCRST

Bit 0: Processor Reset.

PERRST

Bit 2: Peripheral Reset.

EXTRST

Bit 3: External Reset.

KEY

Bits 24-31: System Reset Key.

Allowed values:
0xA5: PASSWD: Writing any other value in this field aborts the write operation.

SR

Status Register

Offset: 0x4, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRCMP
r 		NRSTL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTTYP
r 		URSTS
r
Toggle Fields

URSTS

Bit 0: User Reset Status.

RSTTYP

Bits 8-10: Reset Type.

Allowed values:
0x0: GeneralReset: First power-up Reset
0x1: BackupReset: Return from Backup Mode
0x2: WatchdogReset: Watchdog fault occurred
0x3: SoftwareReset: Processor reset required by the software
0x4: UserReset: NRST pin detected low

NRSTL

Bit 16: NRST Pin Level.

SRCMP

Bit 17: Software Reset Command in Progress.

MR

Mode Register

Offset: 0x8, reset: 0x00000001, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERSTL
rw 		URSTIEN
rw 		URSTEN
rw
Toggle Fields

URSTEN

Bit 0: User Reset Enable.

URSTIEN

Bit 4: User Reset Interrupt Enable.

ERSTL

Bits 8-11: External Reset Length.

KEY

Bits 24-31: Write Access Password.

Allowed values:
0xA5: PASSWD: Writing any other value in this field aborts the write operation.Always reads as 0.

RTC

0x400e1a60: Real-time Clock

17/56 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MR
0x8 TIMR
0xc CALR
0x10 TIMALR
0x14 CALALR
0x18 SR
0x1c SCCR
0x20 IER
0x24 IDR
0x28 IMR
0x2c VER
0xe4 WPMR

CR

Control Register

Offset: 0x0, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALEVSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEVSEL
rw 		UPDCAL
rw 		UPDTIM
rw
Toggle Fields

UPDTIM

Bit 0: Update Request Time Register.

UPDCAL

Bit 1: Update Request Calendar Register.

TIMEVSEL

Bits 8-9: Time Event Selection.

Allowed values:
0x0: MINUTE: Minute change
0x1: HOUR: Hour change
0x2: MIDNIGHT: Every day at midnight
0x3: NOON: Every day at noon

CALEVSEL

Bits 16-17: Calendar Event Selection.

Allowed values:
0x0: WEEK: Week change (every Monday at time 00:00:00)
0x1: MONTH: Month change (every 01 of each month at time 00:00:00)
0x2: YEAR: Year change (every January 1 at time 00:00:00)

MR

Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRMOD
rw
Toggle Fields

HRMOD

Bit 0: 12-/24-hour Mode.

TIMR

Time Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AMPM
rw 		HOUR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN
rw 		SEC
rw
Toggle Fields

SEC

Bits 0-6: Current Second.

MIN

Bits 8-14: Current Minute.

HOUR

Bits 16-21: Current Hour.

AMPM

Bit 22: Ante Meridiem Post Meridiem Indicator.

CALR

Calendar Register

Offset: 0xc, reset: 0x01210720, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATE
rw 		DAY
rw 		MONTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
YEAR
rw 		CENT
rw
Toggle Fields

CENT

Bits 0-6: Current Century.

YEAR

Bits 8-15: Current Year.

MONTH

Bits 16-20: Current Month.

DAY

Bits 21-23: Current Day in Current Week.

DATE

Bits 24-29: Current Day in Current Month.

TIMALR

Time Alarm Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HOUREN
rw 		AMPM
rw 		HOUR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINEN
rw 		MIN
rw 		SECEN
rw 		SEC
rw
Toggle Fields

SEC

Bits 0-6: Second Alarm.

SECEN

Bit 7: Second Alarm Enable.

MIN

Bits 8-14: Minute Alarm.

MINEN

Bit 15: Minute Alarm Enable.

HOUR

Bits 16-21: Hour Alarm.

AMPM

Bit 22: AM/PM Indicator.

HOUREN

Bit 23: Hour Alarm Enable.

CALALR

Calendar Alarm Register

Offset: 0x14, reset: 0x01010000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATEEN
rw 		DATE
rw 		MTHEN
rw 		MONTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

MONTH

Bits 16-20: Month Alarm.

MTHEN

Bit 23: Month Alarm Enable.

DATE

Bits 24-29: Date Alarm.

DATEEN

Bit 31: Date Alarm Enable.

SR

Status Register

Offset: 0x18, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALEV
r 		TIMEV
r 		SEC
r 		ALARM
r 		ACKUPD
r
Toggle Fields

ACKUPD

Bit 0: Acknowledge for Update.

Allowed values:
0: FREERUN: Time and calendar registers cannot be updated.
1: UPDATE: Time and calendar registers can be updated.

ALARM

Bit 1: Alarm Flag.

Allowed values:
0: NO_ALARMEVENT: No alarm matching condition occurred.
1: ALARMEVENT: An alarm matching condition has occurred.

SEC

Bit 2: Second Event.

Allowed values:
0: NO_SECEVENT: No second event has occurred since the last clear.
1: SECEVENT: At least one second event has occurred since the last clear.

TIMEV

Bit 3: Time Event.

Allowed values:
0: NO_TIMEVENT: No time event has occurred since the last clear.
1: TIMEVENT: At least one time event has occurred since the last clear.

CALEV

Bit 4: Calendar Event.

Allowed values:
0: NO_CALEVENT: No calendar event has occurred since the last clear.
1: CALEVENT: At least one calendar event has occurred since the last clear.

SCCR

Status Clear Command Register

Offset: 0x1c, reset: None, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALCLR
w 		TIMCLR
w 		SECCLR
w 		ALRCLR
w 		ACKCLR
w
Toggle Fields

ACKCLR

Bit 0: Acknowledge Clear.

ALRCLR

Bit 1: Alarm Clear.

SECCLR

Bit 2: Second Clear.

TIMCLR

Bit 3: Time Clear.

CALCLR

Bit 4: Calendar Clear.

IER

Interrupt Enable Register

Offset: 0x20, reset: None, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALEN
w 		TIMEN
w 		SECEN
w 		ALREN
w 		ACKEN
w
Toggle Fields

ACKEN

Bit 0: Acknowledge Update Interrupt Enable.

ALREN

Bit 1: Alarm Interrupt Enable.

SECEN

Bit 2: Second Event Interrupt Enable.

TIMEN

Bit 3: Time Event Interrupt Enable.

CALEN

Bit 4: Calendar Event Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x24, reset: None, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALDIS
w 		TIMDIS
w 		SECDIS
w 		ALRDIS
w 		ACKDIS
w
Toggle Fields

ACKDIS

Bit 0: Acknowledge Update Interrupt Disable.

ALRDIS

Bit 1: Alarm Interrupt Disable.

SECDIS

Bit 2: Second Event Interrupt Disable.

TIMDIS

Bit 3: Time Event Interrupt Disable.

CALDIS

Bit 4: Calendar Event Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x28, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAL
r 		TIM
r 		SEC
r 		ALR
r 		ACK
r
Toggle Fields

ACK

Bit 0: Acknowledge Update Interrupt Mask.

ALR

Bit 1: Alarm Interrupt Mask.

SEC

Bit 2: Second Event Interrupt Mask.

TIM

Bit 3: Time Event Interrupt Mask.

CAL

Bit 4: Calendar Event Interrupt Mask.

VER

Valid Entry Register

Offset: 0x2c, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NVCALALR
r 		NVTIMALR
r 		NVCAL
r 		NVTIM
r
Toggle Fields

NVTIM

Bit 0: Non-valid Time.

NVCAL

Bit 1: Non-valid Calendar.

NVTIMALR

Bit 2: Non-valid Time Alarm.

NVCALALR

Bit 3: Non-valid Calendar Alarm.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x525443: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

RTT

0x400e1a30: Real-time Timer

3/8 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MR
0x4 AR
0x8 VR
0xc SR

MR

Mode Register

Offset: 0x0, reset: 0x00008000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTTRST
rw 		RTTINCIEN
rw 		ALMIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTPRES
rw
Toggle Fields

RTPRES

Bits 0-15: Real-time Timer Prescaler Value.

ALMIEN

Bit 16: Alarm Interrupt Enable.

RTTINCIEN

Bit 17: Real-time Timer Increment Interrupt Enable.

RTTRST

Bit 18: Real-time Timer Restart.

AR

Alarm Register

Offset: 0x4, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALMV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALMV
rw
Toggle Fields

ALMV

Bits 0-31: Alarm Value.

VR

Value Register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRTV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRTV
r
Toggle Fields

CRTV

Bits 0-31: Current Real-time Value.

SR

Status Register

Offset: 0xc, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTTINC
r 		ALMS
r
Toggle Fields

ALMS

Bit 0: Real-time Alarm Status.

RTTINC

Bit 1: Real-time Timer Increment.

SMC

0x400e0000: Static Memory Controller

184/386 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFG
0x4 CTRL
0x8 SR
0xc IER
0x10 IDR
0x14 IMR
0x18 ADDR
0x1c BANK
0x20 ECC_CTRL
0x24 ECC_MD
0x28 ECC_SR1
0x2c ECC_PR0
0x2c ECC_PR0_W8BIT
0x2c ECC_PR0_W9BIT
0x30 ECC_PR1
0x30 ECC_PR1_W8BIT
0x30 ECC_PR1_W9BIT
0x34 ECC_SR2
0x38 ECC_PR2
0x38 ECC_PR2_W8BIT
0x3c ECC_PR3
0x3c ECC_PR3_W8BIT
0x40 ECC_PR4
0x40 ECC_PR4_W8BIT
0x44 ECC_PR5
0x44 ECC_PR5_W8BIT
0x48 ECC_PR6
0x48 ECC_PR6_W8BIT
0x4c ECC_PR7
0x4c ECC_PR7_W8BIT
0x50 ECC_PR8
0x54 ECC_PR9
0x58 ECC_PR10
0x5c ECC_PR11
0x60 ECC_PR12
0x64 ECC_PR13
0x68 ECC_PR14
0x6c ECC_PR15
0x70 SETUP0
0x74 PULSE0
0x78 CYCLE0
0x7c TIMINGS0
0x80 MODE0
0x84 SETUP1
0x88 PULSE1
0x8c CYCLE1
0x90 TIMINGS1
0x94 MODE1
0x98 SETUP2
0x9c PULSE2
0xa0 CYCLE2
0xa4 TIMINGS2
0xa8 MODE2
0xac SETUP3
0xb0 PULSE3
0xb4 CYCLE3
0xb8 TIMINGS3
0xbc MODE3
0xc0 SETUP4
0xc4 PULSE4
0xc8 CYCLE4
0xcc TIMINGS4
0xd0 MODE4
0xd4 SETUP5
0xd8 PULSE5
0xdc CYCLE5
0xe0 TIMINGS5
0xe4 MODE5
0xe8 SETUP6
0xec PULSE6
0xf0 CYCLE6
0xf4 TIMINGS6
0xf8 MODE6
0xfc SETUP7
0x100 PULSE7
0x104 CYCLE7
0x108 TIMINGS7
0x10c MODE7
0x110 OCMS
0x114 KEY1
0x118 KEY2
0x1e4 WPCR
0x1e8 WPSR

CFG

SMC NFC Configuration Register

Offset: 0x0, reset: 0x00000000, access: read-write

2/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTOMUL
rw 		DTOCYC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBEDGE
rw 		EDGECTRL
rw 		RSPARE
rw 		WSPARE
rw 		PAGESIZE
rw
Toggle Fields

PAGESIZE

Bits 0-1: Page Size of the NAND Flash Device.

Allowed values:
0x0: PS512: Main area 512 Bytes
0x1: PS1024: Main area 1024 Bytes
0x2: PS2048: Main area 2048 Bytes
0x3: PS4096: Main area 4096 Bytes

WSPARE

Bit 8: Write Spare Area.

RSPARE

Bit 9: Read Spare Area.

EDGECTRL

Bit 12: Rising/Falling Edge Detection Control.

RBEDGE

Bit 13: Ready/Busy Signal Edge Detection.

DTOCYC

Bits 16-19: Data Timeout Cycle Number.

DTOMUL

Bits 20-22: Data Timeout Multiplier.

Allowed values:
0x0: X1: DTOCYC
0x1: X16: DTOCYC x 16
0x2: X128: DTOCYC x 128
0x3: X256: DTOCYC x 256
0x4: X1024: DTOCYC x 1024
0x5: X4096: DTOCYC x 4096
0x6: X65536: DTOCYC x 65536
0x7: X1048576: DTOCYC x 1048576

CTRL

SMC NFC Control Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFCDIS
w 		NFCEN
w
Toggle Fields

NFCEN

Bit 0: NAND Flash Controller Enable.

NFCDIS

Bit 1: NAND Flash Controller Disable.

SR

SMC NFC Status Register

Offset: 0x8, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB_EDGE0
r 		NFCASE
r 		AWB
r 		UNDEF
r 		DTOE
r 		CMDDONE
r 		XFRDONE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFCSID
r 		NFCWR
r 		NFCBUSY
r 		RB_FALL
r 		RB_RISE
r 		SMCSTS
r
Toggle Fields

SMCSTS

Bit 0: NAND Flash Controller status (this field cannot be reset).

RB_RISE

Bit 4: Selected Ready Busy Rising Edge Detected.

RB_FALL

Bit 5: Selected Ready Busy Falling Edge Detected.

NFCBUSY

Bit 8: NFC Busy (this field cannot be reset).

NFCWR

Bit 11: NFC Write/Read Operation (this field cannot be reset).

NFCSID

Bits 12-14: NFC Chip Select ID (this field cannot be reset).

XFRDONE

Bit 16: NFC Data Transfer Terminated.

CMDDONE

Bit 17: Command Done.

DTOE

Bit 20: Data Timeout Error.

UNDEF

Bit 21: Undefined Area Error.

AWB

Bit 22: Accessing While Busy.

NFCASE

Bit 23: NFC Access Size Error.

RB_EDGE0

Bit 24: Ready/Busy Line 0 Edge Detected.

IER

SMC NFC Interrupt Enable Register

Offset: 0xc, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB_EDGE0
w 		NFCASE
w 		AWB
w 		UNDEF
w 		DTOE
w 		CMDDONE
w 		XFRDONE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB_FALL
w 		RB_RISE
w
Toggle Fields

RB_RISE

Bit 4: Ready Busy Rising Edge Detection Interrupt Enable.

RB_FALL

Bit 5: Ready Busy Falling Edge Detection Interrupt Enable.

XFRDONE

Bit 16: Transfer Done Interrupt Enable.

CMDDONE

Bit 17: Command Done Interrupt Enable.

DTOE

Bit 20: Data Timeout Error Interrupt Enable.

UNDEF

Bit 21: Undefined Area Access Interrupt Enable.

AWB

Bit 22: Accessing While Busy Interrupt Enable.

NFCASE

Bit 23: NFC Access Size Error Interrupt Enable.

RB_EDGE0

Bit 24: Ready/Busy Line 0 Interrupt Enable.

IDR

SMC NFC Interrupt Disable Register

Offset: 0x10, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB_EDGE0
w 		NFCASE
w 		AWB
w 		UNDEF
w 		DTOE
w 		CMDDONE
w 		XFRDONE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB_FALL
w 		RB_RISE
w
Toggle Fields

RB_RISE

Bit 4: Ready Busy Rising Edge Detection Interrupt Disable.

RB_FALL

Bit 5: Ready Busy Falling Edge Detection Interrupt Disable.

XFRDONE

Bit 16: Transfer Done Interrupt Disable.

CMDDONE

Bit 17: Command Done Interrupt Disable.

DTOE

Bit 20: Data Timeout Error Interrupt Disable.

UNDEF

Bit 21: Undefined Area Access Interrupt Disable.

AWB

Bit 22: Accessing While Busy Interrupt Disable.

NFCASE

Bit 23: NFC Access Size Error Interrupt Disable.

RB_EDGE0

Bit 24: Ready/Busy Line 0 Interrupt Disable.

IMR

SMC NFC Interrupt Mask Register

Offset: 0x14, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB_EDGE0
r 		NFCASE
r 		AWB
r 		UNDEF
r 		DTOE
r 		CMDDONE
r 		XFRDONE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB_FALL
r 		RB_RISE
r
Toggle Fields

RB_RISE

Bit 4: Ready Busy Rising Edge Detection Interrupt Mask.

RB_FALL

Bit 5: Ready Busy Falling Edge Detection Interrupt Mask.

XFRDONE

Bit 16: Transfer Done Interrupt Mask.

CMDDONE

Bit 17: Command Done Interrupt Mask.

DTOE

Bit 20: Data Timeout Error Interrupt Mask.

UNDEF

Bit 21: Undefined Area Access Interrupt Mask5.

AWB

Bit 22: Accessing While Busy Interrupt Mask.

NFCASE

Bit 23: NFC Access Size Error Interrupt Mask.

RB_EDGE0

Bit 24: Ready/Busy Line 0 Interrupt Mask.

ADDR

SMC NFC Address Cycle Zero Register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_CYCLE0
rw
Toggle Fields

ADDR_CYCLE0

Bits 0-7: NAND Flash Array Address cycle 0.

BANK

SMC Bank Address Register

Offset: 0x1c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BANK
rw
Toggle Fields

BANK

Bits 0-2: Bank Identifier.

ECC_CTRL

SMC ECC Control Register

Offset: 0x20, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
w 		RST
w
Toggle Fields

RST

Bit 0: Reset ECC.

SWRST

Bit 1: Software Reset.

ECC_MD

SMC ECC Mode Register

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPCORREC
rw 		ECC_PAGESIZE
rw
Toggle Fields

ECC_PAGESIZE

Bits 0-1: ECC Page Size.

Allowed values:
0x0: PS512: Main area 512 Words
0x1: PS1024: Main area 1024 Words
0x2: PS2048: Main area 2048 Words
0x3: PS4096: Main area 4096 Words

TYPCORREC

Bits 4-5: Type of Correction.

Allowed values:
0x0: CPAGE: 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash)
0x1: C256B: 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)
0x2: C512B: 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)

ECC_SR1

SMC ECC Status 1 Register

Offset: 0x28, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MULERR7
r 		ECCERR7
r 		RECERR7
r 		MULERR6
r 		ECCERR6
r 		RECERR6
r 		MULERR5
r 		ECCERR5
r 		RECERR5
r 		MULERR4
r 		ECCERR4
r 		RECERR4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MULERR3
r 		ECCERR3
r 		RECERR3
r 		MULERR2
r 		ECCERR2
r 		RECERR2
r 		MULERR1
r 		ECCERR1
r 		RECERR1
r 		MULERR0
r 		ECCERR0
r 		RECERR0
r
Toggle Fields

RECERR0

Bit 0: Recoverable Error.

ECCERR0

Bit 1: ECC Error.

MULERR0

Bit 2: Multiple Error.

RECERR1

Bit 4: Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes.

ECCERR1

Bit 5: ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes.

MULERR1

Bit 6: Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes.

RECERR2

Bit 8: Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes.

ECCERR2

Bit 9: ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes.

MULERR2

Bit 10: Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes.

RECERR3

Bit 12: Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes.

ECCERR3

Bit 13: ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes.

MULERR3

Bit 14: Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes.

RECERR4

Bit 16: Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes.

ECCERR4

Bit 17: ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes.

MULERR4

Bit 18: Multiple Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes.

RECERR5

Bit 20: Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes.

ECCERR5

Bit 21: ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes.

MULERR5

Bit 22: Multiple Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes.

RECERR6

Bit 24: Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes.

ECCERR6

Bit 25: ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes.

MULERR6

Bit 26: Multiple Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes.

RECERR7

Bit 28: Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes.

ECCERR7

Bit 29: ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes.

MULERR7

Bit 30: Multiple Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes.

ECC_PR0

SMC ECC Parity 0 Register

Offset: 0x2c, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-3: Bit Address.

WORDADDR

Bits 4-15: Word Address.

ECC_PR0_W8BIT

SMC ECC Parity 0 Register

Offset: 0x2c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR0_W9BIT

SMC ECC Parity 0 Register

Offset: 0x2c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_PR1

SMC ECC parity 1 Register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r
Toggle Fields

NPARITY

Bits 0-15: Parity N.

ECC_PR1_W8BIT

SMC ECC parity 1 Register

Offset: 0x30, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR1_W9BIT

SMC ECC parity 1 Register

Offset: 0x30, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_SR2

SMC ECC status 2 Register

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MULERR15
r 		ECCERR15
r 		RECERR15
r 		MULERR14
r 		ECCERR14
r 		RECERR14
r 		MULERR13
r 		ECCERR13
r 		RECERR13
r 		MULERR12
r 		ECCERR12
r 		RECERR12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MULERR11
r 		ECCERR11
r 		RECERR11
r 		MULERR10
r 		ECCERR10
r 		RECERR10
r 		MULERR9
r 		ECCERR9
r 		RECERR9
r 		MULERR8
r 		ECCERR8
r 		RECERR8
r
Toggle Fields

RECERR8

Bit 0: Recoverable Error in the page between the 2048th and the 2303rd bytes.

ECCERR8

Bit 1: ECC Error in the page between the 2048th and the 2303rd bytes.

MULERR8

Bit 2: Multiple Error in the page between the 2048th and the 2303rd bytes.

RECERR9

Bit 4: Recoverable Error in the page between the 2304th and the 2559th bytes.

ECCERR9

Bit 5: ECC Error in the page between the 2304th and the 2559th bytes.

MULERR9

Bit 6: Multiple Error in the page between the 2304th and the 2559th bytes.

RECERR10

Bit 8: Recoverable Error in the page between the 2560th and the 2815th bytes.

ECCERR10

Bit 9: ECC Error in the page between the 2560th and the 2815th bytes.

MULERR10

Bit 10: Multiple Error in the page between the 2560th and the 2815th bytes.

RECERR11

Bit 12: Recoverable Error in the page between the 2816th and the 3071st bytes.

ECCERR11

Bit 13: ECC Error in the page between the 2816th and the 3071st bytes.

MULERR11

Bit 14: Multiple Error in the page between the 2816th and the 3071st bytes.

RECERR12

Bit 16: Recoverable Error in the page between the 3072nd and the 3327th bytes.

ECCERR12

Bit 17: ECC Error in the page between the 3072nd and the 3327th bytes.

MULERR12

Bit 18: Multiple Error in the page between the 3072nd and the 3327th bytes.

RECERR13

Bit 20: Recoverable Error in the page between the 3328th and the 3583rd bytes.

ECCERR13

Bit 21: ECC Error in the page between the 3328th and the 3583rd bytes.

MULERR13

Bit 22: Multiple Error in the page between the 3328th and the 3583rd bytes.

RECERR14

Bit 24: Recoverable Error in the page between the 3584th and the 3839th bytes.

ECCERR14

Bit 25: ECC Error in the page between the 3584th and the 3839th bytes.

MULERR14

Bit 26: Multiple Error in the page between the 3584th and the 3839th bytes.

RECERR15

Bit 28: Recoverable Error in the page between the 3840th and the 4095th bytes.

ECCERR15

Bit 29: ECC Error in the page between the 3840th and the 4095th bytes.

MULERR15

Bit 30: Multiple Error in the page between the 3840th and the 4095th bytes.

ECC_PR2

SMC ECC parity 2 Register

Offset: 0x38, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_PR2_W8BIT

SMC ECC parity 2 Register

Offset: 0x38, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR3

SMC ECC parity 3 Register

Offset: 0x3c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_PR3_W8BIT

SMC ECC parity 3 Register

Offset: 0x3c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR4

SMC ECC parity 4 Register

Offset: 0x40, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_PR4_W8BIT

SMC ECC parity 4 Register

Offset: 0x40, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR5

SMC ECC parity 5 Register

Offset: 0x44, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_PR5_W8BIT

SMC ECC parity 5 Register

Offset: 0x44, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR6

SMC ECC parity 6 Register

Offset: 0x48, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_PR6_W8BIT

SMC ECC parity 6 Register

Offset: 0x48, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR7

SMC ECC parity 7 Register

Offset: 0x4c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-11: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-23: Parity N.

ECC_PR7_W8BIT

SMC ECC parity 7 Register

Offset: 0x4c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR8

SMC ECC parity 8 Register

Offset: 0x50, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR9

SMC ECC parity 9 Register

Offset: 0x54, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR10

SMC ECC parity 10 Register

Offset: 0x58, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR11

SMC ECC parity 11 Register

Offset: 0x5c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR12

SMC ECC parity 12 Register

Offset: 0x60, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR13

SMC ECC parity 13 Register

Offset: 0x64, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR14

SMC ECC parity 14 Register

Offset: 0x68, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

ECC_PR15

SMC ECC parity 15 Register

Offset: 0x6c, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPARITY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPARITY
r 		WORDADDR
r 		BITADDR
r
Toggle Fields

BITADDR

Bits 0-2: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

WORDADDR

Bits 3-10: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes.

NPARITY

Bits 12-22: Parity N.

SETUP0

SMC Setup Register (CS_number = 0)

Offset: 0x70, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE0

SMC Pulse Register (CS_number = 0)

Offset: 0x74, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE0

SMC Cycle Register (CS_number = 0)

Offset: 0x78, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS0

SMC Timings Register (CS_number = 0)

Offset: 0x7c, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE0

SMC Mode Register (CS_number = 0)

Offset: 0x80, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

SETUP1

SMC Setup Register (CS_number = 1)

Offset: 0x84, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE1

SMC Pulse Register (CS_number = 1)

Offset: 0x88, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE1

SMC Cycle Register (CS_number = 1)

Offset: 0x8c, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS1

SMC Timings Register (CS_number = 1)

Offset: 0x90, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE1

SMC Mode Register (CS_number = 1)

Offset: 0x94, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

SETUP2

SMC Setup Register (CS_number = 2)

Offset: 0x98, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE2

SMC Pulse Register (CS_number = 2)

Offset: 0x9c, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE2

SMC Cycle Register (CS_number = 2)

Offset: 0xa0, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS2

SMC Timings Register (CS_number = 2)

Offset: 0xa4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE2

SMC Mode Register (CS_number = 2)

Offset: 0xa8, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

SETUP3

SMC Setup Register (CS_number = 3)

Offset: 0xac, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE3

SMC Pulse Register (CS_number = 3)

Offset: 0xb0, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE3

SMC Cycle Register (CS_number = 3)

Offset: 0xb4, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS3

SMC Timings Register (CS_number = 3)

Offset: 0xb8, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE3

SMC Mode Register (CS_number = 3)

Offset: 0xbc, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

SETUP4

SMC Setup Register (CS_number = 4)

Offset: 0xc0, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE4

SMC Pulse Register (CS_number = 4)

Offset: 0xc4, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE4

SMC Cycle Register (CS_number = 4)

Offset: 0xc8, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS4

SMC Timings Register (CS_number = 4)

Offset: 0xcc, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE4

SMC Mode Register (CS_number = 4)

Offset: 0xd0, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

SETUP5

SMC Setup Register (CS_number = 5)

Offset: 0xd4, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE5

SMC Pulse Register (CS_number = 5)

Offset: 0xd8, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE5

SMC Cycle Register (CS_number = 5)

Offset: 0xdc, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS5

SMC Timings Register (CS_number = 5)

Offset: 0xe0, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE5

SMC Mode Register (CS_number = 5)

Offset: 0xe4, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

SETUP6

SMC Setup Register (CS_number = 6)

Offset: 0xe8, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE6

SMC Pulse Register (CS_number = 6)

Offset: 0xec, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE6

SMC Cycle Register (CS_number = 6)

Offset: 0xf0, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS6

SMC Timings Register (CS_number = 6)

Offset: 0xf4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE6

SMC Mode Register (CS_number = 6)

Offset: 0xf8, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

SETUP7

SMC Setup Register (CS_number = 7)

Offset: 0xfc, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_SETUP
rw 		NRD_SETUP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_SETUP
rw 		NWE_SETUP
rw
Toggle Fields

NWE_SETUP

Bits 0-5: NWE Setup Length.

NCS_WR_SETUP

Bits 8-13: NCS Setup Length in Write Access.

NRD_SETUP

Bits 16-21: NRD Setup Length.

NCS_RD_SETUP

Bits 24-29: NCS Setup Length in Read Access.

PULSE7

SMC Pulse Register (CS_number = 7)

Offset: 0x100, reset: 0x01010101, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCS_RD_PULSE
rw 		NRD_PULSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCS_WR_PULSE
rw 		NWE_PULSE
rw
Toggle Fields

NWE_PULSE

Bits 0-6: NWE Pulse Length.

NCS_WR_PULSE

Bits 8-14: NCS Pulse Length in WRITE Access.

NRD_PULSE

Bits 16-22: NRD Pulse Length.

NCS_RD_PULSE

Bits 24-30: NCS Pulse Length in READ Access.

CYCLE7

SMC Cycle Register (CS_number = 7)

Offset: 0x104, reset: 0x00030003, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NRD_CYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWE_CYCLE
rw
Toggle Fields

NWE_CYCLE

Bits 0-8: Total Write Cycle Length.

NRD_CYCLE

Bits 16-24: Total Read Cycle Length.

TIMINGS7

SMC Timings Register (CS_number = 7)

Offset: 0x108, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFSEL
rw 		RBNSEL
rw 		TWB
rw 		TRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCMS
rw 		TAR
rw 		TADL
rw 		TCLR
rw
Toggle Fields

TCLR

Bits 0-3: CLE to REN Low Delay.

TADL

Bits 4-7: ALE to Data Start.

TAR

Bits 8-11: ALE to REN Low Delay.

OCMS

Bit 12: Off Chip Memory Scrambling Enable.

TRR

Bits 16-19: Ready to REN Low Delay.

TWB

Bits 24-27: WEN High to REN to Busy.

RBNSEL

Bits 28-30: Ready/Busy Line Selection.

NFSEL

Bit 31: NAND Flash Selection.

MODE7

SMC Mode Register (CS_number = 7)

Offset: 0x10c, reset: 0x10000003, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDF_MODE
rw 		TDF_CYCLES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBW
rw 		BAT
rw 		EXNW_MODE
rw 		WRITE_MODE
rw 		READ_MODE
rw
Toggle Fields

READ_MODE

Bit 0: Selection of the Control Signal for Read Operation.

Allowed values:
0: NCS_CTRL: The Read operation is controlled by the NCS signal.
1: NRD_CTRL: The Read operation is controlled by the NRD signal.

WRITE_MODE

Bit 1: Selection of the Control Signal for Write Operation.

Allowed values:
0: NCS_CTRL: The Write operation is controller by the NCS signal.
1: NWE_CTRL: The Write operation is controlled by the NWE signal.

EXNW_MODE

Bits 4-5: NWAIT Mode.

Allowed values:
0x0: DISABLED: Disabled
0x2: FROZEN: Frozen Mode
0x3: READY: Ready Mode

BAT

Bit 8: Byte Access Type.

DBW

Bit 12: Data Bus Width.

Allowed values:
0: BIT_8: 8-bit bus
1: BIT_16: 16-bit bus

TDF_CYCLES

Bits 16-19: Data Float Time.

TDF_MODE

Bit 20: TDF Optimization.

OCMS

SMC OCMS Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRSE
rw 		SMSE
rw
Toggle Fields

SMSE

Bit 0: Static Memory Controller Scrambling Enable.

SRSE

Bit 1: SRAM Scrambling Enable.

KEY1

SMC OCMS KEY1 Register

Offset: 0x114, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
w
Toggle Fields

KEY1

Bits 0-31: Off Chip Memory Scrambling (OCMS) Key Part 1.

KEY2

SMC OCMS KEY2 Register

Offset: 0x118, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
w
Toggle Fields

KEY2

Bits 0-31: Off Chip Memory Scrambling (OCMS) Key Part 2.

WPCR

Write Protection Control Register

Offset: 0x1e4, reset: 0x00000000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WP_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WP_KEY
w 		WP_EN
w
Toggle Fields

WP_EN

Bit 0: Write Protection Enable.

WP_KEY

Bits 8-31: Write Protection KEY Password.

Allowed values:
0x534D43: PASSWD: Writing any other value in this field aborts the write operation of the WP_EN bit. Always reads as 0.

WPSR

Write Protection Status Register

Offset: 0x1e8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WP_VSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WP_VSRC
r 		WP_VS
r
Toggle Fields

WP_VS

Bits 0-3: Write Protection Violation Status.

WP_VSRC

Bits 8-23: Write Protection Violation Source.

SPI0

0x40008000: Serial Peripheral Interface 0

24/82 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MR
0x8 RDR
0xc TDR
0x10 SR
0x14 IER
0x18 IDR
0x1c IMR
0x30 CSR[[0]]
0x34 CSR[[1]]
0x38 CSR[[2]]
0x3c CSR[[3]]
0xe4 WPMR
0xe8 WPSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LASTXFER
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
w 		SPIDIS
w 		SPIEN
w
Toggle Fields

SPIEN

Bit 0: SPI Enable.

SPIDIS

Bit 1: SPI Disable.

SWRST

Bit 7: SPI Software Reset.

LASTXFER

Bit 24: Last Transfer.

MR

Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYBCS
rw 		PCS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LLB
rw 		WDRBT
rw 		MODFDIS
rw 		PCSDEC
rw 		PS
rw 		MSTR
rw
Toggle Fields

MSTR

Bit 0: Master/Slave Mode.

PS

Bit 1: Peripheral Select.

PCSDEC

Bit 2: Chip Select Decode.

MODFDIS

Bit 4: Mode Fault Detection.

WDRBT

Bit 5: Wait Data Read Before Transfer.

LLB

Bit 7: Local Loopback Enable.

PCS

Bits 16-19: Peripheral Chip Select.

DLYBCS

Bits 24-31: Delay Between Chip Selects.

RDR

Receive Data Register

Offset: 0x8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD
r
Toggle Fields

RD

Bits 0-15: Receive Data.

PCS

Bits 16-19: Peripheral Chip Select.

TDR

Transmit Data Register

Offset: 0xc, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LASTXFER
w 		PCS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TD
w
Toggle Fields

TD

Bits 0-15: Transmit Data.

PCS

Bits 16-19: Peripheral Chip Select.

LASTXFER

Bit 24: Last Transfer.

SR

Status Register

Offset: 0x10, reset: 0x000000F0, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPIENS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNDES
r 		TXEMPTY
r 		NSSR
r 		OVRES
r 		MODF
r 		TDRE
r 		RDRF
r
Toggle Fields

RDRF

Bit 0: Receive Data Register Full.

TDRE

Bit 1: Transmit Data Register Empty.

MODF

Bit 2: Mode Fault Error.

OVRES

Bit 3: Overrun Error Status.

NSSR

Bit 8: NSS Rising.

TXEMPTY

Bit 9: Transmission Registers Empty.

UNDES

Bit 10: Underrun Error Status (Slave Mode Only).

SPIENS

Bit 16: SPI Enable Status.

IER

Interrupt Enable Register

Offset: 0x14, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNDES
w 		TXEMPTY
w 		NSSR
w 		OVRES
w 		MODF
w 		TDRE
w 		RDRF
w
Toggle Fields

RDRF

Bit 0: Receive Data Register Full Interrupt Enable.

TDRE

Bit 1: SPI Transmit Data Register Empty Interrupt Enable.

MODF

Bit 2: Mode Fault Error Interrupt Enable.

OVRES

Bit 3: Overrun Error Interrupt Enable.

NSSR

Bit 8: NSS Rising Interrupt Enable.

TXEMPTY

Bit 9: Transmission Registers Empty Enable.

UNDES

Bit 10: Underrun Error Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x18, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNDES
w 		TXEMPTY
w 		NSSR
w 		OVRES
w 		MODF
w 		TDRE
w 		RDRF
w
Toggle Fields

RDRF

Bit 0: Receive Data Register Full Interrupt Disable.

TDRE

Bit 1: SPI Transmit Data Register Empty Interrupt Disable.

MODF

Bit 2: Mode Fault Error Interrupt Disable.

OVRES

Bit 3: Overrun Error Interrupt Disable.

NSSR

Bit 8: NSS Rising Interrupt Disable.

TXEMPTY

Bit 9: Transmission Registers Empty Disable.

UNDES

Bit 10: Underrun Error Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x1c, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNDES
r 		TXEMPTY
r 		NSSR
r 		OVRES
r 		MODF
r 		TDRE
r 		RDRF
r
Toggle Fields

RDRF

Bit 0: Receive Data Register Full Interrupt Mask.

TDRE

Bit 1: SPI Transmit Data Register Empty Interrupt Mask.

MODF

Bit 2: Mode Fault Error Interrupt Mask.

OVRES

Bit 3: Overrun Error Interrupt Mask.

NSSR

Bit 8: NSS Rising Interrupt Mask.

TXEMPTY

Bit 9: Transmission Registers Empty Mask.

UNDES

Bit 10: Underrun Error Interrupt Mask.

CSR[[0]]

Chip Select Register

Offset: 0x30, reset: None, access: read-write

1/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYBCT
rw 		DLYBS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCBR
rw 		BITS
rw 		CSAAT
rw 		CSNAAT
rw 		NCPHA
rw 		CPOL
rw
Toggle Fields

CPOL

Bit 0: Clock Polarity.

NCPHA

Bit 1: Clock Phase.

CSNAAT

Bit 2: Chip Select Not Active After Transfer (Ignored if CSAAT = 1).

CSAAT

Bit 3: Chip Select Active After Transfer.

BITS

Bits 4-7: Bits Per Transfer.

Allowed values:
0x0: 8_BIT: 8 bits for transfer
0x1: 9_BIT: 9 bits for transfer
0x2: 10_BIT: 10 bits for transfer
0x3: 11_BIT: 11 bits for transfer
0x4: 12_BIT: 12 bits for transfer
0x5: 13_BIT: 13 bits for transfer
0x6: 14_BIT: 14 bits for transfer
0x7: 15_BIT: 15 bits for transfer
0x8: 16_BIT: 16 bits for transfer

SCBR

Bits 8-15: Serial Clock Baud Rate.

DLYBS

Bits 16-23: Delay Before SPCK.

DLYBCT

Bits 24-31: Delay Between Consecutive Transfers.

CSR[[1]]

Chip Select Register

Offset: 0x34, reset: None, access: read-write

1/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYBCT
rw 		DLYBS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCBR
rw 		BITS
rw 		CSAAT
rw 		CSNAAT
rw 		NCPHA
rw 		CPOL
rw
Toggle Fields

CPOL

Bit 0: Clock Polarity.

NCPHA

Bit 1: Clock Phase.

CSNAAT

Bit 2: Chip Select Not Active After Transfer (Ignored if CSAAT = 1).

CSAAT

Bit 3: Chip Select Active After Transfer.

BITS

Bits 4-7: Bits Per Transfer.

Allowed values:
0x0: 8_BIT: 8 bits for transfer
0x1: 9_BIT: 9 bits for transfer
0x2: 10_BIT: 10 bits for transfer
0x3: 11_BIT: 11 bits for transfer
0x4: 12_BIT: 12 bits for transfer
0x5: 13_BIT: 13 bits for transfer
0x6: 14_BIT: 14 bits for transfer
0x7: 15_BIT: 15 bits for transfer
0x8: 16_BIT: 16 bits for transfer

SCBR

Bits 8-15: Serial Clock Baud Rate.

DLYBS

Bits 16-23: Delay Before SPCK.

DLYBCT

Bits 24-31: Delay Between Consecutive Transfers.

CSR[[2]]

Chip Select Register

Offset: 0x38, reset: None, access: read-write

1/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYBCT
rw 		DLYBS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCBR
rw 		BITS
rw 		CSAAT
rw 		CSNAAT
rw 		NCPHA
rw 		CPOL
rw
Toggle Fields

CPOL

Bit 0: Clock Polarity.

NCPHA

Bit 1: Clock Phase.

CSNAAT

Bit 2: Chip Select Not Active After Transfer (Ignored if CSAAT = 1).

CSAAT

Bit 3: Chip Select Active After Transfer.

BITS

Bits 4-7: Bits Per Transfer.

Allowed values:
0x0: 8_BIT: 8 bits for transfer
0x1: 9_BIT: 9 bits for transfer
0x2: 10_BIT: 10 bits for transfer
0x3: 11_BIT: 11 bits for transfer
0x4: 12_BIT: 12 bits for transfer
0x5: 13_BIT: 13 bits for transfer
0x6: 14_BIT: 14 bits for transfer
0x7: 15_BIT: 15 bits for transfer
0x8: 16_BIT: 16 bits for transfer

SCBR

Bits 8-15: Serial Clock Baud Rate.

DLYBS

Bits 16-23: Delay Before SPCK.

DLYBCT

Bits 24-31: Delay Between Consecutive Transfers.

CSR[[3]]

Chip Select Register

Offset: 0x3c, reset: None, access: read-write

1/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYBCT
rw 		DLYBS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCBR
rw 		BITS
rw 		CSAAT
rw 		CSNAAT
rw 		NCPHA
rw 		CPOL
rw
Toggle Fields

CPOL

Bit 0: Clock Polarity.

NCPHA

Bit 1: Clock Phase.

CSNAAT

Bit 2: Chip Select Not Active After Transfer (Ignored if CSAAT = 1).

CSAAT

Bit 3: Chip Select Active After Transfer.

BITS

Bits 4-7: Bits Per Transfer.

Allowed values:
0x0: 8_BIT: 8 bits for transfer
0x1: 9_BIT: 9 bits for transfer
0x2: 10_BIT: 10 bits for transfer
0x3: 11_BIT: 11 bits for transfer
0x4: 12_BIT: 12 bits for transfer
0x5: 13_BIT: 13 bits for transfer
0x6: 14_BIT: 14 bits for transfer
0x7: 15_BIT: 15 bits for transfer
0x8: 16_BIT: 16 bits for transfer

SCBR

Bits 8-15: Serial Clock Baud Rate.

DLYBS

Bits 16-23: Delay Before SPCK.

DLYBCT

Bits 24-31: Delay Between Consecutive Transfers.

WPMR

Write Protection Control Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect Key.

Allowed values:
0x535049: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

WPSR

Write Protection Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-15: Write Protection Violation Source.

SSC

0x40004000: Synchronous Serial Controller

33/81 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CMR
0x10 RCMR
0x14 RFMR
0x18 TCMR
0x1c TFMR
0x20 RHR
0x24 THR
0x30 RSHR
0x34 TSHR
0x38 RC0R
0x3c RC1R
0x40 SR
0x44 IER
0x48 IDR
0x4c IMR
0xe4 WPMR
0xe8 WPSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w
Toggle Fields

RXEN

Bit 0: Receive Enable.

RXDIS

Bit 1: Receive Disable.

TXEN

Bit 8: Transmit Enable.

TXDIS

Bit 9: Transmit Disable.

SWRST

Bit 15: Software Reset.

CMR

Clock Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
rw
Toggle Fields

DIV

Bits 0-11: Clock Divider.

RCMR

Receive Clock Mode Register

Offset: 0x10, reset: 0x00000000, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIOD
rw 		STTDLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
rw 		START
rw 		CKG
rw 		CKI
rw 		CKO
rw 		CKS
rw
Toggle Fields

CKS

Bits 0-1: Receive Clock Selection.

Allowed values:
0x0: MCK: Divided Clock
0x1: TK: TK Clock signal
0x2: RK: RK pin

CKO

Bits 2-4: Receive Clock Output Mode Selection.

Allowed values:
0x0: NONE: None, RK pin is an input
0x1: CONTINUOUS: Continuous Receive Clock, RK pin is an output
0x2: TRANSFER: Receive Clock only during data transfers, RK pin is an output

CKI

Bit 5: Receive Clock Inversion.

CKG

Bits 6-7: Receive Clock Gating Selection.

Allowed values:
0x0: CONTINUOUS: None
0x1: EN_RF_LOW: Receive Clock enabled only if RF Low
0x2: EN_RF_HIGH: Receive Clock enabled only if RF High

START

Bits 8-11: Receive Start Selection.

Allowed values:
0x0: CONTINUOUS: Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
0x1: TRANSMIT: Transmit start
0x2: RF_LOW: Detection of a low level on RF signal
0x3: RF_HIGH: Detection of a high level on RF signal
0x4: RF_FALLING: Detection of a falling edge on RF signal
0x5: RF_RISING: Detection of a rising edge on RF signal
0x6: RF_LEVEL: Detection of any level change on RF signal
0x7: RF_EDGE: Detection of any edge on RF signal
0x8: CMP_0: Compare 0

STOP

Bit 12: Receive Stop Selection.

STTDLY

Bits 16-23: Receive Start Delay.

PERIOD

Bits 24-31: Receive Period Divider Selection.

RFMR

Receive Frame Mode Register

Offset: 0x14, reset: 0x00000000, access: read-write

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSLEN_EXT
rw 		FSEDGE
rw 		FSOS
rw 		FSLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATNB
rw 		MSBF
rw 		LOOP
rw 		DATLEN
rw
Toggle Fields

DATLEN

Bits 0-4: Data Length.

LOOP

Bit 5: Loop Mode.

MSBF

Bit 7: Most Significant Bit First.

DATNB

Bits 8-11: Data Number per Frame.

FSLEN

Bits 16-19: Receive Frame Sync Length.

FSOS

Bits 20-22: Receive Frame Sync Output Selection.

Allowed values:
0x0: NONE: None, RF pin is an input
0x1: NEGATIVE: Negative Pulse, RF pin is an output
0x2: POSITIVE: Positive Pulse, RF pin is an output
0x3: LOW: Driven Low during data transfer, RF pin is an output
0x4: HIGH: Driven High during data transfer, RF pin is an output
0x5: TOGGLING: Toggling at each start of data transfer, RF pin is an output

FSEDGE

Bit 24: Frame Sync Edge Detection.

Allowed values:
0: POSITIVE: Positive Edge Detection
1: NEGATIVE: Negative Edge Detection

FSLEN_EXT

Bits 28-31: FSLEN Field Extension.

TCMR

Transmit Clock Mode Register

Offset: 0x18, reset: 0x00000000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIOD
rw 		STTDLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START
rw 		CKG
rw 		CKI
rw 		CKO
rw 		CKS
rw
Toggle Fields

CKS

Bits 0-1: Transmit Clock Selection.

Allowed values:
0x0: MCK: Divided Clock
0x1: RK: RK Clock signal
0x2: TK: TK pin

CKO

Bits 2-4: Transmit Clock Output Mode Selection.

Allowed values:
0x0: NONE: None, TK pin is an input
0x1: CONTINUOUS: Continuous Transmit Clock, TK pin is an output
0x2: TRANSFER: Transmit Clock only during data transfers, TK pin is an output

CKI

Bit 5: Transmit Clock Inversion.

CKG

Bits 6-7: Transmit Clock Gating Selection.

Allowed values:
0x0: CONTINUOUS: None
0x1: EN_TF_LOW: Transmit Clock enabled only if TF Low
0x2: EN_TF_HIGH: Transmit Clock enabled only if TF High

START

Bits 8-11: Transmit Start Selection.

Allowed values:
0x0: CONTINUOUS: Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data
0x1: RECEIVE: Receive start
0x2: TF_LOW: Detection of a low level on TF signal
0x3: TF_HIGH: Detection of a high level on TF signal
0x4: TF_FALLING: Detection of a falling edge on TF signal
0x5: TF_RISING: Detection of a rising edge on TF signal
0x6: TF_LEVEL: Detection of any level change on TF signal
0x7: TF_EDGE: Detection of any edge on TF signal

STTDLY

Bits 16-23: Transmit Start Delay.

PERIOD

Bits 24-31: Transmit Period Divider Selection.

TFMR

Transmit Frame Mode Register

Offset: 0x1c, reset: 0x00000000, access: read-write

2/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSLEN_EXT
rw 		FSEDGE
rw 		FSDEN
rw 		FSOS
rw 		FSLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATNB
rw 		MSBF
rw 		DATDEF
rw 		DATLEN
rw
Toggle Fields

DATLEN

Bits 0-4: Data Length.

DATDEF

Bit 5: Data Default Value.

MSBF

Bit 7: Most Significant Bit First.

DATNB

Bits 8-11: Data Number per frame.

FSLEN

Bits 16-19: Transmit Frame Sync Length.

FSOS

Bits 20-22: Transmit Frame Sync Output Selection.

Allowed values:
0x0: NONE: None, RF pin is an input
0x1: NEGATIVE: Negative Pulse, RF pin is an output
0x2: POSITIVE: Positive Pulse, RF pin is an output
0x3: LOW: Driven Low during data transfer
0x4: HIGH: Driven High during data transfer
0x5: TOGGLING: Toggling at each start of data transfer

FSDEN

Bit 23: Frame Sync Data Enable.

FSEDGE

Bit 24: Frame Sync Edge Detection.

Allowed values:
0: POSITIVE: Positive Edge Detection
1: NEGATIVE: Negative Edge Detection

FSLEN_EXT

Bits 28-31: FSLEN Field Extension.

RHR

Receive Holding Register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDAT
r
Toggle Fields

RDAT

Bits 0-31: Receive Data.

THR

Transmit Holding Register

Offset: 0x24, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDAT
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDAT
w
Toggle Fields

TDAT

Bits 0-31: Transmit Data.

RSHR

Receive Sync. Holding Register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSDAT
r
Toggle Fields

RSDAT

Bits 0-15: Receive Synchronization Data.

TSHR

Transmit Sync. Holding Register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSDAT
rw
Toggle Fields

TSDAT

Bits 0-15: Transmit Synchronization Data.

RC0R

Receive Compare 0 Register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP0
rw
Toggle Fields

CP0

Bits 0-15: Receive Compare Data 0.

RC1R

Receive Compare 1 Register

Offset: 0x3c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP1
rw
Toggle Fields

CP1

Bits 0-15: Receive Compare Data 1.

SR

Status Register

Offset: 0x40, reset: 0x000000CC, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXEN
r 		TXEN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYN
r 		TXSYN
r 		CP1
r 		CP0
r 		OVRUN
r 		RXRDY
r 		TXEMPTY
r 		TXRDY
r
Toggle Fields

TXRDY

Bit 0: Transmit Ready.

TXEMPTY

Bit 1: Transmit Empty.

RXRDY

Bit 4: Receive Ready.

OVRUN

Bit 5: Receive Overrun.

CP0

Bit 8: Compare 0.

CP1

Bit 9: Compare 1.

TXSYN

Bit 10: Transmit Sync.

RXSYN

Bit 11: Receive Sync.

TXEN

Bit 16: Transmit Enable.

RXEN

Bit 17: Receive Enable.

IER

Interrupt Enable Register

Offset: 0x44, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYN
w 		TXSYN
w 		CP1
w 		CP0
w 		OVRUN
w 		RXRDY
w 		TXEMPTY
w 		TXRDY
w
Toggle Fields

TXRDY

Bit 0: Transmit Ready Interrupt Enable.

TXEMPTY

Bit 1: Transmit Empty Interrupt Enable.

RXRDY

Bit 4: Receive Ready Interrupt Enable.

OVRUN

Bit 5: Receive Overrun Interrupt Enable.

CP0

Bit 8: Compare 0 Interrupt Enable.

CP1

Bit 9: Compare 1 Interrupt Enable.

TXSYN

Bit 10: Tx Sync Interrupt Enable.

RXSYN

Bit 11: Rx Sync Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x48, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYN
w 		TXSYN
w 		CP1
w 		CP0
w 		OVRUN
w 		RXRDY
w 		TXEMPTY
w 		TXRDY
w
Toggle Fields

TXRDY

Bit 0: Transmit Ready Interrupt Disable.

TXEMPTY

Bit 1: Transmit Empty Interrupt Disable.

RXRDY

Bit 4: Receive Ready Interrupt Disable.

OVRUN

Bit 5: Receive Overrun Interrupt Disable.

CP0

Bit 8: Compare 0 Interrupt Disable.

CP1

Bit 9: Compare 1 Interrupt Disable.

TXSYN

Bit 10: Tx Sync Interrupt Enable.

RXSYN

Bit 11: Rx Sync Interrupt Enable.

IMR

Interrupt Mask Register

Offset: 0x4c, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYN
r 		TXSYN
r 		CP1
r 		CP0
r 		OVRUN
r 		RXRDY
r 		TXEMPTY
r 		TXRDY
r
Toggle Fields

TXRDY

Bit 0: Transmit Ready Interrupt Mask.

TXEMPTY

Bit 1: Transmit Empty Interrupt Mask.

RXRDY

Bit 4: Receive Ready Interrupt Mask.

OVRUN

Bit 5: Receive Overrun Interrupt Mask.

CP0

Bit 8: Compare 0 Interrupt Mask.

CP1

Bit 9: Compare 1 Interrupt Mask.

TXSYN

Bit 10: Tx Sync Interrupt Mask.

RXSYN

Bit 11: Rx Sync Interrupt Mask.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x535343: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

WPSR

Write Protect Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SUPC

0x400e1a10: Supply Controller

74/75 fields covered. Toggle Registers

Show register map

CR

Supply Controller Control Register

Offset: 0x0, reset: None, access: write-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XTALSEL
w 		VROFF
w
Toggle Fields

VROFF

Bit 2: Voltage Regulator Off.

Allowed values:
0: NO_EFFECT: no effect.
1: STOP_VREG: if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator.

XTALSEL

Bit 3: Crystal Oscillator Select.

Allowed values:
0: NO_EFFECT: no effect.
1: CRYSTAL_SEL: if KEY is correct, switches the slow clock on the crystal oscillator output.

KEY

Bits 24-31: Password.

Allowed values:
0xA5: PASSWD: Writing any other value in this field aborts the write operation.

SMMR

Supply Controller Supply Monitor Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMIEN
rw 		SMRSTEN
rw 		SMSMPL
rw 		SMTH
rw
Toggle Fields

SMTH

Bits 0-3: Supply Monitor Threshold.

SMSMPL

Bits 8-10: Supply Monitor Sampling Period.

Allowed values:
0x0: SMD: Supply Monitor disabled
0x1: CSM: Continuous Supply Monitor
0x2: 32SLCK: Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3: 256SLCK: Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4: 2048SLCK: Supply Monitor enabled one SLCK period every 2,048 SLCK periods

SMRSTEN

Bit 12: Supply Monitor Reset Enable.

Allowed values:
0: NOT_ENABLE: the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs.
1: ENABLE: the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.

SMIEN

Bit 13: Supply Monitor Interrupt Enable.

Allowed values:
0: NOT_ENABLE: the SUPC interrupt signal is not affected when a supply monitor detection occurs.
1: ENABLE: the SUPC interrupt signal is asserted when a supply monitor detection occurs.

MR

Supply Controller Mode Register

Offset: 0x8, reset: 0x00005A00, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw 		OSCBYPASS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDIORDY
rw 		BODDIS
rw 		BODRSTEN
rw
Toggle Fields

BODRSTEN

Bit 12: Brownout Detector Reset Enable.

Allowed values:
0: NOT_ENABLE: the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs.
1: ENABLE: the core reset signal, vddcore_nreset is asserted when a brownout detection occurs.

BODDIS

Bit 13: Brownout Detector Disable.

Allowed values:
0: ENABLE: the core brownout detector is enabled.
1: DISABLE: the core brownout detector is disabled.

VDDIORDY

Bit 14: VDDIO Ready.

Allowed values:
0: VDDIO_REMOVED: VDDIO is removed (used before going to backup mode when backup batteries are used)
1: VDDIO_PRESENT: VDDIO is present (used before going to backup mode when backup batteries are used)

OSCBYPASS

Bit 20: Oscillator Bypass.

Allowed values:
0: NO_EFFECT: no effect. Clock selection depends on XTALSEL value.
1: BYPASS: the 32-KHz XTAL oscillator is selected and is put in bypass mode.

KEY

Bits 24-31: Password Key.

Allowed values:
0xA5: PASSWD: Writing any other value in this field aborts the write operation.

WUMR

Supply Controller Wake-up Mode Register

Offset: 0xc, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPDBC
rw 		FWUPDBC
rw 		RTCEN
rw 		RTTEN
rw 		SMEN
rw 		FWUPEN
rw
Toggle Fields

FWUPEN

Bit 0: Force Wake-up Enable.

Allowed values:
0: NOT_ENABLE: the Force Wake-up pin has no wake-up effect.
1: ENABLE: the Force Wake-up pin low forces the wake-up of the core power supply.

SMEN

Bit 1: Supply Monitor Wake-up Enable.

Allowed values:
0: NOT_ENABLE: the supply monitor detection has no wake-up effect.
1: ENABLE: the supply monitor detection forces the wake-up of the core power supply.

RTTEN

Bit 2: Real Time Timer Wake-up Enable.

Allowed values:
0: NOT_ENABLE: the RTT alarm signal has no wake-up effect.
1: ENABLE: the RTT alarm signal forces the wake-up of the core power supply.

RTCEN

Bit 3: Real Time Clock Wake-up Enable.

Allowed values:
0: NOT_ENABLE: the RTC alarm signal has no wake-up effect.
1: ENABLE: the RTC alarm signal forces the wake-up of the core power supply.

FWUPDBC

Bits 8-10: Force Wake-up Debouncer Period.

Allowed values:
0x0: IMMEDIATE: Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x1: 3_SCLK: FWUP shall be low for at least 3 SLCK periods
0x2: 32_SCLK: FWUP shall be low for at least 32 SLCK periods
0x3: 512_SCLK: FWUP shall be low for at least 512 SLCK periods
0x4: 4096_SCLK: FWUP shall be low for at least 4,096 SLCK periods
0x5: 32768_SCLK: FWUP shall be low for at least 32,768 SLCK periods

WKUPDBC

Bits 12-14: Wake-up Inputs Debouncer Period.

Allowed values:
0x0: IMMEDIATE: Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x1: 3_SCLK: WKUPx shall be in its active state for at least 3 SLCK periods
0x2: 32_SCLK: WKUPx shall be in its active state for at least 32 SLCK periods
0x3: 512_SCLK: WKUPx shall be in its active state for at least 512 SLCK periods
0x4: 4096_SCLK: WKUPx shall be in its active state for at least 4,096 SLCK periods
0x5: 32768_SCLK: WKUPx shall be in its active state for at least 32,768 SLCK periods

WUIR

Supply Controller Wake-up Inputs Register

Offset: 0x10, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPT15
rw 		WKUPT14
rw 		WKUPT13
rw 		WKUPT12
rw 		WKUPT11
rw 		WKUPT10
rw 		WKUPT9
rw 		WKUPT8
rw 		WKUPT7
rw 		WKUPT6
rw 		WKUPT5
rw 		WKUPT4
rw 		WKUPT3
rw 		WKUPT2
rw 		WKUPT1
rw 		WKUPT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPEN15
rw 		WKUPEN14
rw 		WKUPEN13
rw 		WKUPEN12
rw 		WKUPEN11
rw 		WKUPEN10
rw 		WKUPEN9
rw 		WKUPEN8
rw 		WKUPEN7
rw 		WKUPEN6
rw 		WKUPEN5
rw 		WKUPEN4
rw 		WKUPEN3
rw 		WKUPEN2
rw 		WKUPEN1
rw 		WKUPEN0
rw
Toggle Fields

WKUPEN0

Bit 0: Wake-up Input Enable 0.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN1

Bit 1: Wake-up Input Enable 1.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN2

Bit 2: Wake-up Input Enable 2.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN3

Bit 3: Wake-up Input Enable 3.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN4

Bit 4: Wake-up Input Enable 4.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN5

Bit 5: Wake-up Input Enable 5.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN6

Bit 6: Wake-up Input Enable 6.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN7

Bit 7: Wake-up Input Enable 7.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN8

Bit 8: Wake-up Input Enable 8.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN9

Bit 9: Wake-up Input Enable 9.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN10

Bit 10: Wake-up Input Enable 10.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN11

Bit 11: Wake-up Input Enable 11.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN12

Bit 12: Wake-up Input Enable 12.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN13

Bit 13: Wake-up Input Enable 13.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN14

Bit 14: Wake-up Input Enable 14.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPEN15

Bit 15: Wake-up Input Enable 15.

Allowed values:
0: DISABLE: the corresponding wake-up input has no wake-up effect.
1: ENABLE: the corresponding wake-up input forces the wake-up of the core power supply.

WKUPT0

Bit 16: Wake-up Input Type 0.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT1

Bit 17: Wake-up Input Type 1.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT2

Bit 18: Wake-up Input Type 2.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT3

Bit 19: Wake-up Input Type 3.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT4

Bit 20: Wake-up Input Type 4.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT5

Bit 21: Wake-up Input Type 5.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT6

Bit 22: Wake-up Input Type 6.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT7

Bit 23: Wake-up Input Type 7.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT8

Bit 24: Wake-up Input Type 8.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT9

Bit 25: Wake-up Input Type 9.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT10

Bit 26: Wake-up Input Type 10.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT11

Bit 27: Wake-up Input Type 11.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT12

Bit 28: Wake-up Input Type 12.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT13

Bit 29: Wake-up Input Type 13.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT14

Bit 30: Wake-up Input Type 14.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

WKUPT15

Bit 31: Wake-up Input Type 15.

Allowed values:
0: HIGH_TO_LOW: a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1: LOW_TO_HIGH: a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply.

SR

Supply Controller Status Register

Offset: 0x14, reset: 0x00000000, access: read-only

25/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIS15
r 		WKUPIS14
r 		WKUPIS13
r 		WKUPIS12
r 		WKUPIS11
r 		WKUPIS10
r 		WKUPIS9
r 		WKUPIS8
r 		WKUPIS7
r 		WKUPIS6
r 		WKUPIS5
r 		WKUPIS4
r 		WKUPIS3
r 		WKUPIS2
r 		WKUPIS1
r 		WKUPIS0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FWUPIS
r 		OSCSEL
r 		SMOS
r 		SMS
r 		SMRSTS
r 		BODRSTS
r 		SMWS
r 		WKUPS
r 		FWUPS
r
Toggle Fields

FWUPS

Bit 0: FWUP Wake-up Status.

Allowed values:
0: NO: no wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR.
1: PRESENT: at least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR.

WKUPS

Bit 1: WKUP Wake-up Status.

Allowed values:
0: NO: no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1: PRESENT: at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.

SMWS

Bit 2: Supply Monitor Detection Wake-up Status.

Allowed values:
0: NO: no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1: PRESENT: at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.

BODRSTS

Bit 3: Brownout Detector Reset Status.

Allowed values:
0: NO: no core brownout rising edge event has been detected since the last read of the SUPC_SR.
1: PRESENT: at least one brownout output rising edge event has been detected since the last read of the SUPC_SR.

SMRSTS

Bit 4: Supply Monitor Reset Status.

Allowed values:
0: NO: no supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1: PRESENT: at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.

SMS

Bit 5: Supply Monitor Status.

Allowed values:
0: NO: no supply monitor detection since the last read of SUPC_SR.
1: PRESENT: at least one supply monitor detection since the last read of SUPC_SR.

SMOS

Bit 6: Supply Monitor Output Status.

Allowed values:
0: HIGH: the supply monitor detected VDDUTMI higher than its threshold at its last measurement.
1: LOW: the supply monitor detected VDDUTMI lower than its threshold at its last measurement.

OSCSEL

Bit 7: 32-kHz Oscillator Selection Status.

Allowed values:
0: RC: the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator.
1: CRYST: the slow clock, SLCK is generated by the 32-kHz crystal oscillator.

FWUPIS

Bit 12: FWUP Input Status.

Allowed values:
0: LOW: FWUP input is tied low.
1: HIGH: FWUP input is tied high.

WKUPIS0

Bit 16: WKUP Input Status 0.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS1

Bit 17: WKUP Input Status 1.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS2

Bit 18: WKUP Input Status 2.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS3

Bit 19: WKUP Input Status 3.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS4

Bit 20: WKUP Input Status 4.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS5

Bit 21: WKUP Input Status 5.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS6

Bit 22: WKUP Input Status 6.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS7

Bit 23: WKUP Input Status 7.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS8

Bit 24: WKUP Input Status 8.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS9

Bit 25: WKUP Input Status 9.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS10

Bit 26: WKUP Input Status 10.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS11

Bit 27: WKUP Input Status 11.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS12

Bit 28: WKUP Input Status 12.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS13

Bit 29: WKUP Input Status 13.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS14

Bit 30: WKUP Input Status 14.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

WKUPIS15

Bit 31: WKUP Input Status 15.

Allowed values:
0: DIS: the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1: EN: the corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

TC0

0x40080000: Timer Counter 0

125/252 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR0
0x4 CMR0
0x4 CMR0_WAVE_EQ_1
0x8 SMMR0
0x10 CV0
0x14 RA0
0x18 RB0
0x1c RC0
0x20 SR0
0x24 IER0
0x28 IDR0
0x2c IMR0
0x40 CCR1
0x44 CMR1
0x44 CMR1_WAVE_EQ_1
0x48 SMMR1
0x50 CV1
0x54 RA1
0x58 RB1
0x5c RC1
0x60 SR1
0x64 IER1
0x68 IDR1
0x6c IMR1
0x80 CCR2
0x84 CMR2
0x84 CMR2_WAVE_EQ_1
0x88 SMMR2
0x90 CV2
0x94 RA2
0x98 RB2
0x9c RC2
0xa0 SR2
0xa4 IER2
0xa8 IDR2
0xac IMR2
0xc0 BCR
0xc4 BMR
0xc8 QIER
0xcc QIDR
0xd0 QIMR
0xd4 QISR
0xd8 FMR
0xe4 WPMR

CCR0

Channel Control Register (channel = 0)

Offset: 0x0, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR0

Channel Mode Register (channel = 0)

Offset: 0x4, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR0_WAVE_EQ_1

Channel Mode Register (channel = 0)

Offset: 0x4, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR0

Stepper Motor Mode Register (channel = 0)

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV0

Counter Value (channel = 0)

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA0

Register A (channel = 0)

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB0

Register B (channel = 0)

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC0

Register C (channel = 0)

Offset: 0x1c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR0

Status Register (channel = 0)

Offset: 0x20, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER0

Interrupt Enable Register (channel = 0)

Offset: 0x24, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR0

Interrupt Disable Register (channel = 0)

Offset: 0x28, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR0

Interrupt Mask Register (channel = 0)

Offset: 0x2c, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

CCR1

Channel Control Register (channel = 1)

Offset: 0x40, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR1

Channel Mode Register (channel = 1)

Offset: 0x44, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR1_WAVE_EQ_1

Channel Mode Register (channel = 1)

Offset: 0x44, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR1

Stepper Motor Mode Register (channel = 1)

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV1

Counter Value (channel = 1)

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA1

Register A (channel = 1)

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB1

Register B (channel = 1)

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC1

Register C (channel = 1)

Offset: 0x5c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR1

Status Register (channel = 1)

Offset: 0x60, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER1

Interrupt Enable Register (channel = 1)

Offset: 0x64, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR1

Interrupt Disable Register (channel = 1)

Offset: 0x68, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR1

Interrupt Mask Register (channel = 1)

Offset: 0x6c, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

CCR2

Channel Control Register (channel = 2)

Offset: 0x80, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR2

Channel Mode Register (channel = 2)

Offset: 0x84, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR2_WAVE_EQ_1

Channel Mode Register (channel = 2)

Offset: 0x84, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR2

Stepper Motor Mode Register (channel = 2)

Offset: 0x88, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV2

Counter Value (channel = 2)

Offset: 0x90, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA2

Register A (channel = 2)

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB2

Register B (channel = 2)

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC2

Register C (channel = 2)

Offset: 0x9c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR2

Status Register (channel = 2)

Offset: 0xa0, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER2

Interrupt Enable Register (channel = 2)

Offset: 0xa4, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR2

Interrupt Disable Register (channel = 2)

Offset: 0xa8, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR2

Interrupt Mask Register (channel = 2)

Offset: 0xac, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

BCR

Block Control Register

Offset: 0xc0, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC
w
Toggle Fields

SYNC

Bit 0: Synchro Command.

BMR

Block Mode Register

Offset: 0xc4, reset: 0x00000000, access: read-write

3/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAXFILT
rw 		FILTER
rw 		IDXPHB
rw 		SWAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INVIDX
rw 		INVB
rw 		INVA
rw 		EDGPHA
rw 		QDTRANS
rw 		SPEEDEN
rw 		POSEN
rw 		QDEN
rw 		TC2XC2S
rw 		TC1XC1S
rw 		TC0XC0S
rw
Toggle Fields

TC0XC0S

Bits 0-1: External Clock Signal 0 Selection.

Allowed values:
0x0: TCLK0: Signal connected to XC0: TCLK0
0x2: TIOA1: Signal connected to XC0: TIOA1
0x3: TIOA2: Signal connected to XC0: TIOA2

TC1XC1S

Bits 2-3: External Clock Signal 1 Selection.

Allowed values:
0x0: TCLK1: Signal connected to XC1: TCLK1
0x2: TIOA0: Signal connected to XC1: TIOA0
0x3: TIOA2: Signal connected to XC1: TIOA2

TC2XC2S

Bits 4-5: External Clock Signal 2 Selection.

Allowed values:
0x0: TCLK2: Signal connected to XC2: TCLK2
0x2: TIOA1: Signal connected to XC2: TIOA1
0x3: TIOA2: Signal connected to XC2: TIOA2

QDEN

Bit 8: Quadrature Decoder ENabled.

POSEN

Bit 9: POSition ENabled.

SPEEDEN

Bit 10: SPEED ENabled.

QDTRANS

Bit 11: Quadrature Decoding TRANSparent.

EDGPHA

Bit 12: EDGe on PHA count mode.

INVA

Bit 13: INVerted phA.

INVB

Bit 14: INVerted phB.

INVIDX

Bit 15: INVerted InDeX.

SWAP

Bit 16: SWAP PHA and PHB.

IDXPHB

Bit 17: InDeX pin is PHB pin.

FILTER

Bit 19: None.

MAXFILT

Bits 20-25: MAXimum FILTer.

QIER

QDEC Interrupt Enable Register

Offset: 0xc8, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
w 		DIRCHG
w 		IDX
w
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QIDR

QDEC Interrupt Disable Register

Offset: 0xcc, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
w 		DIRCHG
w 		IDX
w
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QIMR

QDEC Interrupt Mask Register

Offset: 0xd0, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
r 		DIRCHG
r 		IDX
r
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QISR

QDEC Interrupt Status Register

Offset: 0xd4, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIR
r 		QERR
r 		DIRCHG
r 		IDX
r
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

DIR

Bit 8: DIRection.

FMR

Fault Mode Register

Offset: 0xd8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENCF1
rw 		ENCF0
rw
Toggle Fields

ENCF0

Bit 0: ENable Compare Fault Channel 0.

ENCF1

Bit 1: ENable Compare Fault Channel 1.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x54494D: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

TC1

0x40084000: Timer Counter 1

125/252 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR0
0x4 CMR0
0x4 CMR0_WAVE_EQ_1
0x8 SMMR0
0x10 CV0
0x14 RA0
0x18 RB0
0x1c RC0
0x20 SR0
0x24 IER0
0x28 IDR0
0x2c IMR0
0x40 CCR1
0x44 CMR1
0x44 CMR1_WAVE_EQ_1
0x48 SMMR1
0x50 CV1
0x54 RA1
0x58 RB1
0x5c RC1
0x60 SR1
0x64 IER1
0x68 IDR1
0x6c IMR1
0x80 CCR2
0x84 CMR2
0x84 CMR2_WAVE_EQ_1
0x88 SMMR2
0x90 CV2
0x94 RA2
0x98 RB2
0x9c RC2
0xa0 SR2
0xa4 IER2
0xa8 IDR2
0xac IMR2
0xc0 BCR
0xc4 BMR
0xc8 QIER
0xcc QIDR
0xd0 QIMR
0xd4 QISR
0xd8 FMR
0xe4 WPMR

CCR0

Channel Control Register (channel = 0)

Offset: 0x0, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR0

Channel Mode Register (channel = 0)

Offset: 0x4, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR0_WAVE_EQ_1

Channel Mode Register (channel = 0)

Offset: 0x4, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR0

Stepper Motor Mode Register (channel = 0)

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV0

Counter Value (channel = 0)

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA0

Register A (channel = 0)

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB0

Register B (channel = 0)

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC0

Register C (channel = 0)

Offset: 0x1c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR0

Status Register (channel = 0)

Offset: 0x20, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER0

Interrupt Enable Register (channel = 0)

Offset: 0x24, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR0

Interrupt Disable Register (channel = 0)

Offset: 0x28, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR0

Interrupt Mask Register (channel = 0)

Offset: 0x2c, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

CCR1

Channel Control Register (channel = 1)

Offset: 0x40, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR1

Channel Mode Register (channel = 1)

Offset: 0x44, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR1_WAVE_EQ_1

Channel Mode Register (channel = 1)

Offset: 0x44, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR1

Stepper Motor Mode Register (channel = 1)

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV1

Counter Value (channel = 1)

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA1

Register A (channel = 1)

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB1

Register B (channel = 1)

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC1

Register C (channel = 1)

Offset: 0x5c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR1

Status Register (channel = 1)

Offset: 0x60, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER1

Interrupt Enable Register (channel = 1)

Offset: 0x64, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR1

Interrupt Disable Register (channel = 1)

Offset: 0x68, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR1

Interrupt Mask Register (channel = 1)

Offset: 0x6c, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

CCR2

Channel Control Register (channel = 2)

Offset: 0x80, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR2

Channel Mode Register (channel = 2)

Offset: 0x84, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR2_WAVE_EQ_1

Channel Mode Register (channel = 2)

Offset: 0x84, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR2

Stepper Motor Mode Register (channel = 2)

Offset: 0x88, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV2

Counter Value (channel = 2)

Offset: 0x90, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA2

Register A (channel = 2)

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB2

Register B (channel = 2)

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC2

Register C (channel = 2)

Offset: 0x9c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR2

Status Register (channel = 2)

Offset: 0xa0, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER2

Interrupt Enable Register (channel = 2)

Offset: 0xa4, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR2

Interrupt Disable Register (channel = 2)

Offset: 0xa8, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR2

Interrupt Mask Register (channel = 2)

Offset: 0xac, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

BCR

Block Control Register

Offset: 0xc0, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC
w
Toggle Fields

SYNC

Bit 0: Synchro Command.

BMR

Block Mode Register

Offset: 0xc4, reset: 0x00000000, access: read-write

3/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAXFILT
rw 		FILTER
rw 		IDXPHB
rw 		SWAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INVIDX
rw 		INVB
rw 		INVA
rw 		EDGPHA
rw 		QDTRANS
rw 		SPEEDEN
rw 		POSEN
rw 		QDEN
rw 		TC2XC2S
rw 		TC1XC1S
rw 		TC0XC0S
rw
Toggle Fields

TC0XC0S

Bits 0-1: External Clock Signal 0 Selection.

Allowed values:
0x0: TCLK0: Signal connected to XC0: TCLK0
0x2: TIOA1: Signal connected to XC0: TIOA1
0x3: TIOA2: Signal connected to XC0: TIOA2

TC1XC1S

Bits 2-3: External Clock Signal 1 Selection.

Allowed values:
0x0: TCLK1: Signal connected to XC1: TCLK1
0x2: TIOA0: Signal connected to XC1: TIOA0
0x3: TIOA2: Signal connected to XC1: TIOA2

TC2XC2S

Bits 4-5: External Clock Signal 2 Selection.

Allowed values:
0x0: TCLK2: Signal connected to XC2: TCLK2
0x2: TIOA1: Signal connected to XC2: TIOA1
0x3: TIOA2: Signal connected to XC2: TIOA2

QDEN

Bit 8: Quadrature Decoder ENabled.

POSEN

Bit 9: POSition ENabled.

SPEEDEN

Bit 10: SPEED ENabled.

QDTRANS

Bit 11: Quadrature Decoding TRANSparent.

EDGPHA

Bit 12: EDGe on PHA count mode.

INVA

Bit 13: INVerted phA.

INVB

Bit 14: INVerted phB.

INVIDX

Bit 15: INVerted InDeX.

SWAP

Bit 16: SWAP PHA and PHB.

IDXPHB

Bit 17: InDeX pin is PHB pin.

FILTER

Bit 19: None.

MAXFILT

Bits 20-25: MAXimum FILTer.

QIER

QDEC Interrupt Enable Register

Offset: 0xc8, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
w 		DIRCHG
w 		IDX
w
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QIDR

QDEC Interrupt Disable Register

Offset: 0xcc, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
w 		DIRCHG
w 		IDX
w
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QIMR

QDEC Interrupt Mask Register

Offset: 0xd0, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
r 		DIRCHG
r 		IDX
r
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QISR

QDEC Interrupt Status Register

Offset: 0xd4, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIR
r 		QERR
r 		DIRCHG
r 		IDX
r
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

DIR

Bit 8: DIRection.

FMR

Fault Mode Register

Offset: 0xd8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENCF1
rw 		ENCF0
rw
Toggle Fields

ENCF0

Bit 0: ENable Compare Fault Channel 0.

ENCF1

Bit 1: ENable Compare Fault Channel 1.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x54494D: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

TC2

0x40088000: Timer Counter 2

125/252 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR0
0x4 CMR0
0x4 CMR0_WAVE_EQ_1
0x8 SMMR0
0x10 CV0
0x14 RA0
0x18 RB0
0x1c RC0
0x20 SR0
0x24 IER0
0x28 IDR0
0x2c IMR0
0x40 CCR1
0x44 CMR1
0x44 CMR1_WAVE_EQ_1
0x48 SMMR1
0x50 CV1
0x54 RA1
0x58 RB1
0x5c RC1
0x60 SR1
0x64 IER1
0x68 IDR1
0x6c IMR1
0x80 CCR2
0x84 CMR2
0x84 CMR2_WAVE_EQ_1
0x88 SMMR2
0x90 CV2
0x94 RA2
0x98 RB2
0x9c RC2
0xa0 SR2
0xa4 IER2
0xa8 IDR2
0xac IMR2
0xc0 BCR
0xc4 BMR
0xc8 QIER
0xcc QIDR
0xd0 QIMR
0xd4 QISR
0xd8 FMR
0xe4 WPMR

CCR0

Channel Control Register (channel = 0)

Offset: 0x0, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR0

Channel Mode Register (channel = 0)

Offset: 0x4, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR0_WAVE_EQ_1

Channel Mode Register (channel = 0)

Offset: 0x4, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR0

Stepper Motor Mode Register (channel = 0)

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV0

Counter Value (channel = 0)

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA0

Register A (channel = 0)

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB0

Register B (channel = 0)

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC0

Register C (channel = 0)

Offset: 0x1c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR0

Status Register (channel = 0)

Offset: 0x20, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER0

Interrupt Enable Register (channel = 0)

Offset: 0x24, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR0

Interrupt Disable Register (channel = 0)

Offset: 0x28, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR0

Interrupt Mask Register (channel = 0)

Offset: 0x2c, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

CCR1

Channel Control Register (channel = 1)

Offset: 0x40, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR1

Channel Mode Register (channel = 1)

Offset: 0x44, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR1_WAVE_EQ_1

Channel Mode Register (channel = 1)

Offset: 0x44, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR1

Stepper Motor Mode Register (channel = 1)

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV1

Counter Value (channel = 1)

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA1

Register A (channel = 1)

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB1

Register B (channel = 1)

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC1

Register C (channel = 1)

Offset: 0x5c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR1

Status Register (channel = 1)

Offset: 0x60, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER1

Interrupt Enable Register (channel = 1)

Offset: 0x64, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR1

Interrupt Disable Register (channel = 1)

Offset: 0x68, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR1

Interrupt Mask Register (channel = 1)

Offset: 0x6c, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

CCR2

Channel Control Register (channel = 2)

Offset: 0x80, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRG
w 		CLKDIS
w 		CLKEN
w
Toggle Fields

CLKEN

Bit 0: Counter Clock Enable Command.

CLKDIS

Bit 1: Counter Clock Disable Command.

SWTRG

Bit 2: Software Trigger Command.

CMR2

Channel Mode Register (channel = 2)

Offset: 0x84, reset: 0x00000000, access: read-write

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRB
rw 		LDRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		CPCTRG
rw 		ABETRG
rw 		ETRGEDG
rw 		LDBDIS
rw 		LDBSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

LDBSTOP

Bit 6: Counter Clock Stopped with RB Loading.

LDBDIS

Bit 7: Counter Clock Disable with RB Loading.

ETRGEDG

Bits 8-9: External Trigger Edge Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

ABETRG

Bit 10: TIOA or TIOB External Trigger Selection.

CPCTRG

Bit 14: RC Compare Trigger Enable.

WAVE

Bit 15: Waveform Mode.

LDRA

Bits 16-17: RA Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

LDRB

Bits 18-19: RB Loading Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge of TIOA
0x2: FALLING: Falling edge of TIOA
0x3: EDGE: Each edge of TIOA

CMR2_WAVE_EQ_1

Channel Mode Register (channel = 2)

Offset: 0x84, reset: 0x00000000, access: read-write

13/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSWTRG
rw 		BEEVT
rw 		BCPC
rw 		BCPB
rw 		ASWTRG
rw 		AEEVT
rw 		ACPC
rw 		ACPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAVE
rw 		WAVSEL
rw 		ENETRG
rw 		EEVT
rw 		EEVTEDG
rw 		CPCDIS
rw 		CPCSTOP
rw 		BURST
rw 		CLKI
rw 		TCCLKS
rw
Toggle Fields

TCCLKS

Bits 0-2: Clock Selection.

Allowed values:
0x0: TIMER_CLOCK1: Clock selected: TCLK1
0x1: TIMER_CLOCK2: Clock selected: TCLK2
0x2: TIMER_CLOCK3: Clock selected: TCLK3
0x3: TIMER_CLOCK4: Clock selected: TCLK4
0x4: TIMER_CLOCK5: Clock selected: TCLK5
0x5: XC0: Clock selected: XC0
0x6: XC1: Clock selected: XC1
0x7: XC2: Clock selected: XC2

CLKI

Bit 3: Clock Invert.

BURST

Bits 4-5: Burst Signal Selection.

Allowed values:
0x0: NONE: The clock is not gated by an external signal.
0x1: XC0: XC0 is ANDed with the selected clock.
0x2: XC1: XC1 is ANDed with the selected clock.
0x3: XC2: XC2 is ANDed with the selected clock.

CPCSTOP

Bit 6: Counter Clock Stopped with RC Compare.

CPCDIS

Bit 7: Counter Clock Disable with RC Compare.

EEVTEDG

Bits 8-9: External Event Edge Selection.

Allowed values:
0x0: NONE: None
0x1: RISING: Rising edge
0x2: FALLING: Falling edge
0x3: EDGE: Each edge

EEVT

Bits 10-11: External Event Selection.

Allowed values:
0x0: TIOB: TIOB
0x1: XC0: XC0
0x2: XC1: XC1
0x3: XC2: XC2

ENETRG

Bit 12: External Event Trigger Enable.

WAVSEL

Bits 13-14: Waveform Selection.

Allowed values:
0x0: UP: UP mode without automatic trigger on RC Compare
0x1: UPDOWN: UPDOWN mode without automatic trigger on RC Compare
0x2: UP_RC: UP mode with automatic trigger on RC Compare
0x3: UPDOWN_RC: UPDOWN mode with automatic trigger on RC Compare

WAVE

Bit 15: Waveform Mode.

ACPA

Bits 16-17: RA Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ACPC

Bits 18-19: RC Compare Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

AEEVT

Bits 20-21: External Event Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

ASWTRG

Bits 22-23: Software Trigger Effect on TIOA.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPB

Bits 24-25: RB Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BCPC

Bits 26-27: RC Compare Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BEEVT

Bits 28-29: External Event Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

BSWTRG

Bits 30-31: Software Trigger Effect on TIOB.

Allowed values:
0x0: NONE: None
0x1: SET: Set
0x2: CLEAR: Clear
0x3: TOGGLE: Toggle

SMMR2

Stepper Motor Mode Register (channel = 2)

Offset: 0x88, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
rw 		GCEN
rw
Toggle Fields

GCEN

Bit 0: Gray Count Enable.

DOWN

Bit 1: DOWN Count.

CV2

Counter Value (channel = 2)

Offset: 0x90, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CV
r
Toggle Fields

CV

Bits 0-31: Counter Value.

RA2

Register A (channel = 2)

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA
rw
Toggle Fields

RA

Bits 0-31: Register A.

RB2

Register B (channel = 2)

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RB
rw
Toggle Fields

RB

Bits 0-31: Register B.

RC2

Register C (channel = 2)

Offset: 0x9c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
rw
Toggle Fields

RC

Bits 0-31: Register C.

SR2

Status Register (channel = 2)

Offset: 0xa0, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTIOB
r 		MTIOA
r 		CLKSTA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow Status.

LOVRS

Bit 1: Load Overrun Status.

CPAS

Bit 2: RA Compare Status.

CPBS

Bit 3: RB Compare Status.

CPCS

Bit 4: RC Compare Status.

LDRAS

Bit 5: RA Loading Status.

LDRBS

Bit 6: RB Loading Status.

ETRGS

Bit 7: External Trigger Status.

CLKSTA

Bit 16: Clock Enabling Status.

MTIOA

Bit 17: TIOA Mirror.

MTIOB

Bit 18: TIOB Mirror.

IER2

Interrupt Enable Register (channel = 2)

Offset: 0xa4, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IDR2

Interrupt Disable Register (channel = 2)

Offset: 0xa8, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
w 		LDRBS
w 		LDRAS
w 		CPCS
w 		CPBS
w 		CPAS
w 		LOVRS
w 		COVFS
w
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

IMR2

Interrupt Mask Register (channel = 2)

Offset: 0xac, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRGS
r 		LDRBS
r 		LDRAS
r 		CPCS
r 		CPBS
r 		CPAS
r 		LOVRS
r 		COVFS
r
Toggle Fields

COVFS

Bit 0: Counter Overflow.

LOVRS

Bit 1: Load Overrun.

CPAS

Bit 2: RA Compare.

CPBS

Bit 3: RB Compare.

CPCS

Bit 4: RC Compare.

LDRAS

Bit 5: RA Loading.

LDRBS

Bit 6: RB Loading.

ETRGS

Bit 7: External Trigger.

BCR

Block Control Register

Offset: 0xc0, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC
w
Toggle Fields

SYNC

Bit 0: Synchro Command.

BMR

Block Mode Register

Offset: 0xc4, reset: 0x00000000, access: read-write

3/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAXFILT
rw 		FILTER
rw 		IDXPHB
rw 		SWAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INVIDX
rw 		INVB
rw 		INVA
rw 		EDGPHA
rw 		QDTRANS
rw 		SPEEDEN
rw 		POSEN
rw 		QDEN
rw 		TC2XC2S
rw 		TC1XC1S
rw 		TC0XC0S
rw
Toggle Fields

TC0XC0S

Bits 0-1: External Clock Signal 0 Selection.

Allowed values:
0x0: TCLK0: Signal connected to XC0: TCLK0
0x2: TIOA1: Signal connected to XC0: TIOA1
0x3: TIOA2: Signal connected to XC0: TIOA2

TC1XC1S

Bits 2-3: External Clock Signal 1 Selection.

Allowed values:
0x0: TCLK1: Signal connected to XC1: TCLK1
0x2: TIOA0: Signal connected to XC1: TIOA0
0x3: TIOA2: Signal connected to XC1: TIOA2

TC2XC2S

Bits 4-5: External Clock Signal 2 Selection.

Allowed values:
0x0: TCLK2: Signal connected to XC2: TCLK2
0x2: TIOA1: Signal connected to XC2: TIOA1
0x3: TIOA2: Signal connected to XC2: TIOA2

QDEN

Bit 8: Quadrature Decoder ENabled.

POSEN

Bit 9: POSition ENabled.

SPEEDEN

Bit 10: SPEED ENabled.

QDTRANS

Bit 11: Quadrature Decoding TRANSparent.

EDGPHA

Bit 12: EDGe on PHA count mode.

INVA

Bit 13: INVerted phA.

INVB

Bit 14: INVerted phB.

INVIDX

Bit 15: INVerted InDeX.

SWAP

Bit 16: SWAP PHA and PHB.

IDXPHB

Bit 17: InDeX pin is PHB pin.

FILTER

Bit 19: None.

MAXFILT

Bits 20-25: MAXimum FILTer.

QIER

QDEC Interrupt Enable Register

Offset: 0xc8, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
w 		DIRCHG
w 		IDX
w
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QIDR

QDEC Interrupt Disable Register

Offset: 0xcc, reset: None, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
w 		DIRCHG
w 		IDX
w
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QIMR

QDEC Interrupt Mask Register

Offset: 0xd0, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QERR
r 		DIRCHG
r 		IDX
r
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

QISR

QDEC Interrupt Status Register

Offset: 0xd4, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIR
r 		QERR
r 		DIRCHG
r 		IDX
r
Toggle Fields

IDX

Bit 0: InDeX.

DIRCHG

Bit 1: DIRection CHanGe.

QERR

Bit 2: Quadrature ERRor.

DIR

Bit 8: DIRection.

FMR

Fault Mode Register

Offset: 0xd8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENCF1
rw 		ENCF0
rw
Toggle Fields

ENCF0

Bit 0: ENable Compare Fault Channel 0.

ENCF1

Bit 1: ENable Compare Fault Channel 1.

WPMR

Write Protect Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protect Enable.

WPKEY

Bits 8-31: Write Protect KEY.

Allowed values:
0x54494D: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

TRNG

0x400bc000: True Random Number Generator

3/7 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 IER
0x14 IDR
0x18 IMR
0x1c ISR
0x50 ODATA

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w 		ENABLE
w
Toggle Fields

ENABLE

Bit 0: Enables the TRNG to provide random values.

KEY

Bits 8-31: Security Key.

IER

Interrupt Enable Register

Offset: 0x10, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATRDY
w
Toggle Fields

DATRDY

Bit 0: Data Ready Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x14, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATRDY
w
Toggle Fields

DATRDY

Bit 0: Data Ready Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATRDY
r
Toggle Fields

DATRDY

Bit 0: Data Ready Interrupt Mask.

ISR

Interrupt Status Register

Offset: 0x1c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATRDY
r
Toggle Fields

DATRDY

Bit 0: Data Ready.

ODATA

Output Data Register

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ODATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODATA
r
Toggle Fields

ODATA

Bits 0-31: Output Data.

TWI0

0x4008c000: Two-wire Interface 0

33/89 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MMR
0x8 SMR
0xc IADR
0x10 CWGR
0x20 SR
0x24 IER
0x28 IDR
0x2c IMR
0x30 RHR
0x34 THR
0x100 RPR
0x104 RCR
0x108 TPR
0x10c TCR
0x110 RNPR
0x114 RNCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
w 		QUICK
w 		SVDIS
w 		SVEN
w 		MSDIS
w 		MSEN
w 		STOP
w 		START
w
Toggle Fields

START

Bit 0: Send a START Condition.

STOP

Bit 1: Send a STOP Condition.

MSEN

Bit 2: TWI Master Mode Enabled.

MSDIS

Bit 3: TWI Master Mode Disabled.

SVEN

Bit 4: TWI Slave Mode Enabled.

SVDIS

Bit 5: TWI Slave Mode Disabled.

QUICK

Bit 6: SMBUS Quick Command.

SWRST

Bit 7: Software Reset.

MMR

Master Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MREAD
rw 		IADRSZ
rw
Toggle Fields

IADRSZ

Bits 8-9: Internal Device Address Size.

Allowed values:
0x0: NONE: No internal device address
0x1: 1_BYTE: One-byte internal device address
0x2: 2_BYTE: Two-byte internal device address
0x3: 3_BYTE: Three-byte internal device address

MREAD

Bit 12: Master Read Direction.

DADR

Bits 16-22: Device Address.

SMR

Slave Mode Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SADR

Bits 16-22: Slave Address.

IADR

Internal Address Register

Offset: 0xc, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IADR
rw
Toggle Fields

IADR

Bits 0-23: Internal Address.

CWGR

Clock Waveform Generator Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHDIV
rw 		CLDIV
rw
Toggle Fields

CLDIV

Bits 0-7: Clock Low Divider.

CHDIV

Bits 8-15: Clock High Divider.

CKDIV

Bits 16-18: Clock Divider.

SR

Status Register

Offset: 0x20, reset: 0x0000F009, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
r 		RXBUFF
r 		ENDTX
r 		ENDRX
r 		EOSACC
r 		SCLWS
r 		ARBLST
r 		NACK
r 		OVRE
r 		GACC
r 		SVACC
r 		SVREAD
r 		TXRDY
r 		RXRDY
r 		TXCOMP
r
Toggle Fields

TXCOMP

Bit 0: Transmission Completed (automatically set / reset).

RXRDY

Bit 1: Receive Holding Register Ready (automatically set / reset).

TXRDY

Bit 2: Transmit Holding Register Ready (automatically set / reset).

SVREAD

Bit 3: Slave Read (automatically set / reset).

SVACC

Bit 4: Slave Access (automatically set / reset).

GACC

Bit 5: General Call Access (clear on read).

OVRE

Bit 6: Overrun Error (clear on read).

NACK

Bit 8: Not Acknowledged (clear on read).

ARBLST

Bit 9: Arbitration Lost (clear on read).

SCLWS

Bit 10: Clock Wait State (automatically set / reset).

EOSACC

Bit 11: End Of Slave Access (clear on read).

ENDRX

Bit 12: End of RX buffer.

ENDTX

Bit 13: End of TX buffer.

RXBUFF

Bit 14: RX Buffer Full.

TXBUFE

Bit 15: TX Buffer Empty.

IER

Interrupt Enable Register

Offset: 0x24, reset: None, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
w 		RXBUFF
w 		ENDTX
w 		ENDRX
w 		EOSACC
w 		SCL_WS
w 		ARBLST
w 		NACK
w 		OVRE
w 		GACC
w 		SVACC
w 		TXRDY
w 		RXRDY
w 		TXCOMP
w
Toggle Fields

TXCOMP

Bit 0: Transmission Completed Interrupt Enable.

RXRDY

Bit 1: Receive Holding Register Ready Interrupt Enable.

TXRDY

Bit 2: Transmit Holding Register Ready Interrupt Enable.

SVACC

Bit 4: Slave Access Interrupt Enable.

GACC

Bit 5: General Call Access Interrupt Enable.

OVRE

Bit 6: Overrun Error Interrupt Enable.

NACK

Bit 8: Not Acknowledge Interrupt Enable.

ARBLST

Bit 9: Arbitration Lost Interrupt Enable.

SCL_WS

Bit 10: Clock Wait State Interrupt Enable.

EOSACC

Bit 11: End Of Slave Access Interrupt Enable.

ENDRX

Bit 12: End of Receive Buffer Interrupt Enable.

ENDTX

Bit 13: End of Transmit Buffer Interrupt Enable.

RXBUFF

Bit 14: Receive Buffer Full Interrupt Enable.

TXBUFE

Bit 15: Transmit Buffer Empty Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x28, reset: None, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
w 		RXBUFF
w 		ENDTX
w 		ENDRX
w 		EOSACC
w 		SCL_WS
w 		ARBLST
w 		NACK
w 		OVRE
w 		GACC
w 		SVACC
w 		TXRDY
w 		RXRDY
w 		TXCOMP
w
Toggle Fields

TXCOMP

Bit 0: Transmission Completed Interrupt Disable.

RXRDY

Bit 1: Receive Holding Register Ready Interrupt Disable.

TXRDY

Bit 2: Transmit Holding Register Ready Interrupt Disable.

SVACC

Bit 4: Slave Access Interrupt Disable.

GACC

Bit 5: General Call Access Interrupt Disable.

OVRE

Bit 6: Overrun Error Interrupt Disable.

NACK

Bit 8: Not Acknowledge Interrupt Disable.

ARBLST

Bit 9: Arbitration Lost Interrupt Disable.

SCL_WS

Bit 10: Clock Wait State Interrupt Disable.

EOSACC

Bit 11: End Of Slave Access Interrupt Disable.

ENDRX

Bit 12: End of Receive Buffer Interrupt Disable.

ENDTX

Bit 13: End of Transmit Buffer Interrupt Disable.

RXBUFF

Bit 14: Receive Buffer Full Interrupt Disable.

TXBUFE

Bit 15: Transmit Buffer Empty Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x2c, reset: 0x00000000, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
r 		RXBUFF
r 		ENDTX
r 		ENDRX
r 		EOSACC
r 		SCL_WS
r 		ARBLST
r 		NACK
r 		OVRE
r 		GACC
r 		SVACC
r 		TXRDY
r 		RXRDY
r 		TXCOMP
r
Toggle Fields

TXCOMP

Bit 0: Transmission Completed Interrupt Mask.

RXRDY

Bit 1: Receive Holding Register Ready Interrupt Mask.

TXRDY

Bit 2: Transmit Holding Register Ready Interrupt Mask.

SVACC

Bit 4: Slave Access Interrupt Mask.

GACC

Bit 5: General Call Access Interrupt Mask.

OVRE

Bit 6: Overrun Error Interrupt Mask.

NACK

Bit 8: Not Acknowledge Interrupt Mask.

ARBLST

Bit 9: Arbitration Lost Interrupt Mask.

SCL_WS

Bit 10: Clock Wait State Interrupt Mask.

EOSACC

Bit 11: End Of Slave Access Interrupt Mask.

ENDRX

Bit 12: End of Receive Buffer Interrupt Mask.

ENDTX

Bit 13: End of Transmit Buffer Interrupt Mask.

RXBUFF

Bit 14: Receive Buffer Full Interrupt Mask.

TXBUFE

Bit 15: Transmit Buffer Empty Interrupt Mask.

RHR

Receive Holding Register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields

RXDATA

Bits 0-7: Master or Slave Receive Holding Data.

THR

Transmit Holding Register

Offset: 0x34, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
w
Toggle Fields

TXDATA

Bits 0-7: Master or Slave Transmit Holding Data.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TWI1

0x40090000: Two-wire Interface 1

33/89 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MMR
0x8 SMR
0xc IADR
0x10 CWGR
0x20 SR
0x24 IER
0x28 IDR
0x2c IMR
0x30 RHR
0x34 THR
0x100 RPR
0x104 RCR
0x108 TPR
0x10c TCR
0x110 RNPR
0x114 RNCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
w 		QUICK
w 		SVDIS
w 		SVEN
w 		MSDIS
w 		MSEN
w 		STOP
w 		START
w
Toggle Fields

START

Bit 0: Send a START Condition.

STOP

Bit 1: Send a STOP Condition.

MSEN

Bit 2: TWI Master Mode Enabled.

MSDIS

Bit 3: TWI Master Mode Disabled.

SVEN

Bit 4: TWI Slave Mode Enabled.

SVDIS

Bit 5: TWI Slave Mode Disabled.

QUICK

Bit 6: SMBUS Quick Command.

SWRST

Bit 7: Software Reset.

MMR

Master Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MREAD
rw 		IADRSZ
rw
Toggle Fields

IADRSZ

Bits 8-9: Internal Device Address Size.

Allowed values:
0x0: NONE: No internal device address
0x1: 1_BYTE: One-byte internal device address
0x2: 2_BYTE: Two-byte internal device address
0x3: 3_BYTE: Three-byte internal device address

MREAD

Bit 12: Master Read Direction.

DADR

Bits 16-22: Device Address.

SMR

Slave Mode Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields

SADR

Bits 16-22: Slave Address.

IADR

Internal Address Register

Offset: 0xc, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IADR
rw
Toggle Fields

IADR

Bits 0-23: Internal Address.

CWGR

Clock Waveform Generator Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHDIV
rw 		CLDIV
rw
Toggle Fields

CLDIV

Bits 0-7: Clock Low Divider.

CHDIV

Bits 8-15: Clock High Divider.

CKDIV

Bits 16-18: Clock Divider.

SR

Status Register

Offset: 0x20, reset: 0x0000F009, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
r 		RXBUFF
r 		ENDTX
r 		ENDRX
r 		EOSACC
r 		SCLWS
r 		ARBLST
r 		NACK
r 		OVRE
r 		GACC
r 		SVACC
r 		SVREAD
r 		TXRDY
r 		RXRDY
r 		TXCOMP
r
Toggle Fields

TXCOMP

Bit 0: Transmission Completed (automatically set / reset).

RXRDY

Bit 1: Receive Holding Register Ready (automatically set / reset).

TXRDY

Bit 2: Transmit Holding Register Ready (automatically set / reset).

SVREAD

Bit 3: Slave Read (automatically set / reset).

SVACC

Bit 4: Slave Access (automatically set / reset).

GACC

Bit 5: General Call Access (clear on read).

OVRE

Bit 6: Overrun Error (clear on read).

NACK

Bit 8: Not Acknowledged (clear on read).

ARBLST

Bit 9: Arbitration Lost (clear on read).

SCLWS

Bit 10: Clock Wait State (automatically set / reset).

EOSACC

Bit 11: End Of Slave Access (clear on read).

ENDRX

Bit 12: End of RX buffer.

ENDTX

Bit 13: End of TX buffer.

RXBUFF

Bit 14: RX Buffer Full.

TXBUFE

Bit 15: TX Buffer Empty.

IER

Interrupt Enable Register

Offset: 0x24, reset: None, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
w 		RXBUFF
w 		ENDTX
w 		ENDRX
w 		EOSACC
w 		SCL_WS
w 		ARBLST
w 		NACK
w 		OVRE
w 		GACC
w 		SVACC
w 		TXRDY
w 		RXRDY
w 		TXCOMP
w
Toggle Fields

TXCOMP

Bit 0: Transmission Completed Interrupt Enable.

RXRDY

Bit 1: Receive Holding Register Ready Interrupt Enable.

TXRDY

Bit 2: Transmit Holding Register Ready Interrupt Enable.

SVACC

Bit 4: Slave Access Interrupt Enable.

GACC

Bit 5: General Call Access Interrupt Enable.

OVRE

Bit 6: Overrun Error Interrupt Enable.

NACK

Bit 8: Not Acknowledge Interrupt Enable.

ARBLST

Bit 9: Arbitration Lost Interrupt Enable.

SCL_WS

Bit 10: Clock Wait State Interrupt Enable.

EOSACC

Bit 11: End Of Slave Access Interrupt Enable.

ENDRX

Bit 12: End of Receive Buffer Interrupt Enable.

ENDTX

Bit 13: End of Transmit Buffer Interrupt Enable.

RXBUFF

Bit 14: Receive Buffer Full Interrupt Enable.

TXBUFE

Bit 15: Transmit Buffer Empty Interrupt Enable.

IDR

Interrupt Disable Register

Offset: 0x28, reset: None, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
w 		RXBUFF
w 		ENDTX
w 		ENDRX
w 		EOSACC
w 		SCL_WS
w 		ARBLST
w 		NACK
w 		OVRE
w 		GACC
w 		SVACC
w 		TXRDY
w 		RXRDY
w 		TXCOMP
w
Toggle Fields

TXCOMP

Bit 0: Transmission Completed Interrupt Disable.

RXRDY

Bit 1: Receive Holding Register Ready Interrupt Disable.

TXRDY

Bit 2: Transmit Holding Register Ready Interrupt Disable.

SVACC

Bit 4: Slave Access Interrupt Disable.

GACC

Bit 5: General Call Access Interrupt Disable.

OVRE

Bit 6: Overrun Error Interrupt Disable.

NACK

Bit 8: Not Acknowledge Interrupt Disable.

ARBLST

Bit 9: Arbitration Lost Interrupt Disable.

SCL_WS

Bit 10: Clock Wait State Interrupt Disable.

EOSACC

Bit 11: End Of Slave Access Interrupt Disable.

ENDRX

Bit 12: End of Receive Buffer Interrupt Disable.

ENDTX

Bit 13: End of Transmit Buffer Interrupt Disable.

RXBUFF

Bit 14: Receive Buffer Full Interrupt Disable.

TXBUFE

Bit 15: Transmit Buffer Empty Interrupt Disable.

IMR

Interrupt Mask Register

Offset: 0x2c, reset: 0x00000000, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXBUFE
r 		RXBUFF
r 		ENDTX
r 		ENDRX
r 		EOSACC
r 		SCL_WS
r 		ARBLST
r 		NACK
r 		OVRE
r 		GACC
r 		SVACC
r 		TXRDY
r 		RXRDY
r 		TXCOMP
r
Toggle Fields

TXCOMP

Bit 0: Transmission Completed Interrupt Mask.

RXRDY

Bit 1: Receive Holding Register Ready Interrupt Mask.

TXRDY

Bit 2: Transmit Holding Register Ready Interrupt Mask.

SVACC

Bit 4: Slave Access Interrupt Mask.

GACC

Bit 5: General Call Access Interrupt Mask.

OVRE

Bit 6: Overrun Error Interrupt Mask.

NACK

Bit 8: Not Acknowledge Interrupt Mask.

ARBLST

Bit 9: Arbitration Lost Interrupt Mask.

SCL_WS

Bit 10: Clock Wait State Interrupt Mask.

EOSACC

Bit 11: End Of Slave Access Interrupt Mask.

ENDRX

Bit 12: End of Receive Buffer Interrupt Mask.

ENDTX

Bit 13: End of Transmit Buffer Interrupt Mask.

RXBUFF

Bit 14: Receive Buffer Full Interrupt Mask.

TXBUFE

Bit 15: Transmit Buffer Empty Interrupt Mask.

RHR

Receive Holding Register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields

RXDATA

Bits 0-7: Master or Slave Receive Holding Data.

THR

Transmit Holding Register

Offset: 0x34, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
w
Toggle Fields

TXDATA

Bits 0-7: Master or Slave Transmit Holding Data.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

UART

0x400e0800: Universal Asynchronous Receiver Transmitter

25/66 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MR
0x8 IER
0xc IDR
0x10 IMR
0x14 SR
0x18 RHR
0x1c THR
0x20 BRGR
0x100 RPR
0x104 RCR
0x108 TPR
0x10c TCR
0x110 RNPR
0x114 RNCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

MR

Mode Register

Offset: 0x4, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHMODE
rw 		PAR
rw
Toggle Fields

PAR

Bits 9-11: Parity Type.

Allowed values:
0x0: EVEN: Even Parity
0x1: ODD: Odd Parity
0x2: SPACE: Space: parity forced to 0
0x3: MARK: Mark: parity forced to 1
0x4: NO: No Parity

CHMODE

Bits 14-15: Channel Mode.

Allowed values:
0x0: NORMAL: Normal Mode
0x1: AUTOMATIC: Automatic Echo
0x2: LOCAL_LOOPBACK: Local Loopback
0x3: REMOTE_LOOPBACK: Remote Loopback

IER

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: Enable RXRDY Interrupt.

TXRDY

Bit 1: Enable TXRDY Interrupt.

ENDRX

Bit 3: Enable End of Receive Transfer Interrupt.

ENDTX

Bit 4: Enable End of Transmit Interrupt.

OVRE

Bit 5: Enable Overrun Error Interrupt.

FRAME

Bit 6: Enable Framing Error Interrupt.

PARE

Bit 7: Enable Parity Error Interrupt.

TXEMPTY

Bit 9: Enable TXEMPTY Interrupt.

TXBUFE

Bit 11: Enable Buffer Empty Interrupt.

RXBUFF

Bit 12: Enable Buffer Full Interrupt.

IDR

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: Disable RXRDY Interrupt.

TXRDY

Bit 1: Disable TXRDY Interrupt.

ENDRX

Bit 3: Disable End of Receive Transfer Interrupt.

ENDTX

Bit 4: Disable End of Transmit Interrupt.

OVRE

Bit 5: Disable Overrun Error Interrupt.

FRAME

Bit 6: Disable Framing Error Interrupt.

PARE

Bit 7: Disable Parity Error Interrupt.

TXEMPTY

Bit 9: Disable TXEMPTY Interrupt.

TXBUFE

Bit 11: Disable Buffer Empty Interrupt.

RXBUFF

Bit 12: Disable Buffer Full Interrupt.

IMR

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Mask RXRDY Interrupt.

TXRDY

Bit 1: Disable TXRDY Interrupt.

ENDRX

Bit 3: Mask End of Receive Transfer Interrupt.

ENDTX

Bit 4: Mask End of Transmit Interrupt.

OVRE

Bit 5: Mask Overrun Error Interrupt.

FRAME

Bit 6: Mask Framing Error Interrupt.

PARE

Bit 7: Mask Parity Error Interrupt.

TXEMPTY

Bit 9: Mask TXEMPTY Interrupt.

TXBUFE

Bit 11: Mask TXBUFE Interrupt.

RXBUFF

Bit 12: Mask RXBUFF Interrupt.

SR

Status Register

Offset: 0x14, reset: None, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: End of Receiver Transfer.

ENDTX

Bit 4: End of Transmitter Transfer.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TXEMPTY

Bit 9: Transmitter Empty.

TXBUFE

Bit 11: Transmission Buffer Empty.

RXBUFF

Bit 12: Receive Buffer Full.

RHR

Receive Holding Register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCHR
r
Toggle Fields

RXCHR

Bits 0-7: Received Character.

THR

Transmit Holding Register

Offset: 0x1c, reset: None, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCHR
w
Toggle Fields

TXCHR

Bits 0-7: Character to be Transmitted.

BRGR

Baud Rate Generator Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
rw
Toggle Fields

CD

Bits 0-15: Clock Divisor.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

UOTGHS

0x400ac000: USB On-The-Go Interface

862/2453 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DEVCTRL
0x4 DEVISR
0x8 DEVICR
0xc DEVIFR
0x10 DEVIMR
0x14 DEVIDR
0x18 DEVIER
0x1c DEVEPT
0x20 DEVFNUM
0x100 DEVEPTCFG[[0]]
0x104 DEVEPTCFG[[1]]
0x108 DEVEPTCFG[[2]]
0x10c DEVEPTCFG[[3]]
0x110 DEVEPTCFG[[4]]
0x114 DEVEPTCFG[[5]]
0x118 DEVEPTCFG[[6]]
0x11c DEVEPTCFG[[7]]
0x120 DEVEPTCFG[[8]]
0x124 DEVEPTCFG[[9]]
0x130 DEVEPTISR0_ISOENPT
0x130 DEVEPTISR[[0]]
0x134 DEVEPTISR[[1]]
0x138 DEVEPTISR[[2]]
0x13c DEVEPTISR[[3]]
0x140 DEVEPTISR[[4]]
0x144 DEVEPTISR[[5]]
0x148 DEVEPTISR[[6]]
0x14c DEVEPTISR[[7]]
0x150 DEVEPTISR[[8]]
0x154 DEVEPTISR[[9]]
0x160 DEVEPTICR0_ISOENPT
0x160 DEVEPTICR[[0]]
0x164 DEVEPTICR[[1]]
0x168 DEVEPTICR[[2]]
0x16c DEVEPTICR[[3]]
0x170 DEVEPTICR[[4]]
0x174 DEVEPTICR[[5]]
0x178 DEVEPTICR[[6]]
0x17c DEVEPTICR[[7]]
0x180 DEVEPTICR[[8]]
0x184 DEVEPTICR[[9]]
0x190 DEVEPTIFR0_ISOENPT
0x190 DEVEPTIFR[[0]]
0x194 DEVEPTIFR[[1]]
0x198 DEVEPTIFR[[2]]
0x19c DEVEPTIFR[[3]]
0x1a0 DEVEPTIFR[[4]]
0x1a4 DEVEPTIFR[[5]]
0x1a8 DEVEPTIFR[[6]]
0x1ac DEVEPTIFR[[7]]
0x1b0 DEVEPTIFR[[8]]
0x1b4 DEVEPTIFR[[9]]
0x1c0 DEVEPTIMR0_ISOENPT
0x1c0 DEVEPTIMR[[0]]
0x1c4 DEVEPTIMR[[1]]
0x1c8 DEVEPTIMR[[2]]
0x1cc DEVEPTIMR[[3]]
0x1d0 DEVEPTIMR[[4]]
0x1d4 DEVEPTIMR[[5]]
0x1d8 DEVEPTIMR[[6]]
0x1dc DEVEPTIMR[[7]]
0x1e0 DEVEPTIMR[[8]]
0x1e4 DEVEPTIMR[[9]]
0x1f0 DEVEPTIER0_ISOENPT
0x1f0 DEVEPTIER[[0]]
0x1f4 DEVEPTIER[[1]]
0x1f8 DEVEPTIER[[2]]
0x1fc DEVEPTIER[[3]]
0x200 DEVEPTIER[[4]]
0x204 DEVEPTIER[[5]]
0x208 DEVEPTIER[[6]]
0x20c DEVEPTIER[[7]]
0x210 DEVEPTIER[[8]]
0x214 DEVEPTIER[[9]]
0x220 DEVEPTIDR0_ISOENPT
0x220 DEVEPTIDR[[0]]
0x224 DEVEPTIDR[[1]]
0x228 DEVEPTIDR[[2]]
0x22c DEVEPTIDR[[3]]
0x230 DEVEPTIDR[[4]]
0x234 DEVEPTIDR[[5]]
0x238 DEVEPTIDR[[6]]
0x23c DEVEPTIDR[[7]]
0x240 DEVEPTIDR[[8]]
0x244 DEVEPTIDR[[9]]
0x310 DEVDMANXTDSC1
0x314 DEVDMAADDRESS1
0x318 DEVDMACONTROL1
0x31c DEVDMASTATUS1
0x320 DEVDMANXTDSC2
0x324 DEVDMAADDRESS2
0x328 DEVDMACONTROL2
0x32c DEVDMASTATUS2
0x330 DEVDMANXTDSC3
0x334 DEVDMAADDRESS3
0x338 DEVDMACONTROL3
0x33c DEVDMASTATUS3
0x340 DEVDMANXTDSC4
0x344 DEVDMAADDRESS4
0x348 DEVDMACONTROL4
0x34c DEVDMASTATUS4
0x350 DEVDMANXTDSC5
0x354 DEVDMAADDRESS5
0x358 DEVDMACONTROL5
0x35c DEVDMASTATUS5
0x360 DEVDMANXTDSC6
0x364 DEVDMAADDRESS6
0x368 DEVDMACONTROL6
0x36c DEVDMASTATUS6
0x370 DEVDMANXTDSC7
0x374 DEVDMAADDRESS7
0x378 DEVDMACONTROL7
0x37c DEVDMASTATUS7
0x400 HSTCTRL
0x404 HSTISR
0x408 HSTICR
0x40c HSTIFR
0x410 HSTIMR
0x414 HSTIDR
0x418 HSTIER
0x41c HSTPIP
0x420 HSTFNUM
0x424 HSTADDR1
0x428 HSTADDR2
0x42c HSTADDR3
0x500 HSTPIPCFG0_HSBOHSCP
0x500 HSTPIPCFG[[0]]
0x504 HSTPIPCFG[[1]]
0x508 HSTPIPCFG[[2]]
0x50c HSTPIPCFG[[3]]
0x510 HSTPIPCFG[[4]]
0x514 HSTPIPCFG[[5]]
0x518 HSTPIPCFG[[6]]
0x51c HSTPIPCFG[[7]]
0x520 HSTPIPCFG[[8]]
0x524 HSTPIPCFG[[9]]
0x530 HSTPIPISR0_INTPIPES
0x530 HSTPIPISR0_ISOPIPES
0x530 HSTPIPISR[[0]]
0x534 HSTPIPISR[[1]]
0x538 HSTPIPISR[[2]]
0x53c HSTPIPISR[[3]]
0x540 HSTPIPISR[[4]]
0x544 HSTPIPISR[[5]]
0x548 HSTPIPISR[[6]]
0x54c HSTPIPISR[[7]]
0x550 HSTPIPISR[[8]]
0x554 HSTPIPISR[[9]]
0x560 HSTPIPICR0_INTPIPES
0x560 HSTPIPICR0_ISOPIPES
0x560 HSTPIPICR[[0]]
0x564 HSTPIPICR[[1]]
0x568 HSTPIPICR[[2]]
0x56c HSTPIPICR[[3]]
0x570 HSTPIPICR[[4]]
0x574 HSTPIPICR[[5]]
0x578 HSTPIPICR[[6]]
0x57c HSTPIPICR[[7]]
0x580 HSTPIPICR[[8]]
0x584 HSTPIPICR[[9]]
0x590 HSTPIPIFR0_INTPIPES
0x590 HSTPIPIFR0_ISOPIPES
0x590 HSTPIPIFR[[0]]
0x594 HSTPIPIFR[[1]]
0x598 HSTPIPIFR[[2]]
0x59c HSTPIPIFR[[3]]
0x5a0 HSTPIPIFR[[4]]
0x5a4 HSTPIPIFR[[5]]
0x5a8 HSTPIPIFR[[6]]
0x5ac HSTPIPIFR[[7]]
0x5b0 HSTPIPIFR[[8]]
0x5b4 HSTPIPIFR[[9]]
0x5c0 HSTPIPIMR0_INTPIPES
0x5c0 HSTPIPIMR0_ISOPIPES
0x5c0 HSTPIPIMR[[0]]
0x5c4 HSTPIPIMR[[1]]
0x5c8 HSTPIPIMR[[2]]
0x5cc HSTPIPIMR[[3]]
0x5d0 HSTPIPIMR[[4]]
0x5d4 HSTPIPIMR[[5]]
0x5d8 HSTPIPIMR[[6]]
0x5dc HSTPIPIMR[[7]]
0x5e0 HSTPIPIMR[[8]]
0x5e4 HSTPIPIMR[[9]]
0x5f0 HSTPIPIER0_INTPIPES
0x5f0 HSTPIPIER0_ISOPIPES
0x5f0 HSTPIPIER[[0]]
0x5f4 HSTPIPIER[[1]]
0x5f8 HSTPIPIER[[2]]
0x5fc HSTPIPIER[[3]]
0x600 HSTPIPIER[[4]]
0x604 HSTPIPIER[[5]]
0x608 HSTPIPIER[[6]]
0x60c HSTPIPIER[[7]]
0x610 HSTPIPIER[[8]]
0x614 HSTPIPIER[[9]]
0x620 HSTPIPIDR0_INTPIPES
0x620 HSTPIPIDR0_ISOPIPES
0x620 HSTPIPIDR[[0]]
0x624 HSTPIPIDR[[1]]
0x628 HSTPIPIDR[[2]]
0x62c HSTPIPIDR[[3]]
0x630 HSTPIPIDR[[4]]
0x634 HSTPIPIDR[[5]]
0x638 HSTPIPIDR[[6]]
0x63c HSTPIPIDR[[7]]
0x640 HSTPIPIDR[[8]]
0x644 HSTPIPIDR[[9]]
0x650 HSTPIPINRQ[[0]]
0x654 HSTPIPINRQ[[1]]
0x658 HSTPIPINRQ[[2]]
0x65c HSTPIPINRQ[[3]]
0x660 HSTPIPINRQ[[4]]
0x664 HSTPIPINRQ[[5]]
0x668 HSTPIPINRQ[[6]]
0x66c HSTPIPINRQ[[7]]
0x670 HSTPIPINRQ[[8]]
0x674 HSTPIPINRQ[[9]]
0x680 HSTPIPERR[[0]]
0x684 HSTPIPERR[[1]]
0x688 HSTPIPERR[[2]]
0x68c HSTPIPERR[[3]]
0x690 HSTPIPERR[[4]]
0x694 HSTPIPERR[[5]]
0x698 HSTPIPERR[[6]]
0x69c HSTPIPERR[[7]]
0x6a0 HSTPIPERR[[8]]
0x6a4 HSTPIPERR[[9]]
0x710 HSTDMANXTDSC1
0x714 HSTDMAADDRESS1
0x718 HSTDMACONTROL1
0x71c HSTDMASTATUS1
0x720 HSTDMANXTDSC2
0x724 HSTDMAADDRESS2
0x728 HSTDMACONTROL2
0x72c HSTDMASTATUS2
0x730 HSTDMANXTDSC3
0x734 HSTDMAADDRESS3
0x738 HSTDMACONTROL3
0x73c HSTDMASTATUS3
0x740 HSTDMANXTDSC4
0x744 HSTDMAADDRESS4
0x748 HSTDMACONTROL4
0x74c HSTDMASTATUS4
0x750 HSTDMANXTDSC5
0x754 HSTDMAADDRESS5
0x758 HSTDMACONTROL5
0x75c HSTDMASTATUS5
0x760 HSTDMANXTDSC6
0x764 HSTDMAADDRESS6
0x768 HSTDMACONTROL6
0x76c HSTDMASTATUS6
0x770 HSTDMANXTDSC7
0x774 HSTDMAADDRESS7
0x778 HSTDMACONTROL7
0x77c HSTDMASTATUS7
0x800 CTRL
0x804 SR
0x808 SCR
0x80c SFR
0x82c FSM

DEVCTRL

Device General Control Register

Offset: 0x0, reset: 0x00000100, access: read-write

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPMODE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTPCKT
rw 		TSTK
rw 		TSTJ
rw 		LS
rw 		SPDCONF
rw 		RMWKUP
rw 		DETACH
rw 		ADDEN
rw 		UADD
rw
Toggle Fields

UADD

Bits 0-6: USB Address.

ADDEN

Bit 7: Address Enable.

DETACH

Bit 8: Detach.

RMWKUP

Bit 9: Remote Wake-Up.

SPDCONF

Bits 10-11: Mode Configuration.

Allowed values:
0x0: NORMAL: The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable.
0x1: LOW_POWER: For a better consumption, if high-speed is not needed.
0x2: HIGH_SPEED: Forced high speed.
0x3: FORCED_FS: The peripheral remains in full-speed mode whatever the host speed capability.

LS

Bit 12: Low-Speed Mode Force.

TSTJ

Bit 13: Test mode J.

TSTK

Bit 14: Test mode K.

TSTPCKT

Bit 15: Test packet mode.

OPMODE2

Bit 16: Specific Operational mode.

DEVISR

Device Global Interrupt Status Register

Offset: 0x4, reset: 0x00000000, access: read-only

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
r 		DMA_5
r 		DMA_4
r 		DMA_3
r 		DMA_2
r 		DMA_1
r 		PEP_9
r 		PEP_8
r 		PEP_7
r 		PEP_6
r 		PEP_5
r 		PEP_4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_3
r 		PEP_2
r 		PEP_1
r 		PEP_0
r 		UPRSM
r 		EORSM
r 		WAKEUP
r 		EORST
r 		SOF
r 		MSOF
r 		SUSP
r
Toggle Fields

SUSP

Bit 0: Suspend Interrupt.

MSOF

Bit 1: Micro Start of Frame Interrupt.

SOF

Bit 2: Start of Frame Interrupt.

EORST

Bit 3: End of Reset Interrupt.

WAKEUP

Bit 4: Wake-Up Interrupt.

EORSM

Bit 5: End of Resume Interrupt.

UPRSM

Bit 6: Upstream Resume Interrupt.

PEP_0

Bit 12: Endpoint 0 Interrupt.

PEP_1

Bit 13: Endpoint 1 Interrupt.

PEP_2

Bit 14: Endpoint 2 Interrupt.

PEP_3

Bit 15: Endpoint 3 Interrupt.

PEP_4

Bit 16: Endpoint 4 Interrupt.

PEP_5

Bit 17: Endpoint 5 Interrupt.

PEP_6

Bit 18: Endpoint 6 Interrupt.

PEP_7

Bit 19: Endpoint 7 Interrupt.

PEP_8

Bit 20: Endpoint 8 Interrupt.

PEP_9

Bit 21: Endpoint 9 Interrupt.

DMA_1

Bit 25: DMA Channel 1 Interrupt.

DMA_2

Bit 26: DMA Channel 2 Interrupt.

DMA_3

Bit 27: DMA Channel 3 Interrupt.

DMA_4

Bit 28: DMA Channel 4 Interrupt.

DMA_5

Bit 29: DMA Channel 5 Interrupt.

DMA_6

Bit 30: DMA Channel 6 Interrupt.

DEVICR

Device Global Interrupt Clear Register

Offset: 0x8, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPRSMC
w 		EORSMC
w 		WAKEUPC
w 		EORSTC
w 		SOFC
w 		MSOFC
w 		SUSPC
w
Toggle Fields

SUSPC

Bit 0: Suspend Interrupt Clear.

MSOFC

Bit 1: Micro Start of Frame Interrupt Clear.

SOFC

Bit 2: Start of Frame Interrupt Clear.

EORSTC

Bit 3: End of Reset Interrupt Clear.

WAKEUPC

Bit 4: Wake-Up Interrupt Clear.

EORSMC

Bit 5: End of Resume Interrupt Clear.

UPRSMC

Bit 6: Upstream Resume Interrupt Clear.

DEVIFR

Device Global Interrupt Set Register

Offset: 0xc, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
w 		DMA_5
w 		DMA_4
w 		DMA_3
w 		DMA_2
w 		DMA_1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPRSMS
w 		EORSMS
w 		WAKEUPS
w 		EORSTS
w 		SOFS
w 		MSOFS
w 		SUSPS
w
Toggle Fields

SUSPS

Bit 0: Suspend Interrupt Set.

MSOFS

Bit 1: Micro Start of Frame Interrupt Set.

SOFS

Bit 2: Start of Frame Interrupt Set.

EORSTS

Bit 3: End of Reset Interrupt Set.

WAKEUPS

Bit 4: Wake-Up Interrupt Set.

EORSMS

Bit 5: End of Resume Interrupt Set.

UPRSMS

Bit 6: Upstream Resume Interrupt Set.

DMA_1

Bit 25: DMA Channel 1 Interrupt Set.

DMA_2

Bit 26: DMA Channel 2 Interrupt Set.

DMA_3

Bit 27: DMA Channel 3 Interrupt Set.

DMA_4

Bit 28: DMA Channel 4 Interrupt Set.

DMA_5

Bit 29: DMA Channel 5 Interrupt Set.

DMA_6

Bit 30: DMA Channel 6 Interrupt Set.

DEVIMR

Device Global Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
r 		DMA_5
r 		DMA_4
r 		DMA_3
r 		DMA_2
r 		DMA_1
r 		PEP_9
r 		PEP_8
r 		PEP_7
r 		PEP_6
r 		PEP_5
r 		PEP_4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_3
r 		PEP_2
r 		PEP_1
r 		PEP_0
r 		UPRSME
r 		EORSME
r 		WAKEUPE
r 		EORSTE
r 		SOFE
r 		MSOFE
r 		SUSPE
r
Toggle Fields

SUSPE

Bit 0: Suspend Interrupt Mask.

MSOFE

Bit 1: Micro Start of Frame Interrupt Mask.

SOFE

Bit 2: Start of Frame Interrupt Mask.

EORSTE

Bit 3: End of Reset Interrupt Mask.

WAKEUPE

Bit 4: Wake-Up Interrupt Mask.

EORSME

Bit 5: End of Resume Interrupt Mask.

UPRSME

Bit 6: Upstream Resume Interrupt Mask.

PEP_0

Bit 12: Endpoint 0 Interrupt Mask.

PEP_1

Bit 13: Endpoint 1 Interrupt Mask.

PEP_2

Bit 14: Endpoint 2 Interrupt Mask.

PEP_3

Bit 15: Endpoint 3 Interrupt Mask.

PEP_4

Bit 16: Endpoint 4 Interrupt Mask.

PEP_5

Bit 17: Endpoint 5 Interrupt Mask.

PEP_6

Bit 18: Endpoint 6 Interrupt Mask.

PEP_7

Bit 19: Endpoint 7 Interrupt Mask.

PEP_8

Bit 20: Endpoint 8 Interrupt Mask.

PEP_9

Bit 21: Endpoint 9 Interrupt Mask.

DMA_1

Bit 25: DMA Channel 1 Interrupt Mask.

DMA_2

Bit 26: DMA Channel 2 Interrupt Mask.

DMA_3

Bit 27: DMA Channel 3 Interrupt Mask.

DMA_4

Bit 28: DMA Channel 4 Interrupt Mask.

DMA_5

Bit 29: DMA Channel 5 Interrupt Mask.

DMA_6

Bit 30: DMA Channel 6 Interrupt Mask.

DEVIDR

Device Global Interrupt Disable Register

Offset: 0x14, reset: None, access: write-only

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
w 		DMA_5
w 		DMA_4
w 		DMA_3
w 		DMA_2
w 		DMA_1
w 		PEP_9
w 		PEP_8
w 		PEP_7
w 		PEP_6
w 		PEP_5
w 		PEP_4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_3
w 		PEP_2
w 		PEP_1
w 		PEP_0
w 		UPRSMEC
w 		EORSMEC
w 		WAKEUPEC
w 		EORSTEC
w 		SOFEC
w 		MSOFEC
w 		SUSPEC
w
Toggle Fields

SUSPEC

Bit 0: Suspend Interrupt Disable.

MSOFEC

Bit 1: Micro Start of Frame Interrupt Disable.

SOFEC

Bit 2: Start of Frame Interrupt Disable.

EORSTEC

Bit 3: End of Reset Interrupt Disable.

WAKEUPEC

Bit 4: Wake-Up Interrupt Disable.

EORSMEC

Bit 5: End of Resume Interrupt Disable.

UPRSMEC

Bit 6: Upstream Resume Interrupt Disable.

PEP_0

Bit 12: Endpoint 0 Interrupt Disable.

PEP_1

Bit 13: Endpoint 1 Interrupt Disable.

PEP_2

Bit 14: Endpoint 2 Interrupt Disable.

PEP_3

Bit 15: Endpoint 3 Interrupt Disable.

PEP_4

Bit 16: Endpoint 4 Interrupt Disable.

PEP_5

Bit 17: Endpoint 5 Interrupt Disable.

PEP_6

Bit 18: Endpoint 6 Interrupt Disable.

PEP_7

Bit 19: Endpoint 7 Interrupt Disable.

PEP_8

Bit 20: Endpoint 8 Interrupt Disable.

PEP_9

Bit 21: Endpoint 9 Interrupt Disable.

DMA_1

Bit 25: DMA Channel 1 Interrupt Disable.

DMA_2

Bit 26: DMA Channel 2 Interrupt Disable.

DMA_3

Bit 27: DMA Channel 3 Interrupt Disable.

DMA_4

Bit 28: DMA Channel 4 Interrupt Disable.

DMA_5

Bit 29: DMA Channel 5 Interrupt Disable.

DMA_6

Bit 30: DMA Channel 6 Interrupt Disable.

DEVIER

Device Global Interrupt Enable Register

Offset: 0x18, reset: None, access: write-only

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
w 		DMA_5
w 		DMA_4
w 		DMA_3
w 		DMA_2
w 		DMA_1
w 		PEP_9
w 		PEP_8
w 		PEP_7
w 		PEP_6
w 		PEP_5
w 		PEP_4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_3
w 		PEP_2
w 		PEP_1
w 		PEP_0
w 		UPRSMES
w 		EORSMES
w 		WAKEUPES
w 		EORSTES
w 		SOFES
w 		MSOFES
w 		SUSPES
w
Toggle Fields

SUSPES

Bit 0: Suspend Interrupt Enable.

MSOFES

Bit 1: Micro Start of Frame Interrupt Enable.

SOFES

Bit 2: Start of Frame Interrupt Enable.

EORSTES

Bit 3: End of Reset Interrupt Enable.

WAKEUPES

Bit 4: Wake-Up Interrupt Enable.

EORSMES

Bit 5: End of Resume Interrupt Enable.

UPRSMES

Bit 6: Upstream Resume Interrupt Enable.

PEP_0

Bit 12: Endpoint 0 Interrupt Enable.

PEP_1

Bit 13: Endpoint 1 Interrupt Enable.

PEP_2

Bit 14: Endpoint 2 Interrupt Enable.

PEP_3

Bit 15: Endpoint 3 Interrupt Enable.

PEP_4

Bit 16: Endpoint 4 Interrupt Enable.

PEP_5

Bit 17: Endpoint 5 Interrupt Enable.

PEP_6

Bit 18: Endpoint 6 Interrupt Enable.

PEP_7

Bit 19: Endpoint 7 Interrupt Enable.

PEP_8

Bit 20: Endpoint 8 Interrupt Enable.

PEP_9

Bit 21: Endpoint 9 Interrupt Enable.

DMA_1

Bit 25: DMA Channel 1 Interrupt Enable.

DMA_2

Bit 26: DMA Channel 2 Interrupt Enable.

DMA_3

Bit 27: DMA Channel 3 Interrupt Enable.

DMA_4

Bit 28: DMA Channel 4 Interrupt Enable.

DMA_5

Bit 29: DMA Channel 5 Interrupt Enable.

DMA_6

Bit 30: DMA Channel 6 Interrupt Enable.

DEVEPT

Device Endpoint Register

Offset: 0x1c, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPRST8
rw 		EPRST7
rw 		EPRST6
rw 		EPRST5
rw 		EPRST4
rw 		EPRST3
rw 		EPRST2
rw 		EPRST1
rw 		EPRST0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPEN8
rw 		EPEN7
rw 		EPEN6
rw 		EPEN5
rw 		EPEN4
rw 		EPEN3
rw 		EPEN2
rw 		EPEN1
rw 		EPEN0
rw
Toggle Fields

EPEN0

Bit 0: Endpoint 0 Enable.

EPEN1

Bit 1: Endpoint 1 Enable.

EPEN2

Bit 2: Endpoint 2 Enable.

EPEN3

Bit 3: Endpoint 3 Enable.

EPEN4

Bit 4: Endpoint 4 Enable.

EPEN5

Bit 5: Endpoint 5 Enable.

EPEN6

Bit 6: Endpoint 6 Enable.

EPEN7

Bit 7: Endpoint 7 Enable.

EPEN8

Bit 8: Endpoint 8 Enable.

EPRST0

Bit 16: Endpoint 0 Reset.

EPRST1

Bit 17: Endpoint 1 Reset.

EPRST2

Bit 18: Endpoint 2 Reset.

EPRST3

Bit 19: Endpoint 3 Reset.

EPRST4

Bit 20: Endpoint 4 Reset.

EPRST5

Bit 21: Endpoint 5 Reset.

EPRST6

Bit 22: Endpoint 6 Reset.

EPRST7

Bit 23: Endpoint 7 Reset.

EPRST8

Bit 24: Endpoint 8 Reset.

DEVFNUM

Device Frame Number Register

Offset: 0x20, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNCERR
r 		FNUM
r 		MFNUM
r
Toggle Fields

MFNUM

Bits 0-2: Micro Frame Number.

FNUM

Bits 3-13: Frame Number.

FNCERR

Bit 15: Frame Number CRC Error.

DEVEPTCFG[[0]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x100, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[1]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x104, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[2]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x108, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[3]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x10c, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[4]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x110, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[5]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x114, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[6]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x118, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[7]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x11c, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[8]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x120, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTCFG[[9]]

Device Endpoint Configuration Register (n = 0)

Offset: 0x124, reset: None, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBTRANS
rw 		EPTYPE
rw 		AUTOSW
rw 		EPDIR
rw 		EPSIZE
rw 		EPBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Endpoint Memory Allocate.

EPBK

Bits 2-3: Endpoint Banks.

Allowed values:
0x0: 1_BANK: Single-bank endpoint
0x1: 2_BANK: Double-bank endpoint
0x2: 3_BANK: Triple-bank endpoint

EPSIZE

Bits 4-6: Endpoint Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

EPDIR

Bit 8: Endpoint Direction.

Allowed values:
0: OUT: The endpoint direction is OUT.
1: IN: The endpoint direction is IN (nor for control endpoints).

AUTOSW

Bit 9: Automatic Switch.

EPTYPE

Bits 11-12: Endpoint Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

NBTRANS

Bits 13-14: Number of transaction per microframe for isochronous endpoint.

Allowed values:
0x0: 0_TRANS: reserved to endpoint that does not have the high-bandwidth isochronous capability.
0x1: 1_TRANS: default value: one transaction per micro-frame.
0x2: 2_TRANS: 2 transactions per micro-frame. This endpoint should be configured as double-bank.
0x3: 3_TRANS: 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

DEVEPTISR0_ISOENPT

Device Endpoint Status Register (n = 0)

Offset: 0x130, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		ERRORTRANS
r 		DTSEQ
r 		SHORTPACKET
r 		CRCERRI
r 		OVERFI
r 		HBISOFLUSHI
r 		HBISOINERRI
r 		UNDERFI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

UNDERFI

Bit 2: Underflow Interrupt.

HBISOINERRI

Bit 3: High Bandwidth Isochronous IN Underflow Error Interrupt.

HBISOFLUSHI

Bit 4: High Bandwidth Isochronous IN Flush Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

CRCERRI

Bit 6: CRC Error Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Data2 toggle sequence (for high-bandwidth isochronous endpoint)
0x3: MDATA: MData toggle sequence (for high-bandwidth isochronous endpoint)

ERRORTRANS

Bit 10: High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt.

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[0]]

Device Endpoint Status Register (n = 0)

Offset: 0x130, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[1]]

Device Endpoint Status Register (n = 0)

Offset: 0x134, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[2]]

Device Endpoint Status Register (n = 0)

Offset: 0x138, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[3]]

Device Endpoint Status Register (n = 0)

Offset: 0x13c, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[4]]

Device Endpoint Status Register (n = 0)

Offset: 0x140, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[5]]

Device Endpoint Status Register (n = 0)

Offset: 0x144, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[6]]

Device Endpoint Status Register (n = 0)

Offset: 0x148, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[7]]

Device Endpoint Status Register (n = 0)

Offset: 0x14c, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[8]]

Device Endpoint Status Register (n = 0)

Offset: 0x150, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTISR[[9]]

Device Endpoint Status Register (n = 0)

Offset: 0x154, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYCT
r 		CFGOK
r 		CTRLDIR
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKET
r 		STALLEDI
r 		OVERFI
r 		NAKINI
r 		NAKOUTI
r 		RXSTPI
r 		RXOUTI
r 		TXINI
r
Toggle Fields

TXINI

Bit 0: Transmitted IN Data Interrupt.

RXOUTI

Bit 1: Received OUT Data Interrupt.

RXSTPI

Bit 2: Received SETUP Interrupt.

NAKOUTI

Bit 3: NAKed OUT Interrupt.

NAKINI

Bit 4: NAKed IN Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

STALLEDI

Bit 6: STALLed Interrupt.

SHORTPACKET

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0x0: DATA0: Data0 toggle sequence
0x1: DATA1: Data1 toggle sequence
0x2: DATA2: Reserved for high-bandwidth isochronous endpoint
0x3: MDATA: Reserved for high-bandwidth isochronous endpoint

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CTRLDIR

Bit 17: Control Direction.

CFGOK

Bit 18: Configuration OK Status.

BYCT

Bits 20-30: Byte Count.

DEVEPTICR0_ISOENPT

Device Endpoint Clear Register (n = 0)

Offset: 0x160, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		CRCERRIC
w 		OVERFIC
w 		HBISOFLUSHIC
w 		HBISOINERRIC
w 		UNDERFIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

UNDERFIC

Bit 2: Underflow Interrupt Clear.

HBISOINERRIC

Bit 3: High bandwidth isochronous IN Underflow Error Interrupt Clear.

HBISOFLUSHIC

Bit 4: High Bandwidth Isochronous IN Flush Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

CRCERRIC

Bit 6: CRC Error Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[0]]

Device Endpoint Clear Register (n = 0)

Offset: 0x160, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[1]]

Device Endpoint Clear Register (n = 0)

Offset: 0x164, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[2]]

Device Endpoint Clear Register (n = 0)

Offset: 0x168, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[3]]

Device Endpoint Clear Register (n = 0)

Offset: 0x16c, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[4]]

Device Endpoint Clear Register (n = 0)

Offset: 0x170, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[5]]

Device Endpoint Clear Register (n = 0)

Offset: 0x174, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[6]]

Device Endpoint Clear Register (n = 0)

Offset: 0x178, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[7]]

Device Endpoint Clear Register (n = 0)

Offset: 0x17c, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[8]]

Device Endpoint Clear Register (n = 0)

Offset: 0x180, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTICR[[9]]

Device Endpoint Clear Register (n = 0)

Offset: 0x184, reset: None, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETC
w 		STALLEDIC
w 		OVERFIC
w 		NAKINIC
w 		NAKOUTIC
w 		RXSTPIC
w 		RXOUTIC
w 		TXINIC
w
Toggle Fields

TXINIC

Bit 0: Transmitted IN Data Interrupt Clear.

RXOUTIC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPIC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTIC

Bit 3: NAKed OUT Interrupt Clear.

NAKINIC

Bit 4: NAKed IN Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

STALLEDIC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETC

Bit 7: Short Packet Interrupt Clear.

DEVEPTIFR0_ISOENPT

Device Endpoint Set Register (n = 0)

Offset: 0x190, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		CRCERRIS
w 		OVERFIS
w 		HBISOFLUSHIS
w 		HBISOINERRIS
w 		UNDERFIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

UNDERFIS

Bit 2: Underflow Interrupt Set.

HBISOINERRIS

Bit 3: High bandwidth isochronous IN Underflow Error Interrupt Set.

HBISOFLUSHIS

Bit 4: High Bandwidth Isochronous IN Flush Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

CRCERRIS

Bit 6: CRC Error Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[0]]

Device Endpoint Set Register (n = 0)

Offset: 0x190, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[1]]

Device Endpoint Set Register (n = 0)

Offset: 0x194, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[2]]

Device Endpoint Set Register (n = 0)

Offset: 0x198, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[3]]

Device Endpoint Set Register (n = 0)

Offset: 0x19c, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[4]]

Device Endpoint Set Register (n = 0)

Offset: 0x1a0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[5]]

Device Endpoint Set Register (n = 0)

Offset: 0x1a4, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[6]]

Device Endpoint Set Register (n = 0)

Offset: 0x1a8, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[7]]

Device Endpoint Set Register (n = 0)

Offset: 0x1ac, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[8]]

Device Endpoint Set Register (n = 0)

Offset: 0x1b0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIFR[[9]]

Device Endpoint Set Register (n = 0)

Offset: 0x1b4, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETS
w 		STALLEDIS
w 		OVERFIS
w 		NAKINIS
w 		NAKOUTIS
w 		RXSTPIS
w 		RXOUTIS
w 		TXINIS
w
Toggle Fields

TXINIS

Bit 0: Transmitted IN Data Interrupt Set.

RXOUTIS

Bit 1: Received OUT Data Interrupt Set.

RXSTPIS

Bit 2: Received SETUP Interrupt Set.

NAKOUTIS

Bit 3: NAKed OUT Interrupt Set.

NAKINIS

Bit 4: NAKed IN Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

STALLEDIS

Bit 6: STALLed Interrupt Set.

SHORTPACKETS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Interrupt Set.

DEVEPTIMR0_ISOENPT

Device Endpoint Mask Register (n = 0)

Offset: 0x1c0, reset: None, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		ERRORTRANSE
r 		DATAXE
r 		MDATAE
r 		SHORTPACKETE
r 		CRCERRE
r 		OVERFE
r 		HBISOFLUSHE
r 		HBISOINERRE
r 		UNDERFE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

UNDERFE

Bit 2: Underflow Interrupt.

HBISOINERRE

Bit 3: High Bandwidth Isochronous IN Error Interrupt.

HBISOFLUSHE

Bit 4: High Bandwidth Isochronous IN Flush Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

CRCERRE

Bit 6: CRC Error Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

MDATAE

Bit 8: MData Interrupt.

DATAXE

Bit 9: DataX Interrupt.

ERRORTRANSE

Bit 10: Transaction Error Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

RSTDT

Bit 18: Reset Data Toggle.

DEVEPTIMR[[0]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1c0, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[1]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1c4, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[2]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1c8, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[3]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1cc, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[4]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1d0, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[5]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1d4, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[6]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1d8, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[7]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1dc, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[8]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1e0, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIMR[[9]]

Device Endpoint Mask Register (n = 0)

Offset: 0x1e4, reset: None, access: read-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQ
r 		RSTDT
r 		NYETDIS
r 		EPDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		KILLBK
r 		NBUSYBKE
r 		SHORTPACKETE
r 		STALLEDE
r 		OVERFE
r 		NAKINE
r 		NAKOUTE
r 		RXSTPE
r 		RXOUTE
r 		TXINE
r
Toggle Fields

TXINE

Bit 0: Transmitted IN Data Interrupt.

RXOUTE

Bit 1: Received OUT Data Interrupt.

RXSTPE

Bit 2: Received SETUP Interrupt.

NAKOUTE

Bit 3: NAKed OUT Interrupt.

NAKINE

Bit 4: NAKed IN Interrupt.

OVERFE

Bit 5: Overflow Interrupt.

STALLEDE

Bit 6: STALLed Interrupt.

SHORTPACKETE

Bit 7: Short Packet Interrupt.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt.

KILLBK

Bit 13: Kill IN Bank.

FIFOCON

Bit 14: FIFO Control.

EPDISHDMA

Bit 16: Endpoint Interrupts Disable HDMA Request.

NYETDIS

Bit 17: NYET Token Disable.

RSTDT

Bit 18: Reset Data Toggle.

STALLRQ

Bit 19: STALL Request.

DEVEPTIER0_ISOENPT

Device Endpoint Enable Register (n = 0)

Offset: 0x1f0, reset: None, access: write-only

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		ERRORTRANSES
w 		DATAXES
w 		MDATAES
w 		SHORTPACKETES
w 		CRCERRES
w 		OVERFES
w 		HBISOFLUSHES
w 		HBISOINERRES
w 		UNDERFES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

UNDERFES

Bit 2: Underflow Interrupt Enable.

HBISOINERRES

Bit 3: High Bandwidth Isochronous IN Error Interrupt Enable.

HBISOFLUSHES

Bit 4: High Bandwidth Isochronous IN Flush Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

CRCERRES

Bit 6: CRC Error Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

MDATAES

Bit 8: MData Interrupt Enable.

DATAXES

Bit 9: DataX Interrupt Enable.

ERRORTRANSES

Bit 10: Transaction Error Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[0]]

Device Endpoint Enable Register (n = 0)

Offset: 0x1f0, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[1]]

Device Endpoint Enable Register (n = 0)

Offset: 0x1f4, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[2]]

Device Endpoint Enable Register (n = 0)

Offset: 0x1f8, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[3]]

Device Endpoint Enable Register (n = 0)

Offset: 0x1fc, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[4]]

Device Endpoint Enable Register (n = 0)

Offset: 0x200, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[5]]

Device Endpoint Enable Register (n = 0)

Offset: 0x204, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[6]]

Device Endpoint Enable Register (n = 0)

Offset: 0x208, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[7]]

Device Endpoint Enable Register (n = 0)

Offset: 0x20c, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[8]]

Device Endpoint Enable Register (n = 0)

Offset: 0x210, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIER[[9]]

Device Endpoint Enable Register (n = 0)

Offset: 0x214, reset: None, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQS
w 		RSTDTS
w 		NYETDISS
w 		EPDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONS
w 		KILLBKS
w 		NBUSYBKES
w 		SHORTPACKETES
w 		STALLEDES
w 		OVERFES
w 		NAKINES
w 		NAKOUTES
w 		RXSTPES
w 		RXOUTES
w 		TXINES
w
Toggle Fields

TXINES

Bit 0: Transmitted IN Data Interrupt Enable.

RXOUTES

Bit 1: Received OUT Data Interrupt Enable.

RXSTPES

Bit 2: Received SETUP Interrupt Enable.

NAKOUTES

Bit 3: NAKed OUT Interrupt Enable.

NAKINES

Bit 4: NAKed IN Interrupt Enable.

OVERFES

Bit 5: Overflow Interrupt Enable.

STALLEDES

Bit 6: STALLed Interrupt Enable.

SHORTPACKETES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Interrupt Enable.

KILLBKS

Bit 13: Kill IN Bank.

FIFOCONS

Bit 14: FIFO Control.

EPDISHDMAS

Bit 16: Endpoint Interrupts Disable HDMA Request Enable.

NYETDISS

Bit 17: NYET Token Disable Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

STALLRQS

Bit 19: STALL Request Enable.

DEVEPTIDR0_ISOENPT

Device Endpoint Disable Register (n = 0)

Offset: 0x220, reset: None, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		ERRORTRANSEC
w 		DATAXEC
w 		MDATEC
w 		SHORTPACKETEC
w 		CRCERREC
w 		OVERFEC
w 		HBISOFLUSHEC
w 		HBISOINERREC
w 		UNDERFEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

UNDERFEC

Bit 2: Underflow Interrupt Clear.

HBISOINERREC

Bit 3: High Bandwidth Isochronous IN Error Interrupt Clear.

HBISOFLUSHEC

Bit 4: High Bandwidth Isochronous IN Flush Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

CRCERREC

Bit 6: CRC Error Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

MDATEC

Bit 8: MData Interrupt Clear.

DATAXEC

Bit 9: DataX Interrupt Clear.

ERRORTRANSEC

Bit 10: Transaction Error Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

DEVEPTIDR[[0]]

Device Endpoint Disable Register (n = 0)

Offset: 0x220, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[1]]

Device Endpoint Disable Register (n = 0)

Offset: 0x224, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[2]]

Device Endpoint Disable Register (n = 0)

Offset: 0x228, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[3]]

Device Endpoint Disable Register (n = 0)

Offset: 0x22c, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[4]]

Device Endpoint Disable Register (n = 0)

Offset: 0x230, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[5]]

Device Endpoint Disable Register (n = 0)

Offset: 0x234, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[6]]

Device Endpoint Disable Register (n = 0)

Offset: 0x238, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[7]]

Device Endpoint Disable Register (n = 0)

Offset: 0x23c, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[8]]

Device Endpoint Disable Register (n = 0)

Offset: 0x240, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVEPTIDR[[9]]

Device Endpoint Disable Register (n = 0)

Offset: 0x244, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STALLRQC
w 		NYETDISC
w 		EPDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETEC
w 		STALLEDEC
w 		OVERFEC
w 		NAKINEC
w 		NAKOUTEC
w 		RXSTPEC
w 		RXOUTEC
w 		TXINEC
w
Toggle Fields

TXINEC

Bit 0: Transmitted IN Interrupt Clear.

RXOUTEC

Bit 1: Received OUT Data Interrupt Clear.

RXSTPEC

Bit 2: Received SETUP Interrupt Clear.

NAKOUTEC

Bit 3: NAKed OUT Interrupt Clear.

NAKINEC

Bit 4: NAKed IN Interrupt Clear.

OVERFEC

Bit 5: Overflow Interrupt Clear.

STALLEDEC

Bit 6: STALLed Interrupt Clear.

SHORTPACKETEC

Bit 7: Shortpacket Interrupt Clear.

NBUSYBKEC

Bit 12: Number of Busy Banks Interrupt Clear.

FIFOCONC

Bit 14: FIFO Control Clear.

EPDISHDMAC

Bit 16: Endpoint Interrupts Disable HDMA Request Clear.

NYETDISC

Bit 17: NYET Token Disable Clear.

STALLRQC

Bit 19: STALL Request Clear.

DEVDMANXTDSC1

Device DMA Channel Next Descriptor Address Register (n = 1)

Offset: 0x310, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

DEVDMAADDRESS1

Device DMA Channel Address Register (n = 1)

Offset: 0x314, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

DEVDMACONTROL1

Device DMA Channel Control Register (n = 1)

Offset: 0x318, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable Control.

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

DEVDMASTATUS1

Device DMA Channel Status Register (n = 1)

Offset: 0x31c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

DEVDMANXTDSC2

Device DMA Channel Next Descriptor Address Register (n = 2)

Offset: 0x320, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

DEVDMAADDRESS2

Device DMA Channel Address Register (n = 2)

Offset: 0x324, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

DEVDMACONTROL2

Device DMA Channel Control Register (n = 2)

Offset: 0x328, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable Control.

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

DEVDMASTATUS2

Device DMA Channel Status Register (n = 2)

Offset: 0x32c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

DEVDMANXTDSC3

Device DMA Channel Next Descriptor Address Register (n = 3)

Offset: 0x330, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

DEVDMAADDRESS3

Device DMA Channel Address Register (n = 3)

Offset: 0x334, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

DEVDMACONTROL3

Device DMA Channel Control Register (n = 3)

Offset: 0x338, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable Control.

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

DEVDMASTATUS3

Device DMA Channel Status Register (n = 3)

Offset: 0x33c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

DEVDMANXTDSC4

Device DMA Channel Next Descriptor Address Register (n = 4)

Offset: 0x340, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

DEVDMAADDRESS4

Device DMA Channel Address Register (n = 4)

Offset: 0x344, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

DEVDMACONTROL4

Device DMA Channel Control Register (n = 4)

Offset: 0x348, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable Control.

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

DEVDMASTATUS4

Device DMA Channel Status Register (n = 4)

Offset: 0x34c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

DEVDMANXTDSC5

Device DMA Channel Next Descriptor Address Register (n = 5)

Offset: 0x350, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

DEVDMAADDRESS5

Device DMA Channel Address Register (n = 5)

Offset: 0x354, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

DEVDMACONTROL5

Device DMA Channel Control Register (n = 5)

Offset: 0x358, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable Control.

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

DEVDMASTATUS5

Device DMA Channel Status Register (n = 5)

Offset: 0x35c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

DEVDMANXTDSC6

Device DMA Channel Next Descriptor Address Register (n = 6)

Offset: 0x360, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

DEVDMAADDRESS6

Device DMA Channel Address Register (n = 6)

Offset: 0x364, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

DEVDMACONTROL6

Device DMA Channel Control Register (n = 6)

Offset: 0x368, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable Control.

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

DEVDMASTATUS6

Device DMA Channel Status Register (n = 6)

Offset: 0x36c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

DEVDMANXTDSC7

Device DMA Channel Next Descriptor Address Register (n = 7)

Offset: 0x370, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

DEVDMAADDRESS7

Device DMA Channel Address Register (n = 7)

Offset: 0x374, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

DEVDMACONTROL7

Device DMA Channel Control Register (n = 7)

Offset: 0x378, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable Control.

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

DEVDMASTATUS7

Device DMA Channel Status Register (n = 7)

Offset: 0x37c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

HSTCTRL

Host General Control Register

Offset: 0x400, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPDCONF
rw 		RESUME
rw 		RESET
rw 		SOFE
rw
Toggle Fields

SOFE

Bit 8: Start of Frame Generation Enable.

RESET

Bit 9: Send USB Reset.

RESUME

Bit 10: Send USB Resume.

SPDCONF

Bits 12-13: Mode Configuration.

Allowed values:
0x0: NORMAL: The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable.
0x1: LOW_POWER: For a better consumption, if high-speed is not needed.
0x2: HIGH_SPEED: Forced high speed.
0x3: FORCED_FS: The host remains to full-speed mode whatever the peripheral speed capability.

HSTISR

Host Global Interrupt Status Register

Offset: 0x404, reset: 0x00000000, access: read-only

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
r 		DMA_5
r 		DMA_4
r 		DMA_3
r 		DMA_2
r 		DMA_1
r 		PEP_9
r 		PEP_8
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_7
r 		PEP_6
r 		PEP_5
r 		PEP_4
r 		PEP_3
r 		PEP_2
r 		PEP_1
r 		PEP_0
r 		HWUPI
r 		HSOFI
r 		RXRSMI
r 		RSMEDI
r 		RSTI
r 		DDISCI
r 		DCONNI
r
Toggle Fields

DCONNI

Bit 0: Device Connection Interrupt.

DDISCI

Bit 1: Device Disconnection Interrupt.

RSTI

Bit 2: USB Reset Sent Interrupt.

RSMEDI

Bit 3: Downstream Resume Sent Interrupt.

RXRSMI

Bit 4: Upstream Resume Received Interrupt.

HSOFI

Bit 5: Host Start of Frame Interrupt.

HWUPI

Bit 6: Host Wake-Up Interrupt.

PEP_0

Bit 8: Pipe 0 Interrupt.

PEP_1

Bit 9: Pipe 1 Interrupt.

PEP_2

Bit 10: Pipe 2 Interrupt.

PEP_3

Bit 11: Pipe 3 Interrupt.

PEP_4

Bit 12: Pipe 4 Interrupt.

PEP_5

Bit 13: Pipe 5 Interrupt.

PEP_6

Bit 14: Pipe 6 Interrupt.

PEP_7

Bit 15: Pipe 7 Interrupt.

PEP_8

Bit 16: Pipe 8 Interrupt.

PEP_9

Bit 17: Pipe 9 Interrupt.

DMA_1

Bit 25: DMA Channel 1 Interrupt.

DMA_2

Bit 26: DMA Channel 2 Interrupt.

DMA_3

Bit 27: DMA Channel 3 Interrupt.

DMA_4

Bit 28: DMA Channel 4 Interrupt.

DMA_5

Bit 29: DMA Channel 5 Interrupt.

DMA_6

Bit 30: DMA Channel 6 Interrupt.

HSTICR

Host Global Interrupt Clear Register

Offset: 0x408, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWUPIC
w 		HSOFIC
w 		RXRSMIC
w 		RSMEDIC
w 		RSTIC
w 		DDISCIC
w 		DCONNIC
w
Toggle Fields

DCONNIC

Bit 0: Device Connection Interrupt Clear.

DDISCIC

Bit 1: Device Disconnection Interrupt Clear.

RSTIC

Bit 2: USB Reset Sent Interrupt Clear.

RSMEDIC

Bit 3: Downstream Resume Sent Interrupt Clear.

RXRSMIC

Bit 4: Upstream Resume Received Interrupt Clear.

HSOFIC

Bit 5: Host Start of Frame Interrupt Clear.

HWUPIC

Bit 6: Host Wake-Up Interrupt Clear.

HSTIFR

Host Global Interrupt Set Register

Offset: 0x40c, reset: None, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
w 		DMA_5
w 		DMA_4
w 		DMA_3
w 		DMA_2
w 		DMA_1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWUPIS
w 		HSOFIS
w 		RXRSMIS
w 		RSMEDIS
w 		RSTIS
w 		DDISCIS
w 		DCONNIS
w
Toggle Fields

DCONNIS

Bit 0: Device Connection Interrupt Set.

DDISCIS

Bit 1: Device Disconnection Interrupt Set.

RSTIS

Bit 2: USB Reset Sent Interrupt Set.

RSMEDIS

Bit 3: Downstream Resume Sent Interrupt Set.

RXRSMIS

Bit 4: Upstream Resume Received Interrupt Set.

HSOFIS

Bit 5: Host Start of Frame Interrupt Set.

HWUPIS

Bit 6: Host Wake-Up Interrupt Set.

DMA_1

Bit 25: DMA Channel 1 Interrupt Set.

DMA_2

Bit 26: DMA Channel 2 Interrupt Set.

DMA_3

Bit 27: DMA Channel 3 Interrupt Set.

DMA_4

Bit 28: DMA Channel 4 Interrupt Set.

DMA_5

Bit 29: DMA Channel 5 Interrupt Set.

DMA_6

Bit 30: DMA Channel 6 Interrupt Set.

HSTIMR

Host Global Interrupt Mask Register

Offset: 0x410, reset: 0x00000000, access: read-only

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
r 		DMA_5
r 		DMA_4
r 		DMA_3
r 		DMA_2
r 		DMA_1
r 		PEP_9
r 		PEP_8
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_7
r 		PEP_6
r 		PEP_5
r 		PEP_4
r 		PEP_3
r 		PEP_2
r 		PEP_1
r 		PEP_0
r 		HWUPIE
r 		HSOFIE
r 		RXRSMIE
r 		RSMEDIE
r 		RSTIE
r 		DDISCIE
r 		DCONNIE
r
Toggle Fields

DCONNIE

Bit 0: Device Connection Interrupt Enable.

DDISCIE

Bit 1: Device Disconnection Interrupt Enable.

RSTIE

Bit 2: USB Reset Sent Interrupt Enable.

RSMEDIE

Bit 3: Downstream Resume Sent Interrupt Enable.

RXRSMIE

Bit 4: Upstream Resume Received Interrupt Enable.

HSOFIE

Bit 5: Host Start of Frame Interrupt Enable.

HWUPIE

Bit 6: Host Wake-Up Interrupt Enable.

PEP_0

Bit 8: Pipe 0 Interrupt Enable.

PEP_1

Bit 9: Pipe 1 Interrupt Enable.

PEP_2

Bit 10: Pipe 2 Interrupt Enable.

PEP_3

Bit 11: Pipe 3 Interrupt Enable.

PEP_4

Bit 12: Pipe 4 Interrupt Enable.

PEP_5

Bit 13: Pipe 5 Interrupt Enable.

PEP_6

Bit 14: Pipe 6 Interrupt Enable.

PEP_7

Bit 15: Pipe 7 Interrupt Enable.

PEP_8

Bit 16: Pipe 8 Interrupt Enable.

PEP_9

Bit 17: Pipe 9 Interrupt Enable.

DMA_1

Bit 25: DMA Channel 1 Interrupt Enable.

DMA_2

Bit 26: DMA Channel 2 Interrupt Enable.

DMA_3

Bit 27: DMA Channel 3 Interrupt Enable.

DMA_4

Bit 28: DMA Channel 4 Interrupt Enable.

DMA_5

Bit 29: DMA Channel 5 Interrupt Enable.

DMA_6

Bit 30: DMA Channel 6 Interrupt Enable.

HSTIDR

Host Global Interrupt Disable Register

Offset: 0x414, reset: None, access: write-only

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
w 		DMA_5
w 		DMA_4
w 		DMA_3
w 		DMA_2
w 		DMA_1
w 		PEP_9
w 		PEP_8
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_7
w 		PEP_6
w 		PEP_5
w 		PEP_4
w 		PEP_3
w 		PEP_2
w 		PEP_1
w 		PEP_0
w 		HWUPIEC
w 		HSOFIEC
w 		RXRSMIEC
w 		RSMEDIEC
w 		RSTIEC
w 		DDISCIEC
w 		DCONNIEC
w
Toggle Fields

DCONNIEC

Bit 0: Device Connection Interrupt Disable.

DDISCIEC

Bit 1: Device Disconnection Interrupt Disable.

RSTIEC

Bit 2: USB Reset Sent Interrupt Disable.

RSMEDIEC

Bit 3: Downstream Resume Sent Interrupt Disable.

RXRSMIEC

Bit 4: Upstream Resume Received Interrupt Disable.

HSOFIEC

Bit 5: Host Start of Frame Interrupt Disable.

HWUPIEC

Bit 6: Host Wake-Up Interrupt Disable.

PEP_0

Bit 8: Pipe 0 Interrupt Disable.

PEP_1

Bit 9: Pipe 1 Interrupt Disable.

PEP_2

Bit 10: Pipe 2 Interrupt Disable.

PEP_3

Bit 11: Pipe 3 Interrupt Disable.

PEP_4

Bit 12: Pipe 4 Interrupt Disable.

PEP_5

Bit 13: Pipe 5 Interrupt Disable.

PEP_6

Bit 14: Pipe 6 Interrupt Disable.

PEP_7

Bit 15: Pipe 7 Interrupt Disable.

PEP_8

Bit 16: Pipe 8 Interrupt Disable.

PEP_9

Bit 17: Pipe 9 Interrupt Disable.

DMA_1

Bit 25: DMA Channel 1 Interrupt Disable.

DMA_2

Bit 26: DMA Channel 2 Interrupt Disable.

DMA_3

Bit 27: DMA Channel 3 Interrupt Disable.

DMA_4

Bit 28: DMA Channel 4 Interrupt Disable.

DMA_5

Bit 29: DMA Channel 5 Interrupt Disable.

DMA_6

Bit 30: DMA Channel 6 Interrupt Disable.

HSTIER

Host Global Interrupt Enable Register

Offset: 0x418, reset: None, access: write-only

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_6
w 		DMA_5
w 		DMA_4
w 		DMA_3
w 		DMA_2
w 		DMA_1
w 		PEP_9
w 		PEP_8
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEP_7
w 		PEP_6
w 		PEP_5
w 		PEP_4
w 		PEP_3
w 		PEP_2
w 		PEP_1
w 		PEP_0
w 		HWUPIES
w 		HSOFIES
w 		RXRSMIES
w 		RSMEDIES
w 		RSTIES
w 		DDISCIES
w 		DCONNIES
w
Toggle Fields

DCONNIES

Bit 0: Device Connection Interrupt Enable.

DDISCIES

Bit 1: Device Disconnection Interrupt Enable.

RSTIES

Bit 2: USB Reset Sent Interrupt Enable.

RSMEDIES

Bit 3: Downstream Resume Sent Interrupt Enable.

RXRSMIES

Bit 4: Upstream Resume Received Interrupt Enable.

HSOFIES

Bit 5: Host Start of Frame Interrupt Enable.

HWUPIES

Bit 6: Host Wake-Up Interrupt Enable.

PEP_0

Bit 8: Pipe 0 Interrupt Enable.

PEP_1

Bit 9: Pipe 1 Interrupt Enable.

PEP_2

Bit 10: Pipe 2 Interrupt Enable.

PEP_3

Bit 11: Pipe 3 Interrupt Enable.

PEP_4

Bit 12: Pipe 4 Interrupt Enable.

PEP_5

Bit 13: Pipe 5 Interrupt Enable.

PEP_6

Bit 14: Pipe 6 Interrupt Enable.

PEP_7

Bit 15: Pipe 7 Interrupt Enable.

PEP_8

Bit 16: Pipe 8 Interrupt Enable.

PEP_9

Bit 17: Pipe 9 Interrupt Enable.

DMA_1

Bit 25: DMA Channel 1 Interrupt Enable.

DMA_2

Bit 26: DMA Channel 2 Interrupt Enable.

DMA_3

Bit 27: DMA Channel 3 Interrupt Enable.

DMA_4

Bit 28: DMA Channel 4 Interrupt Enable.

DMA_5

Bit 29: DMA Channel 5 Interrupt Enable.

DMA_6

Bit 30: DMA Channel 6 Interrupt Enable.

HSTPIP

Host Pipe Register

Offset: 0x41c, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRST8
rw 		PRST7
rw 		PRST6
rw 		PRST5
rw 		PRST4
rw 		PRST3
rw 		PRST2
rw 		PRST1
rw 		PRST0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEN8
rw 		PEN7
rw 		PEN6
rw 		PEN5
rw 		PEN4
rw 		PEN3
rw 		PEN2
rw 		PEN1
rw 		PEN0
rw
Toggle Fields

PEN0

Bit 0: Pipe 0 Enable.

PEN1

Bit 1: Pipe 1 Enable.

PEN2

Bit 2: Pipe 2 Enable.

PEN3

Bit 3: Pipe 3 Enable.

PEN4

Bit 4: Pipe 4 Enable.

PEN5

Bit 5: Pipe 5 Enable.

PEN6

Bit 6: Pipe 6 Enable.

PEN7

Bit 7: Pipe 7 Enable.

PEN8

Bit 8: Pipe 8 Enable.

PRST0

Bit 16: Pipe 0 Reset.

PRST1

Bit 17: Pipe 1 Reset.

PRST2

Bit 18: Pipe 2 Reset.

PRST3

Bit 19: Pipe 3 Reset.

PRST4

Bit 20: Pipe 4 Reset.

PRST5

Bit 21: Pipe 5 Reset.

PRST6

Bit 22: Pipe 6 Reset.

PRST7

Bit 23: Pipe 7 Reset.

PRST8

Bit 24: Pipe 8 Reset.

HSTFNUM

Host Frame Number Register

Offset: 0x420, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLENHIGH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNUM
rw 		MFNUM
rw
Toggle Fields

MFNUM

Bits 0-2: Micro Frame Number.

FNUM

Bits 3-13: Frame Number.

FLENHIGH

Bits 16-23: Frame Length.

HSTADDR1

Host Address 1 Register

Offset: 0x424, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSTADDRP3
rw 		HSTADDRP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSTADDRP1
rw 		HSTADDRP0
rw
Toggle Fields

HSTADDRP0

Bits 0-6: USB Host Address.

HSTADDRP1

Bits 8-14: USB Host Address.

HSTADDRP2

Bits 16-22: USB Host Address.

HSTADDRP3

Bits 24-30: USB Host Address.

HSTADDR2

Host Address 2 Register

Offset: 0x428, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSTADDRP7
rw 		HSTADDRP6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSTADDRP5
rw 		HSTADDRP4
rw
Toggle Fields

HSTADDRP4

Bits 0-6: USB Host Address.

HSTADDRP5

Bits 8-14: USB Host Address.

HSTADDRP6

Bits 16-22: USB Host Address.

HSTADDRP7

Bits 24-30: USB Host Address.

HSTADDR3

Host Address 3 Register

Offset: 0x42c, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSTADDRP9
rw 		HSTADDRP8
rw
Toggle Fields

HSTADDRP8

Bits 0-6: USB Host Address.

HSTADDRP9

Bits 8-14: USB Host Address.

HSTPIPCFG0_HSBOHSCP

Host Pipe Configuration Register (n = 0)

Offset: 0x500, reset: None, access: read-write

4/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BINTERVAL
rw 		PINGEN
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x2: BLK: Bulk

PEPNUM

Bits 16-19: Pipe Endpoint Number.

PINGEN

Bit 20: Ping Enable.

BINTERVAL

Bits 24-31: Binterval Parameter for the Bulk-Out/Ping Transaction.

HSTPIPCFG[[0]]

Host Pipe Configuration Register (n = 0)

Offset: 0x500, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[1]]

Host Pipe Configuration Register (n = 0)

Offset: 0x504, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[2]]

Host Pipe Configuration Register (n = 0)

Offset: 0x508, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[3]]

Host Pipe Configuration Register (n = 0)

Offset: 0x50c, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[4]]

Host Pipe Configuration Register (n = 0)

Offset: 0x510, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[5]]

Host Pipe Configuration Register (n = 0)

Offset: 0x514, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[6]]

Host Pipe Configuration Register (n = 0)

Offset: 0x518, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[7]]

Host Pipe Configuration Register (n = 0)

Offset: 0x51c, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[8]]

Host Pipe Configuration Register (n = 0)

Offset: 0x520, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPCFG[[9]]

Host Pipe Configuration Register (n = 0)

Offset: 0x524, reset: None, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTFRQ
rw 		PEPNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTYPE
rw 		AUTOSW
rw 		PTOKEN
rw 		PSIZE
rw 		PBK
rw 		ALLOC
rw
Toggle Fields

ALLOC

Bit 1: Pipe Memory Allocate.

PBK

Bits 2-3: Pipe Banks.

Allowed values:
0x0: 1_BANK: Single-bank pipe
0x1: 2_BANK: Double-bank pipe
0x2: 3_BANK: Triple-bank pipe

PSIZE

Bits 4-6: Pipe Size.

Allowed values:
0x0: 8_BYTE: 8 bytes
0x1: 16_BYTE: 16 bytes
0x2: 32_BYTE: 32 bytes
0x3: 64_BYTE: 64 bytes
0x4: 128_BYTE: 128 bytes
0x5: 256_BYTE: 256 bytes
0x6: 512_BYTE: 512 bytes
0x7: 1024_BYTE: 1024 bytes

PTOKEN

Bits 8-9: Pipe Token.

Allowed values:
0x0: SETUP: SETUP
0x1: IN: IN
0x2: OUT: OUT

AUTOSW

Bit 10: Automatic Switch.

PTYPE

Bits 12-13: Pipe Type.

Allowed values:
0x0: CTRL: Control
0x1: ISO: Isochronous
0x2: BLK: Bulk
0x3: INTRPT: Interrupt

PEPNUM

Bits 16-19: Pipe Endpoint Number.

INTFRQ

Bits 24-31: Pipe Interrupt Request Frequency.

HSTPIPISR0_INTPIPES

Host Pipe Status Register (n = 0)

Offset: 0x530, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		UNDERFI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

UNDERFI

Bit 2: Underflow Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR0_ISOPIPES

Host Pipe Status Register (n = 0)

Offset: 0x530, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		CRCERRI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		UNDERFI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

UNDERFI

Bit 2: Underflow Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

CRCERRI

Bit 6: CRC Error Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[0]]

Host Pipe Status Register (n = 0)

Offset: 0x530, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[1]]

Host Pipe Status Register (n = 0)

Offset: 0x534, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[2]]

Host Pipe Status Register (n = 0)

Offset: 0x538, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[3]]

Host Pipe Status Register (n = 0)

Offset: 0x53c, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[4]]

Host Pipe Status Register (n = 0)

Offset: 0x540, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[5]]

Host Pipe Status Register (n = 0)

Offset: 0x544, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[6]]

Host Pipe Status Register (n = 0)

Offset: 0x548, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[7]]

Host Pipe Status Register (n = 0)

Offset: 0x54c, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[8]]

Host Pipe Status Register (n = 0)

Offset: 0x550, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPISR[[9]]

Host Pipe Status Register (n = 0)

Offset: 0x554, reset: None, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBYCT
r 		CFGOK
r 		RWALL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBK
r 		NBUSYBK
r 		DTSEQ
r 		SHORTPACKETI
r 		RXSTALLDI
r 		OVERFI
r 		NAKEDI
r 		PERRI
r 		TXSTPI
r 		TXOUTI
r 		RXINI
r
Toggle Fields

RXINI

Bit 0: Received IN Data Interrupt.

TXOUTI

Bit 1: Transmitted OUT Data Interrupt.

TXSTPI

Bit 2: Transmitted SETUP Interrupt.

PERRI

Bit 3: Pipe Error Interrupt.

NAKEDI

Bit 4: NAKed Interrupt.

OVERFI

Bit 5: Overflow Interrupt.

RXSTALLDI

Bit 6: Received STALLed Interrupt.

SHORTPACKETI

Bit 7: Short Packet Interrupt.

DTSEQ

Bits 8-9: Data Toggle Sequence.

Allowed values:
0: DATA0: Data0 toggle sequence
1: DATA1: Data1 toggle sequence

NBUSYBK

Bits 12-13: Number of Busy Banks.

Allowed values:
0x0: 0_BUSY: 0 busy bank (all banks free)
0x1: 1_BUSY: 1 busy bank
0x2: 2_BUSY: 2 busy banks
0x3: 3_BUSY: 3 busy banks

CURRBK

Bits 14-15: Current Bank.

Allowed values:
0x0: BANK0: Current bank is bank0
0x1: BANK1: Current bank is bank1
0x2: BANK2: Current bank is bank2

RWALL

Bit 16: Read-write Allowed.

CFGOK

Bit 18: Configuration OK Status.

PBYCT

Bits 20-30: Pipe Byte Count.

HSTPIPICR0_INTPIPES

Host Pipe Clear Register (n = 0)

Offset: 0x560, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		UNDERFIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

UNDERFIC

Bit 2: Underflow Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR0_ISOPIPES

Host Pipe Clear Register (n = 0)

Offset: 0x560, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		CRCERRIC
w 		OVERFIC
w 		NAKEDIC
w 		UNDERFIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

UNDERFIC

Bit 2: Underflow Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

CRCERRIC

Bit 6: CRC Error Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[0]]

Host Pipe Clear Register (n = 0)

Offset: 0x560, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[1]]

Host Pipe Clear Register (n = 0)

Offset: 0x564, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[2]]

Host Pipe Clear Register (n = 0)

Offset: 0x568, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[3]]

Host Pipe Clear Register (n = 0)

Offset: 0x56c, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[4]]

Host Pipe Clear Register (n = 0)

Offset: 0x570, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[5]]

Host Pipe Clear Register (n = 0)

Offset: 0x574, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[6]]

Host Pipe Clear Register (n = 0)

Offset: 0x578, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[7]]

Host Pipe Clear Register (n = 0)

Offset: 0x57c, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[8]]

Host Pipe Clear Register (n = 0)

Offset: 0x580, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPICR[[9]]

Host Pipe Clear Register (n = 0)

Offset: 0x584, reset: None, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHORTPACKETIC
w 		RXSTALLDIC
w 		OVERFIC
w 		NAKEDIC
w 		TXSTPIC
w 		TXOUTIC
w 		RXINIC
w
Toggle Fields

RXINIC

Bit 0: Received IN Data Interrupt Clear.

TXOUTIC

Bit 1: Transmitted OUT Data Interrupt Clear.

TXSTPIC

Bit 2: Transmitted SETUP Interrupt Clear.

NAKEDIC

Bit 4: NAKed Interrupt Clear.

OVERFIC

Bit 5: Overflow Interrupt Clear.

RXSTALLDIC

Bit 6: Received STALLed Interrupt Clear.

SHORTPACKETIC

Bit 7: Short Packet Interrupt Clear.

HSTPIPIFR0_INTPIPES

Host Pipe Set Register (n = 0)

Offset: 0x590, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		UNDERFIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

UNDERFIS

Bit 2: Underflow Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR0_ISOPIPES

Host Pipe Set Register (n = 0)

Offset: 0x590, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		CRCERRIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		UNDERFIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

UNDERFIS

Bit 2: Underflow Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

CRCERRIS

Bit 6: CRC Error Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[0]]

Host Pipe Set Register (n = 0)

Offset: 0x590, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[1]]

Host Pipe Set Register (n = 0)

Offset: 0x594, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[2]]

Host Pipe Set Register (n = 0)

Offset: 0x598, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[3]]

Host Pipe Set Register (n = 0)

Offset: 0x59c, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[4]]

Host Pipe Set Register (n = 0)

Offset: 0x5a0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[5]]

Host Pipe Set Register (n = 0)

Offset: 0x5a4, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[6]]

Host Pipe Set Register (n = 0)

Offset: 0x5a8, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[7]]

Host Pipe Set Register (n = 0)

Offset: 0x5ac, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[8]]

Host Pipe Set Register (n = 0)

Offset: 0x5b0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIFR[[9]]

Host Pipe Set Register (n = 0)

Offset: 0x5b4, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKS
w 		SHORTPACKETIS
w 		RXSTALLDIS
w 		OVERFIS
w 		NAKEDIS
w 		PERRIS
w 		TXSTPIS
w 		TXOUTIS
w 		RXINIS
w
Toggle Fields

RXINIS

Bit 0: Received IN Data Interrupt Set.

TXOUTIS

Bit 1: Transmitted OUT Data Interrupt Set.

TXSTPIS

Bit 2: Transmitted SETUP Interrupt Set.

PERRIS

Bit 3: Pipe Error Interrupt Set.

NAKEDIS

Bit 4: NAKed Interrupt Set.

OVERFIS

Bit 5: Overflow Interrupt Set.

RXSTALLDIS

Bit 6: Received STALLed Interrupt Set.

SHORTPACKETIS

Bit 7: Short Packet Interrupt Set.

NBUSYBKS

Bit 12: Number of Busy Banks Set.

HSTPIPIMR0_INTPIPES

Host Pipe Mask Register (n = 0)

Offset: 0x5c0, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		UNDERFIE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

UNDERFIE

Bit 2: Underflow Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR0_ISOPIPES

Host Pipe Mask Register (n = 0)

Offset: 0x5c0, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		CRCERRE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		UNDERFIE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

UNDERFIE

Bit 2: Underflow Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

CRCERRE

Bit 6: CRC Error Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[0]]

Host Pipe Mask Register (n = 0)

Offset: 0x5c0, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[1]]

Host Pipe Mask Register (n = 0)

Offset: 0x5c4, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[2]]

Host Pipe Mask Register (n = 0)

Offset: 0x5c8, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[3]]

Host Pipe Mask Register (n = 0)

Offset: 0x5cc, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[4]]

Host Pipe Mask Register (n = 0)

Offset: 0x5d0, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[5]]

Host Pipe Mask Register (n = 0)

Offset: 0x5d4, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[6]]

Host Pipe Mask Register (n = 0)

Offset: 0x5d8, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[7]]

Host Pipe Mask Register (n = 0)

Offset: 0x5dc, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[8]]

Host Pipe Mask Register (n = 0)

Offset: 0x5e0, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIMR[[9]]

Host Pipe Mask Register (n = 0)

Offset: 0x5e4, reset: None, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDT
r 		PFREEZE
r 		PDISHDMA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCON
r 		NBUSYBKE
r 		SHORTPACKETIE
r 		RXSTALLDE
r 		OVERFIE
r 		NAKEDE
r 		PERRE
r 		TXSTPE
r 		TXOUTE
r 		RXINE
r
Toggle Fields

RXINE

Bit 0: Received IN Data Interrupt Enable.

TXOUTE

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPE

Bit 2: Transmitted SETUP Interrupt Enable.

PERRE

Bit 3: Pipe Error Interrupt Enable.

NAKEDE

Bit 4: NAKed Interrupt Enable.

OVERFIE

Bit 5: Overflow Interrupt Enable.

RXSTALLDE

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIE

Bit 7: Short Packet Interrupt Enable.

NBUSYBKE

Bit 12: Number of Busy Banks Interrupt Enable.

FIFOCON

Bit 14: FIFO Control.

PDISHDMA

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZE

Bit 17: Pipe Freeze.

RSTDT

Bit 18: Reset Data Toggle.

HSTPIPIER0_INTPIPES

Host Pipe Enable Register (n = 0)

Offset: 0x5f0, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		UNDERFIES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

UNDERFIES

Bit 2: Underflow Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER0_ISOPIPES

Host Pipe Enable Register (n = 0)

Offset: 0x5f0, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		CRCERRES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		UNDERFIES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

UNDERFIES

Bit 2: Underflow Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

CRCERRES

Bit 6: CRC Error Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[0]]

Host Pipe Enable Register (n = 0)

Offset: 0x5f0, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[1]]

Host Pipe Enable Register (n = 0)

Offset: 0x5f4, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[2]]

Host Pipe Enable Register (n = 0)

Offset: 0x5f8, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[3]]

Host Pipe Enable Register (n = 0)

Offset: 0x5fc, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[4]]

Host Pipe Enable Register (n = 0)

Offset: 0x600, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[5]]

Host Pipe Enable Register (n = 0)

Offset: 0x604, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[6]]

Host Pipe Enable Register (n = 0)

Offset: 0x608, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[7]]

Host Pipe Enable Register (n = 0)

Offset: 0x60c, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[8]]

Host Pipe Enable Register (n = 0)

Offset: 0x610, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIER[[9]]

Host Pipe Enable Register (n = 0)

Offset: 0x614, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSTDTS
w 		PFREEZES
w 		PDISHDMAS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBUSYBKES
w 		SHORTPACKETIES
w 		RXSTALLDES
w 		OVERFIES
w 		NAKEDES
w 		PERRES
w 		TXSTPES
w 		TXOUTES
w 		RXINES
w
Toggle Fields

RXINES

Bit 0: Received IN Data Interrupt Enable.

TXOUTES

Bit 1: Transmitted OUT Data Interrupt Enable.

TXSTPES

Bit 2: Transmitted SETUP Interrupt Enable.

PERRES

Bit 3: Pipe Error Interrupt Enable.

NAKEDES

Bit 4: NAKed Interrupt Enable.

OVERFIES

Bit 5: Overflow Interrupt Enable.

RXSTALLDES

Bit 6: Received STALLed Interrupt Enable.

SHORTPACKETIES

Bit 7: Short Packet Interrupt Enable.

NBUSYBKES

Bit 12: Number of Busy Banks Enable.

PDISHDMAS

Bit 16: Pipe Interrupts Disable HDMA Request Enable.

PFREEZES

Bit 17: Pipe Freeze Enable.

RSTDTS

Bit 18: Reset Data Toggle Enable.

HSTPIPIDR0_INTPIPES

Host Pipe Disable Register (n = 0)

Offset: 0x620, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		UNDERFIEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

UNDERFIEC

Bit 2: Underflow Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR0_ISOPIPES

Host Pipe Disable Register (n = 0)

Offset: 0x620, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		CRCERREC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		UNDERFIEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

UNDERFIEC

Bit 2: Underflow Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

CRCERREC

Bit 6: CRC Error Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[0]]

Host Pipe Disable Register (n = 0)

Offset: 0x620, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[1]]

Host Pipe Disable Register (n = 0)

Offset: 0x624, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[2]]

Host Pipe Disable Register (n = 0)

Offset: 0x628, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[3]]

Host Pipe Disable Register (n = 0)

Offset: 0x62c, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[4]]

Host Pipe Disable Register (n = 0)

Offset: 0x630, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[5]]

Host Pipe Disable Register (n = 0)

Offset: 0x634, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[6]]

Host Pipe Disable Register (n = 0)

Offset: 0x638, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[7]]

Host Pipe Disable Register (n = 0)

Offset: 0x63c, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[8]]

Host Pipe Disable Register (n = 0)

Offset: 0x640, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPIDR[[9]]

Host Pipe Disable Register (n = 0)

Offset: 0x644, reset: None, access: write-only

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFREEZEC
w 		PDISHDMAC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCONC
w 		NBUSYBKEC
w 		SHORTPACKETIEC
w 		RXSTALLDEC
w 		OVERFIEC
w 		NAKEDEC
w 		PERREC
w 		TXSTPEC
w 		TXOUTEC
w 		RXINEC
w
Toggle Fields

RXINEC

Bit 0: Received IN Data Interrupt Disable.

TXOUTEC

Bit 1: Transmitted OUT Data Interrupt Disable.

TXSTPEC

Bit 2: Transmitted SETUP Interrupt Disable.

PERREC

Bit 3: Pipe Error Interrupt Disable.

NAKEDEC

Bit 4: NAKed Interrupt Disable.

OVERFIEC

Bit 5: Overflow Interrupt Disable.

RXSTALLDEC

Bit 6: Received STALLed Interrupt Disable.

SHORTPACKETIEC

Bit 7: Short Packet Interrupt Disable.

NBUSYBKEC

Bit 12: Number of Busy Banks Disable.

FIFOCONC

Bit 14: FIFO Control Disable.

PDISHDMAC

Bit 16: Pipe Interrupts Disable HDMA Request Disable.

PFREEZEC

Bit 17: Pipe Freeze Disable.

HSTPIPINRQ[[0]]

Host Pipe IN Request Register (n = 0)

Offset: 0x650, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[1]]

Host Pipe IN Request Register (n = 0)

Offset: 0x654, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[2]]

Host Pipe IN Request Register (n = 0)

Offset: 0x658, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[3]]

Host Pipe IN Request Register (n = 0)

Offset: 0x65c, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[4]]

Host Pipe IN Request Register (n = 0)

Offset: 0x660, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[5]]

Host Pipe IN Request Register (n = 0)

Offset: 0x664, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[6]]

Host Pipe IN Request Register (n = 0)

Offset: 0x668, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[7]]

Host Pipe IN Request Register (n = 0)

Offset: 0x66c, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[8]]

Host Pipe IN Request Register (n = 0)

Offset: 0x670, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPINRQ[[9]]

Host Pipe IN Request Register (n = 0)

Offset: 0x674, reset: None, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INMODE
rw 		INRQ
rw
Toggle Fields

INRQ

Bits 0-7: IN Request Number before Freeze.

INMODE

Bit 8: IN Request Mode.

HSTPIPERR[[0]]

Host Pipe Error Register (n = 0)

Offset: 0x680, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[1]]

Host Pipe Error Register (n = 0)

Offset: 0x684, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[2]]

Host Pipe Error Register (n = 0)

Offset: 0x688, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[3]]

Host Pipe Error Register (n = 0)

Offset: 0x68c, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[4]]

Host Pipe Error Register (n = 0)

Offset: 0x690, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[5]]

Host Pipe Error Register (n = 0)

Offset: 0x694, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[6]]

Host Pipe Error Register (n = 0)

Offset: 0x698, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[7]]

Host Pipe Error Register (n = 0)

Offset: 0x69c, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[8]]

Host Pipe Error Register (n = 0)

Offset: 0x6a0, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTPIPERR[[9]]

Host Pipe Error Register (n = 0)

Offset: 0x6a4, reset: None, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTER
rw 		CRC16
rw 		TIMEOUT
rw 		PID
rw 		DATAPID
rw 		DATATGL
rw
Toggle Fields

DATATGL

Bit 0: Data Toggle Error.

DATAPID

Bit 1: Data PID Error.

PID

Bit 2: PID Error.

TIMEOUT

Bit 3: Time-Out Error.

CRC16

Bit 4: CRC16 Error.

COUNTER

Bits 5-6: Error Counter.

HSTDMANXTDSC1

Host DMA Channel Next Descriptor Address Register (n = 1)

Offset: 0x710, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

HSTDMAADDRESS1

Host DMA Channel Address Register (n = 1)

Offset: 0x714, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

HSTDMACONTROL1

Host DMA Channel Control Register (n = 1)

Offset: 0x718, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable (Control).

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

HSTDMASTATUS1

Host DMA Channel Status Register (n = 1)

Offset: 0x71c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

HSTDMANXTDSC2

Host DMA Channel Next Descriptor Address Register (n = 2)

Offset: 0x720, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

HSTDMAADDRESS2

Host DMA Channel Address Register (n = 2)

Offset: 0x724, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

HSTDMACONTROL2

Host DMA Channel Control Register (n = 2)

Offset: 0x728, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable (Control).

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

HSTDMASTATUS2

Host DMA Channel Status Register (n = 2)

Offset: 0x72c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

HSTDMANXTDSC3

Host DMA Channel Next Descriptor Address Register (n = 3)

Offset: 0x730, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

HSTDMAADDRESS3

Host DMA Channel Address Register (n = 3)

Offset: 0x734, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

HSTDMACONTROL3

Host DMA Channel Control Register (n = 3)

Offset: 0x738, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable (Control).

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

HSTDMASTATUS3

Host DMA Channel Status Register (n = 3)

Offset: 0x73c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

HSTDMANXTDSC4

Host DMA Channel Next Descriptor Address Register (n = 4)

Offset: 0x740, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

HSTDMAADDRESS4

Host DMA Channel Address Register (n = 4)

Offset: 0x744, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

HSTDMACONTROL4

Host DMA Channel Control Register (n = 4)

Offset: 0x748, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable (Control).

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

HSTDMASTATUS4

Host DMA Channel Status Register (n = 4)

Offset: 0x74c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

HSTDMANXTDSC5

Host DMA Channel Next Descriptor Address Register (n = 5)

Offset: 0x750, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

HSTDMAADDRESS5

Host DMA Channel Address Register (n = 5)

Offset: 0x754, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

HSTDMACONTROL5

Host DMA Channel Control Register (n = 5)

Offset: 0x758, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable (Control).

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

HSTDMASTATUS5

Host DMA Channel Status Register (n = 5)

Offset: 0x75c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

HSTDMANXTDSC6

Host DMA Channel Next Descriptor Address Register (n = 6)

Offset: 0x760, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

HSTDMAADDRESS6

Host DMA Channel Address Register (n = 6)

Offset: 0x764, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

HSTDMACONTROL6

Host DMA Channel Control Register (n = 6)

Offset: 0x768, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable (Control).

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

HSTDMASTATUS6

Host DMA Channel Status Register (n = 6)

Offset: 0x76c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

HSTDMANXTDSC7

Host DMA Channel Next Descriptor Address Register (n = 7)

Offset: 0x770, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NXT_DSC_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NXT_DSC_ADD
rw
Toggle Fields

NXT_DSC_ADD

Bits 0-31: Next Descriptor Address.

HSTDMAADDRESS7

Host DMA Channel Address Register (n = 7)

Offset: 0x774, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFF_ADD
rw
Toggle Fields

BUFF_ADD

Bits 0-31: Buffer Address.

HSTDMACONTROL7

Host DMA Channel Control Register (n = 7)

Offset: 0x778, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BURST_LCK
rw 		DESC_LD_IT
rw 		END_BUFFIT
rw 		END_TR_IT
rw 		END_B_EN
rw 		END_TR_EN
rw 		LDNXT_DSC
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Command.

LDNXT_DSC

Bit 1: Load Next Channel Transfer Descriptor Enable Command.

END_TR_EN

Bit 2: End of Transfer Enable (Control).

END_B_EN

Bit 3: End of Buffer Enable Control.

END_TR_IT

Bit 4: End of Transfer Interrupt Enable.

END_BUFFIT

Bit 5: End of Buffer Interrupt Enable.

DESC_LD_IT

Bit 6: Descriptor Loaded Interrupt Enable.

BURST_LCK

Bit 7: Burst Lock Enable.

BUFF_LENGTH

Bits 16-31: Buffer Byte Length (Write-only).

HSTDMASTATUS7

Host DMA Channel Status Register (n = 7)

Offset: 0x77c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUFF_COUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESC_LDST
rw 		END_BF_ST
rw 		END_TR_ST
rw 		CHANN_ACT
rw 		CHANN_ENB
rw
Toggle Fields

CHANN_ENB

Bit 0: Channel Enable Status.

CHANN_ACT

Bit 1: Channel Active Status.

END_TR_ST

Bit 4: End of Channel Transfer Status.

END_BF_ST

Bit 5: End of Channel Buffer Status.

DESC_LDST

Bit 6: Descriptor Loaded Status.

BUFF_COUNT

Bits 16-31: Buffer Byte Count.

CTRL

General Control Register

Offset: 0x800, reset: 0x03004000, access: read-write

2/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIMOD
rw 		UIDE
rw 		UNLOCK
rw 		TIMPAGE
rw 		TIMVALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBE
rw 		FRZCLK
rw 		VBUSPO
rw 		OTGPADE
rw 		HNPREQ
rw 		SRPREQ
rw 		SRPSEL
rw 		VBUSHWC
rw 		STOE
rw 		HNPERRE
rw 		ROLEEXE
rw 		BCERRE
rw 		VBERRE
rw 		SRPE
rw 		VBUSTE
rw 		IDTE
rw
Toggle Fields

IDTE

Bit 0: ID Transition Interrupt Enable.

VBUSTE

Bit 1: VBus Transition Interrupt Enable.

SRPE

Bit 2: SRP Interrupt Enable.

VBERRE

Bit 3: VBus Error Interrupt Enable.

BCERRE

Bit 4: B-Connection Error Interrupt Enable.

ROLEEXE

Bit 5: Role Exchange Interrupt Enable.

HNPERRE

Bit 6: HNP Error Interrupt Enable.

STOE

Bit 7: Suspend Time-Out Interrupt Enable.

VBUSHWC

Bit 8: VBus Hardware Control.

SRPSEL

Bit 9: SRP Selection.

SRPREQ

Bit 10: SRP Request.

HNPREQ

Bit 11: HNP Request.

OTGPADE

Bit 12: OTG Pad Enable.

VBUSPO

Bit 13: VBus Polarity Off.

FRZCLK

Bit 14: Freeze USB Clock.

USBE

Bit 15: UOTGHS Enable.

TIMVALUE

Bits 16-17: Timer Value.

TIMPAGE

Bits 20-21: Timer Page.

UNLOCK

Bit 22: Timer Access Unlock.

UIDE

Bit 24: UOTGID Pin Enable.

Allowed values:
0: UIMOD: The USB mode (device/host) is selected from the UIMOD bit.
1: UOTGID: The USB mode (device/host) is selected from the UOTGID input pin.

UIMOD

Bit 25: UOTGHS Mode.

Allowed values:
0: HOST: The module is in USB host mode.
1: DEVICE: The module is in USB device mode.

SR

General Status Register

Offset: 0x804, reset: 0x00000400, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKUSABLE
r 		SPEED
r 		VBUS
r 		ID
r 		VBUSRQ
r 		STOI
r 		HNPERRI
r 		ROLEEXI
r 		BCERRI
r 		VBERRI
r 		SRPI
r 		VBUSTI
r 		IDTI
r
Toggle Fields

IDTI

Bit 0: ID Transition Interrupt.

VBUSTI

Bit 1: VBus Transition Interrupt.

SRPI

Bit 2: SRP Interrupt.

VBERRI

Bit 3: VBus Error Interrupt.

BCERRI

Bit 4: B-Connection Error Interrupt.

ROLEEXI

Bit 5: Role Exchange Interrupt.

HNPERRI

Bit 6: HNP Error Interrupt.

STOI

Bit 7: Suspend Time-Out Interrupt.

VBUSRQ

Bit 9: VBus Request.

ID

Bit 10: UOTGID Pin State.

VBUS

Bit 11: VBus Level.

SPEED

Bits 12-13: Speed Status.

Allowed values:
0x0: FULL_SPEED: Full-Speed mode
0x1: HIGH_SPEED: High-Speed mode
0x2: LOW_SPEED: Low-Speed mode

CLKUSABLE

Bit 14: UTMI Clock Usable.

SCR

General Status Clear Register

Offset: 0x808, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSRQC
w 		STOIC
w 		HNPERRIC
w 		ROLEEXIC
w 		BCERRIC
w 		VBERRIC
w 		SRPIC
w 		VBUSTIC
w 		IDTIC
w
Toggle Fields

IDTIC

Bit 0: ID Transition Interrupt Clear.

VBUSTIC

Bit 1: VBus Transition Interrupt Clear.

SRPIC

Bit 2: SRP Interrupt Clear.

VBERRIC

Bit 3: VBus Error Interrupt Clear.

BCERRIC

Bit 4: B-Connection Error Interrupt Clear.

ROLEEXIC

Bit 5: Role Exchange Interrupt Clear.

HNPERRIC

Bit 6: HNP Error Interrupt Clear.

STOIC

Bit 7: Suspend Time-Out Interrupt Clear.

VBUSRQC

Bit 9: VBus Request Clear.

SFR

General Status Set Register

Offset: 0x80c, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSRQS
w 		STOIS
w 		HNPERRIS
w 		ROLEEXIS
w 		BCERRIS
w 		VBERRIS
w 		SRPIS
w 		VBUSTIS
w 		IDTIS
w
Toggle Fields

IDTIS

Bit 0: ID Transition Interrupt Set.

VBUSTIS

Bit 1: VBus Transition Interrupt Set.

SRPIS

Bit 2: SRP Interrupt Set.

VBERRIS

Bit 3: VBus Error Interrupt Set.

BCERRIS

Bit 4: B-Connection Error Interrupt Set.

ROLEEXIS

Bit 5: Role Exchange Interrupt Set.

HNPERRIS

Bit 6: HNP Error Interrupt Set.

STOIS

Bit 7: Suspend Time-Out Interrupt Set.

VBUSRQS

Bit 9: VBus Request Set.

FSM

General Finite State Machine Register

Offset: 0x82c, reset: 0x00000009, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRDSTATE
r
Toggle Fields

DRDSTATE

Bits 0-3: Dual Role Device State.

Allowed values:
0x0: A_IDLESTATE: This is the start state for A-devices (when the ID pin is 0)
0x1: A_WAIT_VRISE: In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V).
0x2: A_WAIT_BCON: In this state, the A-device waits for the B-device to signal a connection.
0x3: A_HOST: In this state, the A-device that operates in Host mode is operational.
0x4: A_SUSPEND: The A-device operating as a host is in the suspend mode.
0x5: A_PERIPHERAL: The A-device operates as a peripheral.
0x6: A_WAIT_VFALL: In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V).
0x7: A_VBUS_ERR: In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.
0x8: A_WAIT_DISCHARGE: In this state, the A-device waits for the data USB line to discharge (100 us).
0x9: B_IDLE: This is the start state for B-device (when the ID pin is 1).
0xA: B_PERIPHERAL: In this state, the B-device acts as the peripheral.
0xB: B_WAIT_BEGIN_HNP: In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested.
0xC: B_WAIT_DISCHARGE: In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host.
0xD: B_WAIT_ACON: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.
0xE: B_HOST: In this state, the B-device acts as the Host.
0xF: B_SRP_INIT: In this state, the B-device attempts to start a session using the SRP protocol.

USART0

0x40098000: Universal Synchronous Asynchronous Receiver Transmitter 0

112/280 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x0 CR_SPI_MODE
0x4 MR
0x4 MR_SPI_MODE
0x8 IER
0x8 IER_LIN_MODE
0x8 IER_SPI_MODE
0xc IDR
0xc IDR_LIN_MODE
0xc IDR_SPI_MODE
0x10 IMR
0x10 IMR_LIN_MODE
0x10 IMR_SPI_MODE
0x14 CSR
0x14 CSR_LIN_MODE
0x14 CSR_SPI_MODE
0x18 RHR
0x1c THR
0x20 BRGR
0x24 RTOR
0x28 TTGR
0x40 FIDI
0x44 NER
0x4c IF
0x50 MAN
0x54 LINMR
0x58 LINIR
0x5c LINBRR
0xe4 WPMR
0xe8 WPSR
0x100 RPR
0x104 RCR
0x108 TPR
0x10c TCR
0x110 RNPR
0x114 RNCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINWKUP
w 		LINABT
w 		RTSDIS
w 		RTSEN
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETTO
w 		RSTNACK
w 		RSTIT
w 		SENDA
w 		STTTO
w 		STPBRK
w 		STTBRK
w 		RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

STTBRK

Bit 9: Start Break.

STPBRK

Bit 10: Stop Break.

STTTO

Bit 11: Start Time-out.

SENDA

Bit 12: Send Address.

RSTIT

Bit 13: Reset Iterations.

RSTNACK

Bit 14: Reset Non Acknowledge.

RETTO

Bit 15: Rearm Time-out.

RTSEN

Bit 18: Request to Send Enable.

RTSDIS

Bit 19: Request to Send Disable.

LINABT

Bit 20: Abort LIN Transmission.

LINWKUP

Bit 21: Send LIN Wakeup Signal.

CR_SPI_MODE

Control Register

Offset: 0x0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCS
w 		FCS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

FCS

Bit 18: Force SPI Chip Select.

RCS

Bit 19: Release SPI Chip Select.

MR

Mode Register

Offset: 0x4, reset: None, access: read-write

6/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ONEBIT
rw 		MODSYNC
rw 		MAN
rw 		FILTER
rw 		MAX_ITERATION
rw 		INVDATA
rw 		VAR_SYNC
rw 		DSNACK
rw 		INACK
rw 		OVER
rw 		CLKO
rw 		MODE9
rw 		MSBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHMODE
rw 		NBSTOP
rw 		PAR
rw 		SYNC
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0x0: NORMAL: Normal mode
0x1: RS485: RS485
0x2: HW_HANDSHAKING: Hardware Handshaking
0x4: IS07816_T_0: IS07816 Protocol: T = 0
0x6: IS07816_T_1: IS07816 Protocol: T = 1
0x8: IRDA: IrDA
0xA: LIN_MASTER: LIN master
0xB: LIN_SLAVE: LIN Slave
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x0: 5_BIT: Character length is 5 bits
0x1: 6_BIT: Character length is 6 bits
0x2: 7_BIT: Character length is 7 bits
0x3: 8_BIT: Character length is 8 bits

SYNC

Bit 8: Synchronous Mode Select.

PAR

Bits 9-11: Parity Type.

Allowed values:
0x0: EVEN: Even parity
0x1: ODD: Odd parity
0x2: SPACE: Parity forced to 0 (Space)
0x3: MARK: Parity forced to 1 (Mark)
0x4: NO: No parity
0x6: MULTIDROP: Multidrop mode

NBSTOP

Bits 12-13: Number of Stop Bits.

Allowed values:
0x0: 1_BIT: 1 stop bit
0x1: 1_5_BIT: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x2: 2_BIT: 2 stop bits

CHMODE

Bits 14-15: Channel Mode.

Allowed values:
0x0: NORMAL: Normal mode
0x1: AUTOMATIC: Automatic Echo. Receiver input is connected to the TXD pin.
0x2: LOCAL_LOOPBACK: Local Loopback. Transmitter output is connected to the Receiver Input.
0x3: REMOTE_LOOPBACK: Remote Loopback. RXD pin is internally connected to the TXD pin.

MSBF

Bit 16: Bit Order.

MODE9

Bit 17: 9-bit Character Length.

CLKO

Bit 18: Clock Output Select.

OVER

Bit 19: Oversampling Mode.

INACK

Bit 20: Inhibit Non Acknowledge.

DSNACK

Bit 21: Disable Successive NACK.

VAR_SYNC

Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter.

INVDATA

Bit 23: Inverted Data.

MAX_ITERATION

Bits 24-26: Maximum Number of Automatic Iteration.

FILTER

Bit 28: Infrared Receive Line Filter.

MAN

Bit 29: Manchester Encoder/Decoder Enable.

MODSYNC

Bit 30: Manchester Synchronization Mode.

ONEBIT

Bit 31: Start Frame Delimiter Selector.

MR_SPI_MODE

Mode Register

Offset: 0x4, reset: None, access: read-write

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRDBT
rw 		CPOL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPHA
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x3: 8_BIT: Character length is 8 bits

CPHA

Bit 8: SPI Clock Phase.

CPOL

Bit 16: SPI Clock Polarity.

WRDBT

Bit 20: Wait Read Data Before Transfer.

IER

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

RXBRK

Bit 2: Receiver Break Interrupt Enable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Enable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Enable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

ITER

Bit 10: Max number of Repetitions Reached Interrupt Enable.

TXBUFE

Bit 11: Buffer Empty Interrupt Enable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Enable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Enable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Enable.

MANE

Bit 24: Manchester Error Interrupt Enable.

IER_LIN_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Enable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Enable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Enable.

LINBE

Bit 25: LIN Bus Error Interrupt Enable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Enable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Enable.

LINCE

Bit 28: LIN Checksum Error Interrupt Enable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Enable.

IER_SPI_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

UNRE

Bit 10: SPI Underrun Error Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IDR

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

RXBRK

Bit 2: Receiver Break Interrupt Disable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Disable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Disable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Disable.

TXBUFE

Bit 11: Buffer Empty Interrupt Disable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Disable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Disable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Disable.

MANE

Bit 24: Manchester Error Interrupt Disable.

IDR_LIN_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Disable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Disable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Disable.

LINBE

Bit 25: LIN Bus Error Interrupt Disable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Disable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Disable.

LINCE

Bit 28: LIN Checksum Error Interrupt Disable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Disable.

IDR_SPI_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

UNRE

Bit 10: SPI Underrun Error Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IMR

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

RXBRK

Bit 2: Receiver Break Interrupt Mask.

ENDRX

Bit 3: End of Receive Transfer Interrupt Mask (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Mask (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Mask.

TXBUFE

Bit 11: Buffer Empty Interrupt Mask (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Mask (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Mask.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Mask.

MANE

Bit 24: Manchester Error Interrupt Mask.

IMR_LIN_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Mask.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Mask.

LINTC

Bit 15: LIN Transfer Completed Interrupt Mask.

LINBE

Bit 25: LIN Bus Error Interrupt Mask.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Mask.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Mask.

LINCE

Bit 28: LIN Checksum Error Interrupt Mask.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Mask.

IMR_SPI_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

UNRE

Bit 10: SPI Underrun Error Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

CSR

Channel Status Register

Offset: 0x14, reset: None, access: read-only

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANERR
r 		CTS
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

RXBRK

Bit 2: Break Received/End of Break.

ENDRX

Bit 3: End of Receiver Transfer.

ENDTX

Bit 4: End of Transmitter Transfer.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

ITER

Bit 10: Max Number of Repetitions Reached.

TXBUFE

Bit 11: Transmission Buffer Empty.

RXBUFF

Bit 12: Reception Buffer Full.

NACK

Bit 13: Non Acknowledge Interrupt.

CTSIC

Bit 19: Clear to Send Input Change Flag.

CTS

Bit 23: Image of CTS Input.

MANERR

Bit 24: Manchester Error.

CSR_LIN_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r 		LINBLS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received.

LINTC

Bit 15: LIN Transfer Completed.

LINBLS

Bit 23: LIN Bus Line Status.

LINBE

Bit 25: LIN Bit Error.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error.

LINIPE

Bit 27: LIN Identifier Parity Error.

LINCE

Bit 28: LIN Checksum Error.

LINSNRE

Bit 29: LIN Slave Not Responding Error.

CSR_SPI_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

TXEMPTY

Bit 9: Transmitter Empty.

UNRE

Bit 10: Underrun Error.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

RHR

Receive Holding Register

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYNH
r 		RXCHR
r
Toggle Fields

RXCHR

Bits 0-8: Received Character.

RXSYNH

Bit 15: Received Sync.

THR

Transmit Holding Register

Offset: 0x1c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXSYNH
w 		TXCHR
w
Toggle Fields

TXCHR

Bits 0-8: Character to be Transmitted.

TXSYNH

Bit 15: Sync Field to be Transmitted.

BRGR

Baud Rate Generator Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
rw
Toggle Fields

CD

Bits 0-15: Clock Divider.

FP

Bits 16-18: Fractional Part.

RTOR

Receiver Time-out Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
rw
Toggle Fields

TO

Bits 0-16: Time-out Value.

TTGR

Transmitter Timeguard Register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw
Toggle Fields

TG

Bits 0-7: Timeguard Value.

FIDI

FI DI Ratio Register

Offset: 0x40, reset: 0x00000174, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI_DI_RATIO
rw
Toggle Fields

FI_DI_RATIO

Bits 0-10: FI Over DI Ratio Value.

NER

Number of Errors Register

Offset: 0x44, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NB_ERRORS
r
Toggle Fields

NB_ERRORS

Bits 0-7: Number of Errors.

IF

IrDA Filter Register

Offset: 0x4c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRDA_FILTER
rw
Toggle Fields

IRDA_FILTER

Bits 0-7: IrDA Filter.

MAN

Manchester Configuration Register

Offset: 0x50, reset: 0xB0011004, access: read-write

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRIFT
rw 		ONE
rw 		RX_MPOL
rw 		RX_PP
rw 		RX_PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_MPOL
rw 		TX_PP
rw 		TX_PL
rw
Toggle Fields

TX_PL

Bits 0-3: Transmitter Preamble Length.

TX_PP

Bits 8-9: Transmitter Preamble Pattern.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

TX_MPOL

Bit 12: Transmitter Manchester Polarity.

RX_PL

Bits 16-19: Receiver Preamble Length.

RX_PP

Bits 24-25: Receiver Preamble Pattern detected.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

RX_MPOL

Bit 28: Receiver Manchester Polarity.

ONE

Bit 29: Must Be Set to 1.

DRIFT

Bit 30: Drift Compensation.

LINMR

LIN Mode Register

Offset: 0x54, reset: 0x00000000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLC
rw 		WKUPTYP
rw 		FSDIS
rw 		DLM
rw 		CHKTYP
rw 		CHKDIS
rw 		PARDIS
rw 		NACT
rw
Toggle Fields

NACT

Bits 0-1: LIN Node Action.

Allowed values:
0x0: PUBLISH: The USART transmits the response.
0x1: SUBSCRIBE: The USART receives the response.
0x2: IGNORE: The USART does not transmit and does not receive the response.

PARDIS

Bit 2: Parity Disable.

CHKDIS

Bit 3: Checksum Disable.

CHKTYP

Bit 4: Checksum Type.

DLM

Bit 5: Data Length Mode.

FSDIS

Bit 6: Frame Slot Mode Disable.

WKUPTYP

Bit 7: Wakeup Signal Type.

DLC

Bits 8-15: Data Length Control.

PDCM

Bit 16: PDC Mode.

LINIR

LIN Identifier Register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDCHR
rw
Toggle Fields

IDCHR

Bits 0-7: Identifier Character.

LINBRR

LIN Baud Rate Register

Offset: 0x5c, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINFP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCD
r
Toggle Fields

LINCD

Bits 0-15: Clock Divider after Synchronization.

LINFP

Bits 16-18: Fractional Part after Synchronization.

WPMR

Write Protection Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protection Enable.

WPKEY

Bits 8-31: Write Protection Key.

Allowed values:
0x555341: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

WPSR

Write Protection Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-23: Write Protection Violation Source.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

USART1

0x4009c000: Universal Synchronous Asynchronous Receiver Transmitter 1

112/280 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x0 CR_SPI_MODE
0x4 MR
0x4 MR_SPI_MODE
0x8 IER
0x8 IER_LIN_MODE
0x8 IER_SPI_MODE
0xc IDR
0xc IDR_LIN_MODE
0xc IDR_SPI_MODE
0x10 IMR
0x10 IMR_LIN_MODE
0x10 IMR_SPI_MODE
0x14 CSR
0x14 CSR_LIN_MODE
0x14 CSR_SPI_MODE
0x18 RHR
0x1c THR
0x20 BRGR
0x24 RTOR
0x28 TTGR
0x40 FIDI
0x44 NER
0x4c IF
0x50 MAN
0x54 LINMR
0x58 LINIR
0x5c LINBRR
0xe4 WPMR
0xe8 WPSR
0x100 RPR
0x104 RCR
0x108 TPR
0x10c TCR
0x110 RNPR
0x114 RNCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINWKUP
w 		LINABT
w 		RTSDIS
w 		RTSEN
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETTO
w 		RSTNACK
w 		RSTIT
w 		SENDA
w 		STTTO
w 		STPBRK
w 		STTBRK
w 		RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

STTBRK

Bit 9: Start Break.

STPBRK

Bit 10: Stop Break.

STTTO

Bit 11: Start Time-out.

SENDA

Bit 12: Send Address.

RSTIT

Bit 13: Reset Iterations.

RSTNACK

Bit 14: Reset Non Acknowledge.

RETTO

Bit 15: Rearm Time-out.

RTSEN

Bit 18: Request to Send Enable.

RTSDIS

Bit 19: Request to Send Disable.

LINABT

Bit 20: Abort LIN Transmission.

LINWKUP

Bit 21: Send LIN Wakeup Signal.

CR_SPI_MODE

Control Register

Offset: 0x0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCS
w 		FCS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

FCS

Bit 18: Force SPI Chip Select.

RCS

Bit 19: Release SPI Chip Select.

MR

Mode Register

Offset: 0x4, reset: None, access: read-write

6/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ONEBIT
rw 		MODSYNC
rw 		MAN
rw 		FILTER
rw 		MAX_ITERATION
rw 		INVDATA
rw 		VAR_SYNC
rw 		DSNACK
rw 		INACK
rw 		OVER
rw 		CLKO
rw 		MODE9
rw 		MSBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHMODE
rw 		NBSTOP
rw 		PAR
rw 		SYNC
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0x0: NORMAL: Normal mode
0x1: RS485: RS485
0x2: HW_HANDSHAKING: Hardware Handshaking
0x4: IS07816_T_0: IS07816 Protocol: T = 0
0x6: IS07816_T_1: IS07816 Protocol: T = 1
0x8: IRDA: IrDA
0xA: LIN_MASTER: LIN master
0xB: LIN_SLAVE: LIN Slave
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x0: 5_BIT: Character length is 5 bits
0x1: 6_BIT: Character length is 6 bits
0x2: 7_BIT: Character length is 7 bits
0x3: 8_BIT: Character length is 8 bits

SYNC

Bit 8: Synchronous Mode Select.

PAR

Bits 9-11: Parity Type.

Allowed values:
0x0: EVEN: Even parity
0x1: ODD: Odd parity
0x2: SPACE: Parity forced to 0 (Space)
0x3: MARK: Parity forced to 1 (Mark)
0x4: NO: No parity
0x6: MULTIDROP: Multidrop mode

NBSTOP

Bits 12-13: Number of Stop Bits.

Allowed values:
0x0: 1_BIT: 1 stop bit
0x1: 1_5_BIT: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x2: 2_BIT: 2 stop bits

CHMODE

Bits 14-15: Channel Mode.

Allowed values:
0x0: NORMAL: Normal mode
0x1: AUTOMATIC: Automatic Echo. Receiver input is connected to the TXD pin.
0x2: LOCAL_LOOPBACK: Local Loopback. Transmitter output is connected to the Receiver Input.
0x3: REMOTE_LOOPBACK: Remote Loopback. RXD pin is internally connected to the TXD pin.

MSBF

Bit 16: Bit Order.

MODE9

Bit 17: 9-bit Character Length.

CLKO

Bit 18: Clock Output Select.

OVER

Bit 19: Oversampling Mode.

INACK

Bit 20: Inhibit Non Acknowledge.

DSNACK

Bit 21: Disable Successive NACK.

VAR_SYNC

Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter.

INVDATA

Bit 23: Inverted Data.

MAX_ITERATION

Bits 24-26: Maximum Number of Automatic Iteration.

FILTER

Bit 28: Infrared Receive Line Filter.

MAN

Bit 29: Manchester Encoder/Decoder Enable.

MODSYNC

Bit 30: Manchester Synchronization Mode.

ONEBIT

Bit 31: Start Frame Delimiter Selector.

MR_SPI_MODE

Mode Register

Offset: 0x4, reset: None, access: read-write

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRDBT
rw 		CPOL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPHA
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x3: 8_BIT: Character length is 8 bits

CPHA

Bit 8: SPI Clock Phase.

CPOL

Bit 16: SPI Clock Polarity.

WRDBT

Bit 20: Wait Read Data Before Transfer.

IER

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

RXBRK

Bit 2: Receiver Break Interrupt Enable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Enable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Enable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

ITER

Bit 10: Max number of Repetitions Reached Interrupt Enable.

TXBUFE

Bit 11: Buffer Empty Interrupt Enable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Enable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Enable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Enable.

MANE

Bit 24: Manchester Error Interrupt Enable.

IER_LIN_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Enable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Enable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Enable.

LINBE

Bit 25: LIN Bus Error Interrupt Enable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Enable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Enable.

LINCE

Bit 28: LIN Checksum Error Interrupt Enable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Enable.

IER_SPI_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

UNRE

Bit 10: SPI Underrun Error Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IDR

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

RXBRK

Bit 2: Receiver Break Interrupt Disable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Disable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Disable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Disable.

TXBUFE

Bit 11: Buffer Empty Interrupt Disable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Disable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Disable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Disable.

MANE

Bit 24: Manchester Error Interrupt Disable.

IDR_LIN_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Disable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Disable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Disable.

LINBE

Bit 25: LIN Bus Error Interrupt Disable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Disable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Disable.

LINCE

Bit 28: LIN Checksum Error Interrupt Disable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Disable.

IDR_SPI_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

UNRE

Bit 10: SPI Underrun Error Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IMR

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

RXBRK

Bit 2: Receiver Break Interrupt Mask.

ENDRX

Bit 3: End of Receive Transfer Interrupt Mask (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Mask (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Mask.

TXBUFE

Bit 11: Buffer Empty Interrupt Mask (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Mask (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Mask.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Mask.

MANE

Bit 24: Manchester Error Interrupt Mask.

IMR_LIN_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Mask.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Mask.

LINTC

Bit 15: LIN Transfer Completed Interrupt Mask.

LINBE

Bit 25: LIN Bus Error Interrupt Mask.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Mask.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Mask.

LINCE

Bit 28: LIN Checksum Error Interrupt Mask.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Mask.

IMR_SPI_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

UNRE

Bit 10: SPI Underrun Error Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

CSR

Channel Status Register

Offset: 0x14, reset: None, access: read-only

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANERR
r 		CTS
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

RXBRK

Bit 2: Break Received/End of Break.

ENDRX

Bit 3: End of Receiver Transfer.

ENDTX

Bit 4: End of Transmitter Transfer.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

ITER

Bit 10: Max Number of Repetitions Reached.

TXBUFE

Bit 11: Transmission Buffer Empty.

RXBUFF

Bit 12: Reception Buffer Full.

NACK

Bit 13: Non Acknowledge Interrupt.

CTSIC

Bit 19: Clear to Send Input Change Flag.

CTS

Bit 23: Image of CTS Input.

MANERR

Bit 24: Manchester Error.

CSR_LIN_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r 		LINBLS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received.

LINTC

Bit 15: LIN Transfer Completed.

LINBLS

Bit 23: LIN Bus Line Status.

LINBE

Bit 25: LIN Bit Error.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error.

LINIPE

Bit 27: LIN Identifier Parity Error.

LINCE

Bit 28: LIN Checksum Error.

LINSNRE

Bit 29: LIN Slave Not Responding Error.

CSR_SPI_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

TXEMPTY

Bit 9: Transmitter Empty.

UNRE

Bit 10: Underrun Error.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

RHR

Receive Holding Register

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYNH
r 		RXCHR
r
Toggle Fields

RXCHR

Bits 0-8: Received Character.

RXSYNH

Bit 15: Received Sync.

THR

Transmit Holding Register

Offset: 0x1c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXSYNH
w 		TXCHR
w
Toggle Fields

TXCHR

Bits 0-8: Character to be Transmitted.

TXSYNH

Bit 15: Sync Field to be Transmitted.

BRGR

Baud Rate Generator Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
rw
Toggle Fields

CD

Bits 0-15: Clock Divider.

FP

Bits 16-18: Fractional Part.

RTOR

Receiver Time-out Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
rw
Toggle Fields

TO

Bits 0-16: Time-out Value.

TTGR

Transmitter Timeguard Register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw
Toggle Fields

TG

Bits 0-7: Timeguard Value.

FIDI

FI DI Ratio Register

Offset: 0x40, reset: 0x00000174, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI_DI_RATIO
rw
Toggle Fields

FI_DI_RATIO

Bits 0-10: FI Over DI Ratio Value.

NER

Number of Errors Register

Offset: 0x44, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NB_ERRORS
r
Toggle Fields

NB_ERRORS

Bits 0-7: Number of Errors.

IF

IrDA Filter Register

Offset: 0x4c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRDA_FILTER
rw
Toggle Fields

IRDA_FILTER

Bits 0-7: IrDA Filter.

MAN

Manchester Configuration Register

Offset: 0x50, reset: 0xB0011004, access: read-write

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRIFT
rw 		ONE
rw 		RX_MPOL
rw 		RX_PP
rw 		RX_PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_MPOL
rw 		TX_PP
rw 		TX_PL
rw
Toggle Fields

TX_PL

Bits 0-3: Transmitter Preamble Length.

TX_PP

Bits 8-9: Transmitter Preamble Pattern.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

TX_MPOL

Bit 12: Transmitter Manchester Polarity.

RX_PL

Bits 16-19: Receiver Preamble Length.

RX_PP

Bits 24-25: Receiver Preamble Pattern detected.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

RX_MPOL

Bit 28: Receiver Manchester Polarity.

ONE

Bit 29: Must Be Set to 1.

DRIFT

Bit 30: Drift Compensation.

LINMR

LIN Mode Register

Offset: 0x54, reset: 0x00000000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLC
rw 		WKUPTYP
rw 		FSDIS
rw 		DLM
rw 		CHKTYP
rw 		CHKDIS
rw 		PARDIS
rw 		NACT
rw
Toggle Fields

NACT

Bits 0-1: LIN Node Action.

Allowed values:
0x0: PUBLISH: The USART transmits the response.
0x1: SUBSCRIBE: The USART receives the response.
0x2: IGNORE: The USART does not transmit and does not receive the response.

PARDIS

Bit 2: Parity Disable.

CHKDIS

Bit 3: Checksum Disable.

CHKTYP

Bit 4: Checksum Type.

DLM

Bit 5: Data Length Mode.

FSDIS

Bit 6: Frame Slot Mode Disable.

WKUPTYP

Bit 7: Wakeup Signal Type.

DLC

Bits 8-15: Data Length Control.

PDCM

Bit 16: PDC Mode.

LINIR

LIN Identifier Register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDCHR
rw
Toggle Fields

IDCHR

Bits 0-7: Identifier Character.

LINBRR

LIN Baud Rate Register

Offset: 0x5c, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINFP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCD
r
Toggle Fields

LINCD

Bits 0-15: Clock Divider after Synchronization.

LINFP

Bits 16-18: Fractional Part after Synchronization.

WPMR

Write Protection Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protection Enable.

WPKEY

Bits 8-31: Write Protection Key.

Allowed values:
0x555341: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

WPSR

Write Protection Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-23: Write Protection Violation Source.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

USART2

0x400a0000: Universal Synchronous Asynchronous Receiver Transmitter 2

112/280 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x0 CR_SPI_MODE
0x4 MR
0x4 MR_SPI_MODE
0x8 IER
0x8 IER_LIN_MODE
0x8 IER_SPI_MODE
0xc IDR
0xc IDR_LIN_MODE
0xc IDR_SPI_MODE
0x10 IMR
0x10 IMR_LIN_MODE
0x10 IMR_SPI_MODE
0x14 CSR
0x14 CSR_LIN_MODE
0x14 CSR_SPI_MODE
0x18 RHR
0x1c THR
0x20 BRGR
0x24 RTOR
0x28 TTGR
0x40 FIDI
0x44 NER
0x4c IF
0x50 MAN
0x54 LINMR
0x58 LINIR
0x5c LINBRR
0xe4 WPMR
0xe8 WPSR
0x100 RPR
0x104 RCR
0x108 TPR
0x10c TCR
0x110 RNPR
0x114 RNCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINWKUP
w 		LINABT
w 		RTSDIS
w 		RTSEN
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETTO
w 		RSTNACK
w 		RSTIT
w 		SENDA
w 		STTTO
w 		STPBRK
w 		STTBRK
w 		RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

STTBRK

Bit 9: Start Break.

STPBRK

Bit 10: Stop Break.

STTTO

Bit 11: Start Time-out.

SENDA

Bit 12: Send Address.

RSTIT

Bit 13: Reset Iterations.

RSTNACK

Bit 14: Reset Non Acknowledge.

RETTO

Bit 15: Rearm Time-out.

RTSEN

Bit 18: Request to Send Enable.

RTSDIS

Bit 19: Request to Send Disable.

LINABT

Bit 20: Abort LIN Transmission.

LINWKUP

Bit 21: Send LIN Wakeup Signal.

CR_SPI_MODE

Control Register

Offset: 0x0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCS
w 		FCS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

FCS

Bit 18: Force SPI Chip Select.

RCS

Bit 19: Release SPI Chip Select.

MR

Mode Register

Offset: 0x4, reset: None, access: read-write

6/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ONEBIT
rw 		MODSYNC
rw 		MAN
rw 		FILTER
rw 		MAX_ITERATION
rw 		INVDATA
rw 		VAR_SYNC
rw 		DSNACK
rw 		INACK
rw 		OVER
rw 		CLKO
rw 		MODE9
rw 		MSBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHMODE
rw 		NBSTOP
rw 		PAR
rw 		SYNC
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0x0: NORMAL: Normal mode
0x1: RS485: RS485
0x2: HW_HANDSHAKING: Hardware Handshaking
0x4: IS07816_T_0: IS07816 Protocol: T = 0
0x6: IS07816_T_1: IS07816 Protocol: T = 1
0x8: IRDA: IrDA
0xA: LIN_MASTER: LIN master
0xB: LIN_SLAVE: LIN Slave
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x0: 5_BIT: Character length is 5 bits
0x1: 6_BIT: Character length is 6 bits
0x2: 7_BIT: Character length is 7 bits
0x3: 8_BIT: Character length is 8 bits

SYNC

Bit 8: Synchronous Mode Select.

PAR

Bits 9-11: Parity Type.

Allowed values:
0x0: EVEN: Even parity
0x1: ODD: Odd parity
0x2: SPACE: Parity forced to 0 (Space)
0x3: MARK: Parity forced to 1 (Mark)
0x4: NO: No parity
0x6: MULTIDROP: Multidrop mode

NBSTOP

Bits 12-13: Number of Stop Bits.

Allowed values:
0x0: 1_BIT: 1 stop bit
0x1: 1_5_BIT: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x2: 2_BIT: 2 stop bits

CHMODE

Bits 14-15: Channel Mode.

Allowed values:
0x0: NORMAL: Normal mode
0x1: AUTOMATIC: Automatic Echo. Receiver input is connected to the TXD pin.
0x2: LOCAL_LOOPBACK: Local Loopback. Transmitter output is connected to the Receiver Input.
0x3: REMOTE_LOOPBACK: Remote Loopback. RXD pin is internally connected to the TXD pin.

MSBF

Bit 16: Bit Order.

MODE9

Bit 17: 9-bit Character Length.

CLKO

Bit 18: Clock Output Select.

OVER

Bit 19: Oversampling Mode.

INACK

Bit 20: Inhibit Non Acknowledge.

DSNACK

Bit 21: Disable Successive NACK.

VAR_SYNC

Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter.

INVDATA

Bit 23: Inverted Data.

MAX_ITERATION

Bits 24-26: Maximum Number of Automatic Iteration.

FILTER

Bit 28: Infrared Receive Line Filter.

MAN

Bit 29: Manchester Encoder/Decoder Enable.

MODSYNC

Bit 30: Manchester Synchronization Mode.

ONEBIT

Bit 31: Start Frame Delimiter Selector.

MR_SPI_MODE

Mode Register

Offset: 0x4, reset: None, access: read-write

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRDBT
rw 		CPOL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPHA
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x3: 8_BIT: Character length is 8 bits

CPHA

Bit 8: SPI Clock Phase.

CPOL

Bit 16: SPI Clock Polarity.

WRDBT

Bit 20: Wait Read Data Before Transfer.

IER

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

RXBRK

Bit 2: Receiver Break Interrupt Enable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Enable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Enable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

ITER

Bit 10: Max number of Repetitions Reached Interrupt Enable.

TXBUFE

Bit 11: Buffer Empty Interrupt Enable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Enable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Enable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Enable.

MANE

Bit 24: Manchester Error Interrupt Enable.

IER_LIN_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Enable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Enable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Enable.

LINBE

Bit 25: LIN Bus Error Interrupt Enable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Enable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Enable.

LINCE

Bit 28: LIN Checksum Error Interrupt Enable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Enable.

IER_SPI_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

UNRE

Bit 10: SPI Underrun Error Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IDR

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

RXBRK

Bit 2: Receiver Break Interrupt Disable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Disable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Disable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Disable.

TXBUFE

Bit 11: Buffer Empty Interrupt Disable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Disable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Disable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Disable.

MANE

Bit 24: Manchester Error Interrupt Disable.

IDR_LIN_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Disable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Disable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Disable.

LINBE

Bit 25: LIN Bus Error Interrupt Disable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Disable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Disable.

LINCE

Bit 28: LIN Checksum Error Interrupt Disable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Disable.

IDR_SPI_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

UNRE

Bit 10: SPI Underrun Error Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IMR

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

RXBRK

Bit 2: Receiver Break Interrupt Mask.

ENDRX

Bit 3: End of Receive Transfer Interrupt Mask (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Mask (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Mask.

TXBUFE

Bit 11: Buffer Empty Interrupt Mask (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Mask (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Mask.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Mask.

MANE

Bit 24: Manchester Error Interrupt Mask.

IMR_LIN_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Mask.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Mask.

LINTC

Bit 15: LIN Transfer Completed Interrupt Mask.

LINBE

Bit 25: LIN Bus Error Interrupt Mask.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Mask.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Mask.

LINCE

Bit 28: LIN Checksum Error Interrupt Mask.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Mask.

IMR_SPI_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

UNRE

Bit 10: SPI Underrun Error Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

CSR

Channel Status Register

Offset: 0x14, reset: None, access: read-only

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANERR
r 		CTS
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

RXBRK

Bit 2: Break Received/End of Break.

ENDRX

Bit 3: End of Receiver Transfer.

ENDTX

Bit 4: End of Transmitter Transfer.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

ITER

Bit 10: Max Number of Repetitions Reached.

TXBUFE

Bit 11: Transmission Buffer Empty.

RXBUFF

Bit 12: Reception Buffer Full.

NACK

Bit 13: Non Acknowledge Interrupt.

CTSIC

Bit 19: Clear to Send Input Change Flag.

CTS

Bit 23: Image of CTS Input.

MANERR

Bit 24: Manchester Error.

CSR_LIN_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r 		LINBLS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received.

LINTC

Bit 15: LIN Transfer Completed.

LINBLS

Bit 23: LIN Bus Line Status.

LINBE

Bit 25: LIN Bit Error.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error.

LINIPE

Bit 27: LIN Identifier Parity Error.

LINCE

Bit 28: LIN Checksum Error.

LINSNRE

Bit 29: LIN Slave Not Responding Error.

CSR_SPI_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

TXEMPTY

Bit 9: Transmitter Empty.

UNRE

Bit 10: Underrun Error.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

RHR

Receive Holding Register

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYNH
r 		RXCHR
r
Toggle Fields

RXCHR

Bits 0-8: Received Character.

RXSYNH

Bit 15: Received Sync.

THR

Transmit Holding Register

Offset: 0x1c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXSYNH
w 		TXCHR
w
Toggle Fields

TXCHR

Bits 0-8: Character to be Transmitted.

TXSYNH

Bit 15: Sync Field to be Transmitted.

BRGR

Baud Rate Generator Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
rw
Toggle Fields

CD

Bits 0-15: Clock Divider.

FP

Bits 16-18: Fractional Part.

RTOR

Receiver Time-out Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
rw
Toggle Fields

TO

Bits 0-16: Time-out Value.

TTGR

Transmitter Timeguard Register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw
Toggle Fields

TG

Bits 0-7: Timeguard Value.

FIDI

FI DI Ratio Register

Offset: 0x40, reset: 0x00000174, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI_DI_RATIO
rw
Toggle Fields

FI_DI_RATIO

Bits 0-10: FI Over DI Ratio Value.

NER

Number of Errors Register

Offset: 0x44, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NB_ERRORS
r
Toggle Fields

NB_ERRORS

Bits 0-7: Number of Errors.

IF

IrDA Filter Register

Offset: 0x4c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRDA_FILTER
rw
Toggle Fields

IRDA_FILTER

Bits 0-7: IrDA Filter.

MAN

Manchester Configuration Register

Offset: 0x50, reset: 0xB0011004, access: read-write

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRIFT
rw 		ONE
rw 		RX_MPOL
rw 		RX_PP
rw 		RX_PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_MPOL
rw 		TX_PP
rw 		TX_PL
rw
Toggle Fields

TX_PL

Bits 0-3: Transmitter Preamble Length.

TX_PP

Bits 8-9: Transmitter Preamble Pattern.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

TX_MPOL

Bit 12: Transmitter Manchester Polarity.

RX_PL

Bits 16-19: Receiver Preamble Length.

RX_PP

Bits 24-25: Receiver Preamble Pattern detected.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

RX_MPOL

Bit 28: Receiver Manchester Polarity.

ONE

Bit 29: Must Be Set to 1.

DRIFT

Bit 30: Drift Compensation.

LINMR

LIN Mode Register

Offset: 0x54, reset: 0x00000000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLC
rw 		WKUPTYP
rw 		FSDIS
rw 		DLM
rw 		CHKTYP
rw 		CHKDIS
rw 		PARDIS
rw 		NACT
rw
Toggle Fields

NACT

Bits 0-1: LIN Node Action.

Allowed values:
0x0: PUBLISH: The USART transmits the response.
0x1: SUBSCRIBE: The USART receives the response.
0x2: IGNORE: The USART does not transmit and does not receive the response.

PARDIS

Bit 2: Parity Disable.

CHKDIS

Bit 3: Checksum Disable.

CHKTYP

Bit 4: Checksum Type.

DLM

Bit 5: Data Length Mode.

FSDIS

Bit 6: Frame Slot Mode Disable.

WKUPTYP

Bit 7: Wakeup Signal Type.

DLC

Bits 8-15: Data Length Control.

PDCM

Bit 16: PDC Mode.

LINIR

LIN Identifier Register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDCHR
rw
Toggle Fields

IDCHR

Bits 0-7: Identifier Character.

LINBRR

LIN Baud Rate Register

Offset: 0x5c, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINFP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCD
r
Toggle Fields

LINCD

Bits 0-15: Clock Divider after Synchronization.

LINFP

Bits 16-18: Fractional Part after Synchronization.

WPMR

Write Protection Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protection Enable.

WPKEY

Bits 8-31: Write Protection Key.

Allowed values:
0x555341: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

WPSR

Write Protection Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-23: Write Protection Violation Source.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

USART3

0x400a4000: Universal Synchronous Asynchronous Receiver Transmitter 3

112/280 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x0 CR_SPI_MODE
0x4 MR
0x4 MR_SPI_MODE
0x8 IER
0x8 IER_LIN_MODE
0x8 IER_SPI_MODE
0xc IDR
0xc IDR_LIN_MODE
0xc IDR_SPI_MODE
0x10 IMR
0x10 IMR_LIN_MODE
0x10 IMR_SPI_MODE
0x14 CSR
0x14 CSR_LIN_MODE
0x14 CSR_SPI_MODE
0x18 RHR
0x1c THR
0x20 BRGR
0x24 RTOR
0x28 TTGR
0x40 FIDI
0x44 NER
0x4c IF
0x50 MAN
0x54 LINMR
0x58 LINIR
0x5c LINBRR
0xe4 WPMR
0xe8 WPSR
0x100 RPR
0x104 RCR
0x108 TPR
0x10c TCR
0x110 RNPR
0x114 RNCR
0x118 TNPR
0x11c TNCR
0x120 PTCR
0x124 PTSR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINWKUP
w 		LINABT
w 		RTSDIS
w 		RTSEN
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETTO
w 		RSTNACK
w 		RSTIT
w 		SENDA
w 		STTTO
w 		STPBRK
w 		STTBRK
w 		RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

STTBRK

Bit 9: Start Break.

STPBRK

Bit 10: Stop Break.

STTTO

Bit 11: Start Time-out.

SENDA

Bit 12: Send Address.

RSTIT

Bit 13: Reset Iterations.

RSTNACK

Bit 14: Reset Non Acknowledge.

RETTO

Bit 15: Rearm Time-out.

RTSEN

Bit 18: Request to Send Enable.

RTSDIS

Bit 19: Request to Send Disable.

LINABT

Bit 20: Abort LIN Transmission.

LINWKUP

Bit 21: Send LIN Wakeup Signal.

CR_SPI_MODE

Control Register

Offset: 0x0, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCS
w 		FCS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTSTA
w 		TXDIS
w 		TXEN
w 		RXDIS
w 		RXEN
w 		RSTTX
w 		RSTRX
w
Toggle Fields

RSTRX

Bit 2: Reset Receiver.

RSTTX

Bit 3: Reset Transmitter.

RXEN

Bit 4: Receiver Enable.

RXDIS

Bit 5: Receiver Disable.

TXEN

Bit 6: Transmitter Enable.

TXDIS

Bit 7: Transmitter Disable.

RSTSTA

Bit 8: Reset Status Bits.

FCS

Bit 18: Force SPI Chip Select.

RCS

Bit 19: Release SPI Chip Select.

MR

Mode Register

Offset: 0x4, reset: None, access: read-write

6/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ONEBIT
rw 		MODSYNC
rw 		MAN
rw 		FILTER
rw 		MAX_ITERATION
rw 		INVDATA
rw 		VAR_SYNC
rw 		DSNACK
rw 		INACK
rw 		OVER
rw 		CLKO
rw 		MODE9
rw 		MSBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHMODE
rw 		NBSTOP
rw 		PAR
rw 		SYNC
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0x0: NORMAL: Normal mode
0x1: RS485: RS485
0x2: HW_HANDSHAKING: Hardware Handshaking
0x4: IS07816_T_0: IS07816 Protocol: T = 0
0x6: IS07816_T_1: IS07816 Protocol: T = 1
0x8: IRDA: IrDA
0xA: LIN_MASTER: LIN master
0xB: LIN_SLAVE: LIN Slave
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x0: 5_BIT: Character length is 5 bits
0x1: 6_BIT: Character length is 6 bits
0x2: 7_BIT: Character length is 7 bits
0x3: 8_BIT: Character length is 8 bits

SYNC

Bit 8: Synchronous Mode Select.

PAR

Bits 9-11: Parity Type.

Allowed values:
0x0: EVEN: Even parity
0x1: ODD: Odd parity
0x2: SPACE: Parity forced to 0 (Space)
0x3: MARK: Parity forced to 1 (Mark)
0x4: NO: No parity
0x6: MULTIDROP: Multidrop mode

NBSTOP

Bits 12-13: Number of Stop Bits.

Allowed values:
0x0: 1_BIT: 1 stop bit
0x1: 1_5_BIT: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x2: 2_BIT: 2 stop bits

CHMODE

Bits 14-15: Channel Mode.

Allowed values:
0x0: NORMAL: Normal mode
0x1: AUTOMATIC: Automatic Echo. Receiver input is connected to the TXD pin.
0x2: LOCAL_LOOPBACK: Local Loopback. Transmitter output is connected to the Receiver Input.
0x3: REMOTE_LOOPBACK: Remote Loopback. RXD pin is internally connected to the TXD pin.

MSBF

Bit 16: Bit Order.

MODE9

Bit 17: 9-bit Character Length.

CLKO

Bit 18: Clock Output Select.

OVER

Bit 19: Oversampling Mode.

INACK

Bit 20: Inhibit Non Acknowledge.

DSNACK

Bit 21: Disable Successive NACK.

VAR_SYNC

Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter.

INVDATA

Bit 23: Inverted Data.

MAX_ITERATION

Bits 24-26: Maximum Number of Automatic Iteration.

FILTER

Bit 28: Infrared Receive Line Filter.

MAN

Bit 29: Manchester Encoder/Decoder Enable.

MODSYNC

Bit 30: Manchester Synchronization Mode.

ONEBIT

Bit 31: Start Frame Delimiter Selector.

MR_SPI_MODE

Mode Register

Offset: 0x4, reset: None, access: read-write

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRDBT
rw 		CPOL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPHA
rw 		CHRL
rw 		USCLKS
rw 		USART_MODE
rw
Toggle Fields

USART_MODE

Bits 0-3: USART Mode of Operation.

Allowed values:
0xE: SPI_MASTER: SPI master
0xF: SPI_SLAVE: SPI Slave

USCLKS

Bits 4-5: Clock Selection.

Allowed values:
0x0: MCK: master Clock MCK is selected
0x1: DIV: Internal Clock Divided MCK/DIV (DIV=8) is selected
0x3: SCK: Serial Clock SLK is selected

CHRL

Bits 6-7: Character Length.

Allowed values:
0x3: 8_BIT: Character length is 8 bits

CPHA

Bit 8: SPI Clock Phase.

CPOL

Bit 16: SPI Clock Polarity.

WRDBT

Bit 20: Wait Read Data Before Transfer.

IER

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

RXBRK

Bit 2: Receiver Break Interrupt Enable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Enable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Enable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

ITER

Bit 10: Max number of Repetitions Reached Interrupt Enable.

TXBUFE

Bit 11: Buffer Empty Interrupt Enable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Enable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Enable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Enable.

MANE

Bit 24: Manchester Error Interrupt Enable.

IER_LIN_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Enable.

PARE

Bit 7: Parity Error Interrupt Enable.

TIMEOUT

Bit 8: Time-out Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Enable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Enable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Enable.

LINBE

Bit 25: LIN Bus Error Interrupt Enable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Enable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Enable.

LINCE

Bit 28: LIN Checksum Error Interrupt Enable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Enable.

IER_SPI_MODE

Interrupt Enable Register

Offset: 0x8, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Enable.

TXRDY

Bit 1: TXRDY Interrupt Enable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Enable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Enable.

UNRE

Bit 10: SPI Underrun Error Interrupt Enable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IDR

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
w 		CTSIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
w 		RXBUFF
w 		TXBUFE
w 		ITER
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		RXBRK
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

RXBRK

Bit 2: Receiver Break Interrupt Disable.

ENDRX

Bit 3: End of Receive Transfer Interrupt Disable (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Disable (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Enable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Disable.

TXBUFE

Bit 11: Buffer Empty Interrupt Disable (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Disable (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Disable.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Disable.

MANE

Bit 24: Manchester Error Interrupt Disable.

IDR_LIN_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
w 		LINCE
w 		LINIPE
w 		LINISFE
w 		LINBE
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
w 		LINID
w 		LINBK
w 		RXBUFF
w 		TXBUFE
w 		TXEMPTY
w 		TIMEOUT
w 		PARE
w 		FRAME
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

FRAME

Bit 6: Framing Error Interrupt Disable.

PARE

Bit 7: Parity Error Interrupt Disable.

TIMEOUT

Bit 8: Time-out Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Disable.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Disable.

LINTC

Bit 15: LIN Transfer Completed Interrupt Disable.

LINBE

Bit 25: LIN Bus Error Interrupt Disable.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Disable.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Disable.

LINCE

Bit 28: LIN Checksum Error Interrupt Disable.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Disable.

IDR_SPI_MODE

Interrupt Disable Register

Offset: 0xc, reset: None, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
w 		TXBUFE
w 		UNRE
w 		TXEMPTY
w 		OVRE
w 		ENDTX
w 		ENDRX
w 		TXRDY
w 		RXRDY
w
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Disable.

TXRDY

Bit 1: TXRDY Interrupt Disable.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Disable.

TXEMPTY

Bit 9: TXEMPTY Interrupt Disable.

UNRE

Bit 10: SPI Underrun Error Interrupt Disable.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

IMR

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANE
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

RXBRK

Bit 2: Receiver Break Interrupt Mask.

ENDRX

Bit 3: End of Receive Transfer Interrupt Mask (available in all USART modes of operation).

ENDTX

Bit 4: End of Transmit Interrupt Mask (available in all USART modes of operation).

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

ITER

Bit 10: Max Number of Repetitions Reached Interrupt Mask.

TXBUFE

Bit 11: Buffer Empty Interrupt Mask (available in all USART modes of operation).

RXBUFF

Bit 12: Buffer Full Interrupt Mask (available in all USART modes of operation).

NACK

Bit 13: Non Acknowledge Interrupt Mask.

CTSIC

Bit 19: Clear to Send Input Change Interrupt Mask.

MANE

Bit 24: Manchester Error Interrupt Mask.

IMR_LIN_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

FRAME

Bit 6: Framing Error Interrupt Mask.

PARE

Bit 7: Parity Error Interrupt Mask.

TIMEOUT

Bit 8: Time-out Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received Interrupt Mask.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received Interrupt Mask.

LINTC

Bit 15: LIN Transfer Completed Interrupt Mask.

LINBE

Bit 25: LIN Bus Error Interrupt Mask.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error Interrupt Mask.

LINIPE

Bit 27: LIN Identifier Parity Interrupt Mask.

LINCE

Bit 28: LIN Checksum Error Interrupt Mask.

LINSNRE

Bit 29: LIN Slave Not Responding Error Interrupt Mask.

IMR_SPI_MODE

Interrupt Mask Register

Offset: 0x10, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: RXRDY Interrupt Mask.

TXRDY

Bit 1: TXRDY Interrupt Mask.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error Interrupt Mask.

TXEMPTY

Bit 9: TXEMPTY Interrupt Mask.

UNRE

Bit 10: SPI Underrun Error Interrupt Mask.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

CSR

Channel Status Register

Offset: 0x14, reset: None, access: read-only

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MANERR
r 		CTS
r 		CTSIC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r 		RXBUFF
r 		TXBUFE
r 		ITER
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		RXBRK
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

RXBRK

Bit 2: Break Received/End of Break.

ENDRX

Bit 3: End of Receiver Transfer.

ENDTX

Bit 4: End of Transmitter Transfer.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

ITER

Bit 10: Max Number of Repetitions Reached.

TXBUFE

Bit 11: Transmission Buffer Empty.

RXBUFF

Bit 12: Reception Buffer Full.

NACK

Bit 13: Non Acknowledge Interrupt.

CTSIC

Bit 19: Clear to Send Input Change Flag.

CTS

Bit 23: Image of CTS Input.

MANERR

Bit 24: Manchester Error.

CSR_LIN_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINSNRE
r 		LINCE
r 		LINIPE
r 		LINISFE
r 		LINBE
r 		LINBLS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINTC
r 		LINID
r 		LINBK
r 		RXBUFF
r 		TXBUFE
r 		TXEMPTY
r 		TIMEOUT
r 		PARE
r 		FRAME
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

FRAME

Bit 6: Framing Error.

PARE

Bit 7: Parity Error.

TIMEOUT

Bit 8: Receiver Time-out.

TXEMPTY

Bit 9: Transmitter Empty.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

LINBK

Bit 13: LIN Break Sent or LIN Break Received.

LINID

Bit 14: LIN Identifier Sent or LIN Identifier Received.

LINTC

Bit 15: LIN Transfer Completed.

LINBLS

Bit 23: LIN Bus Line Status.

LINBE

Bit 25: LIN Bit Error.

LINISFE

Bit 26: LIN Inconsistent Synch Field Error.

LINIPE

Bit 27: LIN Identifier Parity Error.

LINCE

Bit 28: LIN Checksum Error.

LINSNRE

Bit 29: LIN Slave Not Responding Error.

CSR_SPI_MODE

Channel Status Register

Offset: 0x14, reset: None, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXBUFF
r 		TXBUFE
r 		UNRE
r 		TXEMPTY
r 		OVRE
r 		ENDTX
r 		ENDRX
r 		TXRDY
r 		RXRDY
r
Toggle Fields

RXRDY

Bit 0: Receiver Ready.

TXRDY

Bit 1: Transmitter Ready.

ENDRX

Bit 3: None.

ENDTX

Bit 4: None.

OVRE

Bit 5: Overrun Error.

TXEMPTY

Bit 9: Transmitter Empty.

UNRE

Bit 10: Underrun Error.

TXBUFE

Bit 11: None.

RXBUFF

Bit 12: None.

RHR

Receive Holding Register

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSYNH
r 		RXCHR
r
Toggle Fields

RXCHR

Bits 0-8: Received Character.

RXSYNH

Bit 15: Received Sync.

THR

Transmit Holding Register

Offset: 0x1c, reset: None, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXSYNH
w 		TXCHR
w
Toggle Fields

TXCHR

Bits 0-8: Character to be Transmitted.

TXSYNH

Bit 15: Sync Field to be Transmitted.

BRGR

Baud Rate Generator Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
rw
Toggle Fields

CD

Bits 0-15: Clock Divider.

FP

Bits 16-18: Fractional Part.

RTOR

Receiver Time-out Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
rw
Toggle Fields

TO

Bits 0-16: Time-out Value.

TTGR

Transmitter Timeguard Register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw
Toggle Fields

TG

Bits 0-7: Timeguard Value.

FIDI

FI DI Ratio Register

Offset: 0x40, reset: 0x00000174, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI_DI_RATIO
rw
Toggle Fields

FI_DI_RATIO

Bits 0-10: FI Over DI Ratio Value.

NER

Number of Errors Register

Offset: 0x44, reset: None, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NB_ERRORS
r
Toggle Fields

NB_ERRORS

Bits 0-7: Number of Errors.

IF

IrDA Filter Register

Offset: 0x4c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRDA_FILTER
rw
Toggle Fields

IRDA_FILTER

Bits 0-7: IrDA Filter.

MAN

Manchester Configuration Register

Offset: 0x50, reset: 0xB0011004, access: read-write

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRIFT
rw 		ONE
rw 		RX_MPOL
rw 		RX_PP
rw 		RX_PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_MPOL
rw 		TX_PP
rw 		TX_PL
rw
Toggle Fields

TX_PL

Bits 0-3: Transmitter Preamble Length.

TX_PP

Bits 8-9: Transmitter Preamble Pattern.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

TX_MPOL

Bit 12: Transmitter Manchester Polarity.

RX_PL

Bits 16-19: Receiver Preamble Length.

RX_PP

Bits 24-25: Receiver Preamble Pattern detected.

Allowed values:
0x0: ALL_ONE: The preamble is composed of '1's
0x1: ALL_ZERO: The preamble is composed of '0's
0x2: ZERO_ONE: The preamble is composed of '01's
0x3: ONE_ZERO: The preamble is composed of '10's

RX_MPOL

Bit 28: Receiver Manchester Polarity.

ONE

Bit 29: Must Be Set to 1.

DRIFT

Bit 30: Drift Compensation.

LINMR

LIN Mode Register

Offset: 0x54, reset: 0x00000000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLC
rw 		WKUPTYP
rw 		FSDIS
rw 		DLM
rw 		CHKTYP
rw 		CHKDIS
rw 		PARDIS
rw 		NACT
rw
Toggle Fields

NACT

Bits 0-1: LIN Node Action.

Allowed values:
0x0: PUBLISH: The USART transmits the response.
0x1: SUBSCRIBE: The USART receives the response.
0x2: IGNORE: The USART does not transmit and does not receive the response.

PARDIS

Bit 2: Parity Disable.

CHKDIS

Bit 3: Checksum Disable.

CHKTYP

Bit 4: Checksum Type.

DLM

Bit 5: Data Length Mode.

FSDIS

Bit 6: Frame Slot Mode Disable.

WKUPTYP

Bit 7: Wakeup Signal Type.

DLC

Bits 8-15: Data Length Control.

PDCM

Bit 16: PDC Mode.

LINIR

LIN Identifier Register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDCHR
rw
Toggle Fields

IDCHR

Bits 0-7: Identifier Character.

LINBRR

LIN Baud Rate Register

Offset: 0x5c, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINFP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCD
r
Toggle Fields

LINCD

Bits 0-15: Clock Divider after Synchronization.

LINFP

Bits 16-18: Fractional Part after Synchronization.

WPMR

Write Protection Mode Register

Offset: 0xe4, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPKEY
rw 		WPEN
rw
Toggle Fields

WPEN

Bit 0: Write Protection Enable.

WPKEY

Bits 8-31: Write Protection Key.

Allowed values:
0x555341: PASSWD: Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

WPSR

Write Protection Status Register

Offset: 0xe8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WPVSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPVSRC
r 		WPVS
r
Toggle Fields

WPVS

Bit 0: Write Protection Violation Status.

WPVSRC

Bits 8-23: Write Protection Violation Source.

RPR

Receive Pointer Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPTR
rw
Toggle Fields

RXPTR

Bits 0-31: Receive Pointer Register.

RCR

Receive Counter Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCTR
rw
Toggle Fields

RXCTR

Bits 0-15: Receive Counter Register.

TPR

Transmit Pointer Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPTR
rw
Toggle Fields

TXPTR

Bits 0-31: Transmit Counter Register.

TCR

Transmit Counter Register

Offset: 0x10c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCTR
rw
Toggle Fields

TXCTR

Bits 0-15: Transmit Counter Register.

RNPR

Receive Next Pointer Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNPTR
rw
Toggle Fields

RXNPTR

Bits 0-31: Receive Next Pointer.

RNCR

Receive Next Counter Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXNCTR
rw
Toggle Fields

RXNCTR

Bits 0-15: Receive Next Counter.

TNPR

Transmit Next Pointer Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXNPTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNPTR
rw
Toggle Fields

TXNPTR

Bits 0-31: Transmit Next Pointer.

TNCR

Transmit Next Counter Register

Offset: 0x11c, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXNCTR
rw
Toggle Fields

TXNCTR

Bits 0-15: Transmit Counter Next.

PTCR

Transfer Control Register

Offset: 0x120, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTDIS
w 		TXTEN
w 		RXTDIS
w 		RXTEN
w
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

RXTDIS

Bit 1: Receiver Transfer Disable.

TXTEN

Bit 8: Transmitter Transfer Enable.

TXTDIS

Bit 9: Transmitter Transfer Disable.

PTSR

Transfer Status Register

Offset: 0x124, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTEN
r 		RXTEN
r
Toggle Fields

RXTEN

Bit 0: Receiver Transfer Enable.

TXTEN

Bit 8: Transmitter Transfer Enable.

WDT

0x400e1a50: Watchdog Timer

3/12 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 MR
0x8 SR

CR

Control Register

Offset: 0x0, reset: None, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDRSTT
w
Toggle Fields

WDRSTT

Bit 0: Watchdog Restart.

KEY

Bits 24-31: Password..

Allowed values:
0xA5: PASSWD: Writing any other value in this field aborts the write operation.

MR

Mode Register

Offset: 0x4, reset: 0x3FFF2FFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDIDLEHLT
rw 		WDDBGHLT
rw 		WDD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDDIS
rw 		WDRPROC
rw 		WDRSTEN
rw 		WDFIEN
rw 		WDV
rw
Toggle Fields

WDV

Bits 0-11: Watchdog Counter Value.

WDFIEN

Bit 12: Watchdog Fault Interrupt Enable.

WDRSTEN

Bit 13: Watchdog Reset Enable.

WDRPROC

Bit 14: Watchdog Reset Processor.

WDDIS

Bit 15: Watchdog Disable.

WDD

Bits 16-27: Watchdog Delta Value.

WDDBGHLT

Bit 28: Watchdog Debug Halt.

WDIDLEHLT

Bit 29: Watchdog Idle Halt.

SR

Status Register

Offset: 0x8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDERR
r 		WDUNF
r
Toggle Fields

WDUNF

Bit 0: Watchdog Underflow.

WDERR

Bit 1: Watchdog Error.